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drm/nouveau/bsp,vp: switch to instanced constructor 

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
This commit is contained in:
Ben Skeggs 2021-02-04 08:33:53 +10:00
parent d07be5d788
commit fcc08a7c0d
13 changed files with 40 additions and 42 deletions
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4
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
View File

@ -60,7 +60,6 @@ struct nvkm_device {
struct notifier_block nb;
} acpi;
struct nvkm_engine *bsp;
struct nvkm_engine *ce[9];
struct nvkm_engine *cipher;
struct nvkm_disp *disp;
@ -81,7 +80,6 @@ struct nvkm_device {
struct nvkm_sec2 *sec2;
struct nvkm_sw *sw;
struct nvkm_engine *vic;
struct nvkm_engine *vp;
#define NVKM_LAYOUT_ONCE(type,data,ptr) data *ptr;
#define NVKM_LAYOUT_INST(type,data,ptr,cnt) data *ptr[cnt];
@ -123,7 +121,6 @@ struct nvkm_device_chip {
#undef NVKM_LAYOUT_INST
#undef NVKM_LAYOUT_ONCE
int (*bsp )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*ce[9] )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*cipher )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*disp )(struct nvkm_device *, int idx, struct nvkm_disp **);
@ -144,7 +141,6 @@ struct nvkm_device_chip {
int (*sec2 )(struct nvkm_device *, int idx, struct nvkm_sec2 **);
int (*sw )(struct nvkm_device *, int idx, struct nvkm_sw **);
int (*vic )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*vp )(struct nvkm_device *, int idx, struct nvkm_engine **);
};
struct nvkm_device *nvkm_device_find(u64 name);

8
drivers/gpu/drm/nouveau/include/nvkm/core/engine.h
View File

@ -47,8 +47,12 @@ struct nvkm_engine_func {
struct nvkm_sclass sclass[];
};
int nvkm_engine_ctor(const struct nvkm_engine_func *, struct nvkm_device *,
int index, bool enable, struct nvkm_engine *);
int nvkm_engine_ctor_(const struct nvkm_engine_func *, bool old, struct nvkm_device *,
enum nvkm_subdev_type, int inst, bool enable, struct nvkm_engine *);
#define nvkm_engine_ctor_o(f,d,i, e,s) nvkm_engine_ctor_((f), true, (d), (i), -1 , (e), (s))
#define nvkm_engine_ctor_n(f,d,t,i,e,s) nvkm_engine_ctor_((f), false, (d), (t), (i), (e), (s))
#define nvkm_engine_ctor__(_1,_2,_3,_4,_5,_6,IMPL,...) IMPL
#define nvkm_engine_ctor(A...) nvkm_engine_ctor__(A, nvkm_engine_ctor_n, nvkm_engine_ctor_o)(A)
int nvkm_engine_new_(const struct nvkm_engine_func *, struct nvkm_device *,
int index, bool enable, struct nvkm_engine **);
struct nvkm_engine *nvkm_engine_ref(struct nvkm_engine *);

3
drivers/gpu/drm/nouveau/include/nvkm/core/layout.h
View File

@ -24,3 +24,6 @@ NVKM_LAYOUT_ONCE(NVKM_SUBDEV_ICCSENSE, struct nvkm_iccsense, iccsense)
NVKM_LAYOUT_ONCE(NVKM_SUBDEV_THERM , struct nvkm_therm , therm)
NVKM_LAYOUT_ONCE(NVKM_SUBDEV_CLK , struct nvkm_clk , clk)
NVKM_LAYOUT_ONCE(NVKM_SUBDEV_GSP , struct nvkm_gsp , gsp)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_BSP , struct nvkm_engine , bsp)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_VP , struct nvkm_engine , vp)

2
drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h
View File

@ -2,5 +2,5 @@
#ifndef __NVKM_BSP_H__
#define __NVKM_BSP_H__
#include <engine/xtensa.h>
int g84_bsp_new(struct nvkm_device *, int, struct nvkm_engine **);
int g84_bsp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
#endif

2
drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h
View File

@ -2,5 +2,5 @@
#ifndef __NVKM_VP_H__
#define __NVKM_VP_H__
#include <engine/xtensa.h>
int g84_vp_new(struct nvkm_device *, int, struct nvkm_engine **);
int g84_vp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
#endif

2
drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h
View File

@ -13,7 +13,7 @@ struct nvkm_xtensa {
};
int nvkm_xtensa_new_(const struct nvkm_xtensa_func *, struct nvkm_device *,
int index, bool enable, u32 addr, struct nvkm_engine **);
enum nvkm_subdev_type, int, bool enable, u32 addr, struct nvkm_engine **);
struct nvkm_xtensa_func {
u32 fifo_val;

7
drivers/gpu/drm/nouveau/nvkm/core/engine.c
View File

@ -176,11 +176,10 @@ nvkm_engine = {
};
int
nvkm_engine_ctor(const struct nvkm_engine_func *func,
struct nvkm_device *device, int index, bool enable,
struct nvkm_engine *engine)
nvkm_engine_ctor_(const struct nvkm_engine_func *func, bool old, struct nvkm_device *device,
enum nvkm_subdev_type type, int inst, bool enable, struct nvkm_engine *engine)
{
nvkm_subdev_ctor(&nvkm_engine, device, index, &engine->subdev);
nvkm_subdev_ctor_(&nvkm_engine, old, device, type, inst, &engine->subdev);
engine->func = func;
refcount_set(&engine->use.refcount, 0);
mutex_init(&engine->use.mutex);

2
drivers/gpu/drm/nouveau/nvkm/core/subdev.c
View File

@ -33,7 +33,6 @@ nvkm_subdev_type[NVKM_SUBDEV_NR] = {
#include <core/layout.h>
#undef NVKM_LAYOUT_ONCE
#undef NVKM_LAYOUT_INST
[NVKM_ENGINE_BSP ] = "bsp",
[NVKM_ENGINE_CE0 ] = "ce0",
[NVKM_ENGINE_CE1 ] = "ce1",
[NVKM_ENGINE_CE2 ] = "ce2",
@ -66,7 +65,6 @@ nvkm_subdev_type[NVKM_SUBDEV_NR] = {
[NVKM_ENGINE_SEC2 ] = "sec2",
[NVKM_ENGINE_SW ] = "sw",
[NVKM_ENGINE_VIC ] = "vic",
[NVKM_ENGINE_VP ] = "vp",
};
void

5
drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c
View File

@ -36,8 +36,9 @@ g84_bsp = {
};
int
g84_bsp_new(struct nvkm_device *device, int index, struct nvkm_engine **pengine)
g84_bsp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine)
{
return nvkm_xtensa_new_(&g84_bsp, device, index,
return nvkm_xtensa_new_(&g84_bsp, device, type, inst,
device->chipset != 0x92, 0x103000, pengine);
}

26
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View File

@ -934,7 +934,7 @@ nv84_chipset = {
.therm = { 0x00000001, g84_therm_new },
.timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, nv40_volt_new },
.bsp = g84_bsp_new,
.bsp = { 0x00000001, g84_bsp_new },
.cipher = g84_cipher_new,
.disp = g84_disp_new,
.dma = nv50_dma_new,
@ -943,7 +943,7 @@ nv84_chipset = {
.mpeg = g84_mpeg_new,
.pm = g84_pm_new,
.sw = nv50_sw_new,
.vp = g84_vp_new,
.vp = { 0x00000001, g84_vp_new },
};
static const struct nvkm_device_chip
@ -966,7 +966,7 @@ nv86_chipset = {
.therm = { 0x00000001, g84_therm_new },
.timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, nv40_volt_new },
.bsp = g84_bsp_new,
.bsp = { 0x00000001, g84_bsp_new },
.cipher = g84_cipher_new,
.disp = g84_disp_new,
.dma = nv50_dma_new,
@ -975,7 +975,7 @@ nv86_chipset = {
.mpeg = g84_mpeg_new,
.pm = g84_pm_new,
.sw = nv50_sw_new,
.vp = g84_vp_new,
.vp = { 0x00000001, g84_vp_new },
};
static const struct nvkm_device_chip
@ -998,7 +998,7 @@ nv92_chipset = {
.therm = { 0x00000001, g84_therm_new },
.timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, nv40_volt_new },
.bsp = g84_bsp_new,
.bsp = { 0x00000001, g84_bsp_new },
.cipher = g84_cipher_new,
.disp = g84_disp_new,
.dma = nv50_dma_new,
@ -1007,7 +1007,7 @@ nv92_chipset = {
.mpeg = g84_mpeg_new,
.pm = g84_pm_new,
.sw = nv50_sw_new,
.vp = g84_vp_new,
.vp = { 0x00000001, g84_vp_new },
};
static const struct nvkm_device_chip
@ -1030,7 +1030,7 @@ nv94_chipset = {
.therm = { 0x00000001, g84_therm_new },
.timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, nv40_volt_new },
.bsp = g84_bsp_new,
.bsp = { 0x00000001, g84_bsp_new },
.cipher = g84_cipher_new,
.disp = g94_disp_new,
.dma = nv50_dma_new,
@ -1039,7 +1039,7 @@ nv94_chipset = {
.mpeg = g84_mpeg_new,
.pm = g84_pm_new,
.sw = nv50_sw_new,
.vp = g84_vp_new,
.vp = { 0x00000001, g84_vp_new },
};
static const struct nvkm_device_chip
@ -1062,7 +1062,7 @@ nv96_chipset = {
.therm = { 0x00000001, g84_therm_new },
.timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, nv40_volt_new },
.bsp = g84_bsp_new,
.bsp = { 0x00000001, g84_bsp_new },
.cipher = g84_cipher_new,
.disp = g94_disp_new,
.dma = nv50_dma_new,
@ -1071,7 +1071,7 @@ nv96_chipset = {
.mpeg = g84_mpeg_new,
.pm = g84_pm_new,
.sw = nv50_sw_new,
.vp = g84_vp_new,
.vp = { 0x00000001, g84_vp_new },
};
static const struct nvkm_device_chip
@ -1126,7 +1126,7 @@ nva0_chipset = {
.therm = { 0x00000001, g84_therm_new },
.timer = { 0x00000001, nv41_timer_new },
.volt = { 0x00000001, nv40_volt_new },
.bsp = g84_bsp_new,
.bsp = { 0x00000001, g84_bsp_new },
.cipher = g84_cipher_new,
.disp = gt200_disp_new,
.dma = nv50_dma_new,
@ -1135,7 +1135,7 @@ nva0_chipset = {
.mpeg = g84_mpeg_new,
.pm = gt200_pm_new,
.sw = nv50_sw_new,
.vp = g84_vp_new,
.vp = { 0x00000001, g84_vp_new },
};
static const struct nvkm_device_chip
@ -3248,7 +3248,6 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
#include <core/layout.h>
#undef NVKM_LAYOUT_INST
#undef NVKM_LAYOUT_ONCE
_(NVKM_ENGINE_BSP , bsp);
_(NVKM_ENGINE_CE0 , ce[0]);
_(NVKM_ENGINE_CE1 , ce[1]);
_(NVKM_ENGINE_CE2 , ce[2]);
@ -3281,7 +3280,6 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
_(NVKM_ENGINE_SEC2 , sec2);
_(NVKM_ENGINE_SW , sw);
_(NVKM_ENGINE_VIC , vic);
_(NVKM_ENGINE_VP , vp);
default:
WARN_ON(1);
continue;

6
drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c
View File

@ -36,8 +36,8 @@ g84_vp = {
};
int
g84_vp_new(struct nvkm_device *device, int index, struct nvkm_engine **pengine)
g84_vp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine)
{
return nvkm_xtensa_new_(&g84_vp, device, index,
true, 0x00f000, pengine);
return nvkm_xtensa_new_(&g84_vp, device, type, inst, true, 0x00f000, pengine);
}

9
drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c
View File

@ -175,9 +175,9 @@ nvkm_xtensa = {
};
int
nvkm_xtensa_new_(const struct nvkm_xtensa_func *func,
struct nvkm_device *device, int index, bool enable,
u32 addr, struct nvkm_engine **pengine)
nvkm_xtensa_new_(const struct nvkm_xtensa_func *func, struct nvkm_device *device,
enum nvkm_subdev_type type, int inst, bool enable, u32 addr,
struct nvkm_engine **pengine)
{
struct nvkm_xtensa *xtensa;
@ -187,6 +187,5 @@ nvkm_xtensa_new_(const struct nvkm_xtensa_func *func,
xtensa->addr = addr;
*pengine = &xtensa->engine;
return nvkm_engine_ctor(&nvkm_xtensa, device, index,
enable, &xtensa->engine);
return nvkm_engine_ctor(&nvkm_xtensa, device, type, inst, enable, &xtensa->engine);
}

6
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c
View File

@ -36,15 +36,15 @@ g84_devinit_disable(struct nvkm_devinit *init)
if (!(r001540 & 0x40000000)) {
disable |= (1ULL << NVKM_ENGINE_MPEG);
disable |= (1ULL << NVKM_ENGINE_VP);
disable |= (1ULL << NVKM_ENGINE_BSP);
nvkm_subdev_disable(device, NVKM_ENGINE_VP, 0);
nvkm_subdev_disable(device, NVKM_ENGINE_BSP, 0);
disable |= (1ULL << NVKM_ENGINE_CIPHER);
}
if (!(r00154c & 0x00000004))
disable |= (1ULL << NVKM_ENGINE_DISP);
if (!(r00154c & 0x00000020))
disable |= (1ULL << NVKM_ENGINE_BSP);
nvkm_subdev_disable(device, NVKM_ENGINE_BSP, 0);
if (!(r00154c & 0x00000040))
disable |= (1ULL << NVKM_ENGINE_CIPHER);