reset: npcm: Add NPCM8XX support
Updated the NPCM reset driver to add support for Nuvoton BMC NPCM8XX SoC. As part of adding NPCM8XX support: - Add NPCM8XX specific compatible string. - Add NPCM8XX USB reset. - Add data to handle architecture-specific reset parameters. - Some of the Reset Id and number of resets are different from NPCM7XX. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Tomer Maimon
Arnd Bergmann
parent
85331f56cb
commit
fc5d2a2f4a
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@ -17,13 +17,20 @@
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/* NPCM7xx GCR registers */
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#define NPCM_MDLR_OFFSET 0x7C
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#define NPCM_MDLR_USBD0 BIT(9)
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#define NPCM_MDLR_USBD1 BIT(8)
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#define NPCM_MDLR_USBD2_4 BIT(21)
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#define NPCM_MDLR_USBD5_9 BIT(22)
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#define NPCM7XX_MDLR_USBD0 BIT(9)
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#define NPCM7XX_MDLR_USBD1 BIT(8)
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#define NPCM7XX_MDLR_USBD2_4 BIT(21)
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#define NPCM7XX_MDLR_USBD5_9 BIT(22)
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/* NPCM8xx MDLR bits */
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#define NPCM8XX_MDLR_USBD0_3 BIT(9)
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#define NPCM8XX_MDLR_USBD4_7 BIT(22)
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#define NPCM8XX_MDLR_USBD8 BIT(24)
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#define NPCM8XX_MDLR_USBD9 BIT(21)
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#define NPCM_USB1PHYCTL_OFFSET 0x140
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#define NPCM_USB2PHYCTL_OFFSET 0x144
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#define NPCM_USB3PHYCTL_OFFSET 0x148
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#define NPCM_USBXPHYCTL_RS BIT(28)
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/* NPCM7xx Reset registers */
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@ -49,12 +56,38 @@
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#define NPCM_IPSRST3_USBPHY1 BIT(24)
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#define NPCM_IPSRST3_USBPHY2 BIT(25)
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#define NPCM_IPSRST4 0x74
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#define NPCM_IPSRST4_USBPHY3 BIT(25)
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#define NPCM_IPSRST4_USB_HOST2 BIT(31)
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#define NPCM_RC_RESETS_PER_REG 32
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#define NPCM_MASK_RESETS GENMASK(4, 0)
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enum {
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BMC_NPCM7XX = 0,
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BMC_NPCM8XX,
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};
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static const u32 npxm7xx_ipsrst[] = {NPCM_IPSRST1, NPCM_IPSRST2, NPCM_IPSRST3};
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static const u32 npxm8xx_ipsrst[] = {NPCM_IPSRST1, NPCM_IPSRST2, NPCM_IPSRST3,
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NPCM_IPSRST4};
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struct npcm_reset_info {
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u32 bmc_id;
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u32 num_ipsrst;
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const u32 *ipsrst;
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};
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static const struct npcm_reset_info npxm7xx_reset_info[] = {
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{.bmc_id = BMC_NPCM7XX, .num_ipsrst = 3, .ipsrst = npxm7xx_ipsrst}};
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static const struct npcm_reset_info npxm8xx_reset_info[] = {
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{.bmc_id = BMC_NPCM8XX, .num_ipsrst = 4, .ipsrst = npxm8xx_ipsrst}};
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struct npcm_rc_data {
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struct reset_controller_dev rcdev;
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struct notifier_block restart_nb;
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const struct npcm_reset_info *info;
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struct regmap *gcr_regmap;
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u32 sw_reset_number;
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void __iomem *base;
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spinlock_t lock;
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@ -120,14 +153,24 @@ static int npcm_rc_status(struct reset_controller_dev *rcdev,
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static int npcm_reset_xlate(struct reset_controller_dev *rcdev,
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const struct of_phandle_args *reset_spec)
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{
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struct npcm_rc_data *rc = to_rc_data(rcdev);
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unsigned int offset, bit;
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bool offset_found = false;
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int off_num;
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offset = reset_spec->args[0];
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if (offset != NPCM_IPSRST1 && offset != NPCM_IPSRST2 &&
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offset != NPCM_IPSRST3) {
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for (off_num = 0 ; off_num < rc->info->num_ipsrst ; off_num++) {
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if (offset == rc->info->ipsrst[off_num]) {
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offset_found = true;
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break;
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}
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}
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if (!offset_found) {
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dev_err(rcdev->dev, "Error reset register (0x%x)\n", offset);
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return -EINVAL;
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}
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bit = reset_spec->args[1];
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if (bit >= NPCM_RC_RESETS_PER_REG) {
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dev_err(rcdev->dev, "Error reset number (%d)\n", bit);
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@ -138,49 +181,29 @@ static int npcm_reset_xlate(struct reset_controller_dev *rcdev,
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}
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static const struct of_device_id npcm_rc_match[] = {
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{ .compatible = "nuvoton,npcm750-reset" },
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{ .compatible = "nuvoton,npcm750-reset", .data = &npxm7xx_reset_info},
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{ .compatible = "nuvoton,npcm845-reset", .data = &npxm8xx_reset_info},
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{ }
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};
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/*
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* The following procedure should be observed in USB PHY, USB device and
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* USB host initialization at BMC boot
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*/
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static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc)
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static void npcm_usb_reset_npcm7xx(struct npcm_rc_data *rc)
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{
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u32 mdlr, iprst1, iprst2, iprst3;
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struct device *dev = &pdev->dev;
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struct regmap *gcr_regmap;
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u32 ipsrst1_bits = 0;
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u32 ipsrst2_bits = NPCM_IPSRST2_USB_HOST;
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u32 ipsrst3_bits = 0;
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const char *gcr_dt;
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gcr_dt = (const char *)
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of_match_device(dev->driver->of_match_table, dev)->data;
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gcr_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "nuvoton,sysgcr");
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if (IS_ERR(gcr_regmap)) {
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dev_warn(&pdev->dev, "Failed to find nuvoton,sysgcr property, please update the device tree\n");
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dev_info(&pdev->dev, "Using nuvoton,npcm750-gcr for Poleg backward compatibility\n");
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gcr_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");
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if (IS_ERR(gcr_regmap)) {
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dev_err(&pdev->dev, "Failed to find nuvoton,npcm750-gcr");
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return PTR_ERR(gcr_regmap);
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}
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}
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/* checking which USB device is enabled */
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regmap_read(gcr_regmap, NPCM_MDLR_OFFSET, &mdlr);
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if (!(mdlr & NPCM_MDLR_USBD0))
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regmap_read(rc->gcr_regmap, NPCM_MDLR_OFFSET, &mdlr);
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if (!(mdlr & NPCM7XX_MDLR_USBD0))
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ipsrst3_bits |= NPCM_IPSRST3_USBD0;
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if (!(mdlr & NPCM_MDLR_USBD1))
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if (!(mdlr & NPCM7XX_MDLR_USBD1))
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ipsrst1_bits |= NPCM_IPSRST1_USBD1;
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if (!(mdlr & NPCM_MDLR_USBD2_4))
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if (!(mdlr & NPCM7XX_MDLR_USBD2_4))
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ipsrst1_bits |= (NPCM_IPSRST1_USBD2 |
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NPCM_IPSRST1_USBD3 |
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NPCM_IPSRST1_USBD4);
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if (!(mdlr & NPCM_MDLR_USBD0)) {
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if (!(mdlr & NPCM7XX_MDLR_USBD0)) {
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ipsrst1_bits |= (NPCM_IPSRST1_USBD5 |
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NPCM_IPSRST1_USBD6);
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ipsrst3_bits |= (NPCM_IPSRST3_USBD7 |
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@ -203,9 +226,9 @@ static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc)
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writel(iprst3, rc->base + NPCM_IPSRST3);
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/* clear USB PHY RS bit */
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regmap_update_bits(gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
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regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
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NPCM_USBXPHYCTL_RS, 0);
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regmap_update_bits(gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
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regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
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NPCM_USBXPHYCTL_RS, 0);
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/* deassert reset USB PHY */
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@ -215,9 +238,9 @@ static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc)
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udelay(50);
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/* set USB PHY RS bit */
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regmap_update_bits(gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
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regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
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NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
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regmap_update_bits(gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
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regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
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NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
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/* deassert reset USB devices*/
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@ -228,6 +251,118 @@ static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc)
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writel(iprst1, rc->base + NPCM_IPSRST1);
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writel(iprst2, rc->base + NPCM_IPSRST2);
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writel(iprst3, rc->base + NPCM_IPSRST3);
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}
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static void npcm_usb_reset_npcm8xx(struct npcm_rc_data *rc)
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{
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u32 mdlr, iprst1, iprst2, iprst3, iprst4;
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u32 ipsrst1_bits = 0;
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u32 ipsrst2_bits = NPCM_IPSRST2_USB_HOST;
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u32 ipsrst3_bits = 0;
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u32 ipsrst4_bits = NPCM_IPSRST4_USB_HOST2 | NPCM_IPSRST4_USBPHY3;
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/* checking which USB device is enabled */
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regmap_read(rc->gcr_regmap, NPCM_MDLR_OFFSET, &mdlr);
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if (!(mdlr & NPCM8XX_MDLR_USBD0_3)) {
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ipsrst3_bits |= NPCM_IPSRST3_USBD0;
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ipsrst1_bits |= (NPCM_IPSRST1_USBD1 |
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NPCM_IPSRST1_USBD2 |
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NPCM_IPSRST1_USBD3);
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}
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if (!(mdlr & NPCM8XX_MDLR_USBD4_7)) {
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ipsrst1_bits |= (NPCM_IPSRST1_USBD4 |
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NPCM_IPSRST1_USBD5 |
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NPCM_IPSRST1_USBD6);
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ipsrst3_bits |= NPCM_IPSRST3_USBD7;
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}
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if (!(mdlr & NPCM8XX_MDLR_USBD8))
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ipsrst3_bits |= NPCM_IPSRST3_USBD8;
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if (!(mdlr & NPCM8XX_MDLR_USBD9))
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ipsrst3_bits |= NPCM_IPSRST3_USBD9;
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/* assert reset USB PHY and USB devices */
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iprst1 = readl(rc->base + NPCM_IPSRST1);
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iprst2 = readl(rc->base + NPCM_IPSRST2);
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iprst3 = readl(rc->base + NPCM_IPSRST3);
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iprst4 = readl(rc->base + NPCM_IPSRST4);
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iprst1 |= ipsrst1_bits;
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iprst2 |= ipsrst2_bits;
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iprst3 |= (ipsrst3_bits | NPCM_IPSRST3_USBPHY1 |
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NPCM_IPSRST3_USBPHY2);
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iprst2 |= ipsrst4_bits;
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writel(iprst1, rc->base + NPCM_IPSRST1);
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writel(iprst2, rc->base + NPCM_IPSRST2);
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writel(iprst3, rc->base + NPCM_IPSRST3);
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writel(iprst4, rc->base + NPCM_IPSRST4);
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/* clear USB PHY RS bit */
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regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
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NPCM_USBXPHYCTL_RS, 0);
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regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
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NPCM_USBXPHYCTL_RS, 0);
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regmap_update_bits(rc->gcr_regmap, NPCM_USB3PHYCTL_OFFSET,
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NPCM_USBXPHYCTL_RS, 0);
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/* deassert reset USB PHY */
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iprst3 &= ~(NPCM_IPSRST3_USBPHY1 | NPCM_IPSRST3_USBPHY2);
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writel(iprst3, rc->base + NPCM_IPSRST3);
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iprst4 &= ~NPCM_IPSRST4_USBPHY3;
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writel(iprst4, rc->base + NPCM_IPSRST4);
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/* set USB PHY RS bit */
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regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
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NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
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regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
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NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
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regmap_update_bits(rc->gcr_regmap, NPCM_USB3PHYCTL_OFFSET,
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NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
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/* deassert reset USB devices*/
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iprst1 &= ~ipsrst1_bits;
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iprst2 &= ~ipsrst2_bits;
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iprst3 &= ~ipsrst3_bits;
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iprst4 &= ~ipsrst4_bits;
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writel(iprst1, rc->base + NPCM_IPSRST1);
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writel(iprst2, rc->base + NPCM_IPSRST2);
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writel(iprst3, rc->base + NPCM_IPSRST3);
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writel(iprst4, rc->base + NPCM_IPSRST4);
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}
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/*
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* The following procedure should be observed in USB PHY, USB device and
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* USB host initialization at BMC boot
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*/
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static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc)
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{
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struct device *dev = &pdev->dev;
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rc->gcr_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "nuvoton,sysgcr");
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if (IS_ERR(rc->gcr_regmap)) {
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dev_warn(&pdev->dev, "Failed to find nuvoton,sysgcr property, please update the device tree\n");
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dev_info(&pdev->dev, "Using nuvoton,npcm750-gcr for Poleg backward compatibility\n");
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rc->gcr_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");
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if (IS_ERR(rc->gcr_regmap)) {
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dev_err(&pdev->dev, "Failed to find nuvoton,npcm750-gcr");
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return PTR_ERR(rc->gcr_regmap);
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}
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}
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rc->info = (const struct npcm_reset_info *)
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of_match_device(dev->driver->of_match_table, dev)->data;
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switch (rc->info->bmc_id) {
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case BMC_NPCM7XX:
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npcm_usb_reset_npcm7xx(rc);
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break;
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case BMC_NPCM8XX:
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npcm_usb_reset_npcm8xx(rc);
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break;
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default:
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return -ENODEV;
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}
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return 0;
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}
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