Raw NAND controller driver fixes:
* meson: - Invalidate cache on polling ECC bit - Initialize struct with zeroes * nandsim: Artificially prevent sequential page reads ECC engine driver fixes: * mxic-ecc: Fix mxic_ecc_data_xfer_wait_for_completion() when irq is used Binging fixes: * jedec,spi-nor: Document CPOL/CPHA support -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEE9HuaYnbmDhq/XIDIJWrqGEe9VoQFAmQhTz0ACgkQJWrqGEe9 VoQ4pQf/RFWoA3FVAWZAakknPFDlCw7si1zmtvLzRDEJ9vqWpYpcs0jCeY0nFryV FgeCZC67BeEIYO/o2Wb/6iZtlWQV0CIsOpdj9Nx7TfUBJC3ZheU0bU3uZnSC6m96 rwJ55QFrA1JIbH0OBYEjq3Spkf3A4WnYTOEc+JxV1JjYD4JcWa82UgP2qHQc7pIr tTgjvgWNvDYxCeHk2a79cwMbS5roKi8FKHnGHtAfjDoFvYYGeSM9M0XTUfpneHRC PlpVnNwzwy+eEqo9tlvFCAOgyiZL/+Rqc/AE5/CxM7C8BTjccCFn8Hw2eVh7kkf1 PhigYZtLJOFFfNrOFdUeOlE2i8E3Bw== =l91F -----END PGP SIGNATURE----- Merge tag 'mtd/fixes-for-6.3-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull MTD fixes from Miquel Raynal: "Raw NAND controller driver fixes: - meson: - Invalidate cache on polling ECC bit - Initialize struct with zeroes - nandsim: Artificially prevent sequential page reads ECC engine driver fixes: - mxic-ecc: Fix mxic_ecc_data_xfer_wait_for_completion() when irq is used Binging fixes: - jedec,spi-nor: Document CPOL/CPHA support" * tag 'mtd/fixes-for-6.3-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: mtd: rawnand: meson: invalidate cache on polling ECC bit mtd: rawnand: nandsim: Artificially prevent sequential page reads dt-bindings: mtd: jedec,spi-nor: Document CPOL/CPHA support mtd: nand: mxic-ecc: Fix mxic_ecc_data_xfer_wait_for_completion() when irq is used mtd: rawnand: meson: initialize struct with zeroes
This commit is contained in:
commit
fc5d1a9233
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@ -76,6 +76,13 @@ properties:
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If "broken-flash-reset" is present then having this property does not
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make any difference.
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spi-cpol: true
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spi-cpha: true
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dependencies:
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spi-cpol: [ spi-cpha ]
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spi-cpha: [ spi-cpol ]
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unevaluatedProperties: false
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examples:
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@ -429,6 +429,7 @@ static int mxic_ecc_data_xfer_wait_for_completion(struct mxic_ecc_engine *mxic)
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mxic_ecc_enable_int(mxic);
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ret = wait_for_completion_timeout(&mxic->complete,
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msecs_to_jiffies(1000));
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ret = ret ? 0 : -ETIMEDOUT;
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mxic_ecc_disable_int(mxic);
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} else {
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ret = readl_poll_timeout(mxic->regs + INTRPT_STS, val,
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@ -176,6 +176,7 @@ struct meson_nfc {
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dma_addr_t daddr;
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dma_addr_t iaddr;
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u32 info_bytes;
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unsigned long assigned_cs;
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};
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@ -503,6 +504,7 @@ static int meson_nfc_dma_buffer_setup(struct nand_chip *nand, void *databuf,
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nfc->daddr, datalen, dir);
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return ret;
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}
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nfc->info_bytes = infolen;
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cmd = GENCMDIADDRL(NFC_CMD_AIL, nfc->iaddr);
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writel(cmd, nfc->reg_base + NFC_REG_CMD);
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@ -520,8 +522,10 @@ static void meson_nfc_dma_buffer_release(struct nand_chip *nand,
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struct meson_nfc *nfc = nand_get_controller_data(nand);
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dma_unmap_single(nfc->dev, nfc->daddr, datalen, dir);
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if (infolen)
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if (infolen) {
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dma_unmap_single(nfc->dev, nfc->iaddr, infolen, dir);
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nfc->info_bytes = 0;
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}
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}
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static int meson_nfc_read_buf(struct nand_chip *nand, u8 *buf, int len)
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@ -710,6 +714,8 @@ static void meson_nfc_check_ecc_pages_valid(struct meson_nfc *nfc,
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usleep_range(10, 15);
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/* info is updated by nfc dma engine*/
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smp_rmb();
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dma_sync_single_for_cpu(nfc->dev, nfc->iaddr, nfc->info_bytes,
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DMA_FROM_DEVICE);
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ret = *info & ECC_COMPLETE;
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} while (!ret);
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}
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@ -991,7 +997,7 @@ static const struct mtd_ooblayout_ops meson_ooblayout_ops = {
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static int meson_nfc_clk_init(struct meson_nfc *nfc)
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{
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struct clk_parent_data nfc_divider_parent_data[1];
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struct clk_parent_data nfc_divider_parent_data[1] = {0};
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struct clk_init_data init = {0};
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int ret;
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@ -2160,8 +2160,23 @@ static int ns_exec_op(struct nand_chip *chip, const struct nand_operation *op,
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const struct nand_op_instr *instr = NULL;
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struct nandsim *ns = nand_get_controller_data(chip);
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if (check_only)
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if (check_only) {
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/* The current implementation of nandsim needs to know the
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* ongoing operation when performing the address cycles. This
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* means it cannot make the difference between a regular read
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* and a continuous read. Hence, this hack to manually refuse
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* supporting sequential cached operations.
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*/
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for (op_id = 0; op_id < op->ninstrs; op_id++) {
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instr = &op->instrs[op_id];
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if (instr->type == NAND_OP_CMD_INSTR &&
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(instr->ctx.cmd.opcode == NAND_CMD_READCACHEEND ||
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instr->ctx.cmd.opcode == NAND_CMD_READCACHESEQ))
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return -EOPNOTSUPP;
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}
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return 0;
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}
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ns->lines.ce = 1;
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