powerpc/64s/exception: Remove old INT_ENTRY macro
Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20200225173541.1549955-7-npiggin@gmail.com
This commit is contained in:
Nicholas Piggin
Michael Ellerman
parent
4f50541f67
commit
fc589ee416
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@ -482,13 +482,13 @@ END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948)
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* - Fall through and continue executing in real, unrelocated mode.
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* This is done if early=2.
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*/
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.macro INT_HANDLER name, vec, ool=0, early=0, virt=0, hsrr=0, area=PACA_EXGEN, ri=1, dar=0, dsisr=0, bitmask=0, kvm=0
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.macro GEN_INT_ENTRY name, virt, ool=0
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SET_SCRATCH0(r13) /* save r13 */
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GET_PACA(r13)
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std r9,\area\()+EX_R9(r13) /* save r9 */
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std r9,IAREA+EX_R9(r13) /* save r9 */
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OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR)
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HMT_MEDIUM
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std r10,\area\()+EX_R10(r13) /* save r10 - r12 */
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std r10,IAREA+EX_R10(r13) /* save r10 - r12 */
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OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR)
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.if \ool
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.if !\virt
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@ -502,47 +502,47 @@ END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948)
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.endif
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.endif
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OPT_SAVE_REG_TO_PACA(\area\()+EX_PPR, r9, CPU_FTR_HAS_PPR)
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OPT_SAVE_REG_TO_PACA(\area\()+EX_CFAR, r10, CPU_FTR_CFAR)
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OPT_SAVE_REG_TO_PACA(IAREA+EX_PPR, r9, CPU_FTR_HAS_PPR)
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OPT_SAVE_REG_TO_PACA(IAREA+EX_CFAR, r10, CPU_FTR_CFAR)
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INTERRUPT_TO_KERNEL
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SAVE_CTR(r10, \area\())
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SAVE_CTR(r10, IAREA)
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mfcr r9
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.if \kvm
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KVMTEST \name \hsrr \vec
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.if (!\virt && IKVM_REAL) || (\virt && IKVM_VIRT)
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KVMTEST \name IHSRR IVEC
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.endif
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.if \bitmask
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.if IMASK
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lbz r10,PACAIRQSOFTMASK(r13)
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andi. r10,r10,\bitmask
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andi. r10,r10,IMASK
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/* Associate vector numbers with bits in paca->irq_happened */
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.if \vec == 0x500 || \vec == 0xea0
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.if IVEC == 0x500 || IVEC == 0xea0
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li r10,PACA_IRQ_EE
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.elseif \vec == 0x900
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.elseif IVEC == 0x900
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li r10,PACA_IRQ_DEC
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.elseif \vec == 0xa00 || \vec == 0xe80
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.elseif IVEC == 0xa00 || IVEC == 0xe80
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li r10,PACA_IRQ_DBELL
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.elseif \vec == 0xe60
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.elseif IVEC == 0xe60
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li r10,PACA_IRQ_HMI
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.elseif \vec == 0xf00
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.elseif IVEC == 0xf00
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li r10,PACA_IRQ_PMI
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.else
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.abort "Bad maskable vector"
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.endif
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.if \hsrr == EXC_HV_OR_STD
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.if IHSRR == EXC_HV_OR_STD
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BEGIN_FTR_SECTION
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bne masked_Hinterrupt
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FTR_SECTION_ELSE
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bne masked_interrupt
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ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
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.elseif \hsrr
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.elseif IHSRR
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bne masked_Hinterrupt
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.else
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bne masked_interrupt
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.endif
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.endif
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std r11,\area\()+EX_R11(r13)
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std r12,\area\()+EX_R12(r13)
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std r11,IAREA+EX_R11(r13)
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std r12,IAREA+EX_R12(r13)
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/*
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* DAR/DSISR, SCRATCH0 must be read before setting MSR[RI],
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@ -550,47 +550,39 @@ END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948)
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* not recoverable if they are live.
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*/
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GET_SCRATCH0(r10)
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std r10,\area\()+EX_R13(r13)
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.if \dar == 1
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.if \hsrr
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std r10,IAREA+EX_R13(r13)
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.if IDAR == 1
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.if IHSRR
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mfspr r10,SPRN_HDAR
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.else
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mfspr r10,SPRN_DAR
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.endif
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std r10,\area\()+EX_DAR(r13)
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std r10,IAREA+EX_DAR(r13)
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.endif
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.if \dsisr == 1
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.if \hsrr
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.if IDSISR == 1
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.if IHSRR
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mfspr r10,SPRN_HDSISR
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.else
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mfspr r10,SPRN_DSISR
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.endif
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stw r10,\area\()+EX_DSISR(r13)
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stw r10,IAREA+EX_DSISR(r13)
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.endif
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.if \early == 2
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.if IEARLY == 2
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/* nothing more */
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.elseif \early
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.elseif IEARLY
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mfctr r10 /* save ctr, even for !RELOCATABLE */
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BRANCH_TO_C000(r11, \name\()_common)
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.elseif !\virt
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INT_SAVE_SRR_AND_JUMP \name\()_common, \hsrr, \ri
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INT_SAVE_SRR_AND_JUMP \name\()_common, IHSRR, ISET_RI
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.else
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INT_VIRT_SAVE_SRR_AND_JUMP \name\()_common, \hsrr
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INT_VIRT_SAVE_SRR_AND_JUMP \name\()_common, IHSRR
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.endif
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.if \ool
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.popsection
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.endif
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.endm
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.macro GEN_INT_ENTRY name, virt, ool=0
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.if ! \virt
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INT_HANDLER \name, IVEC, \ool, IEARLY, \virt, IHSRR, IAREA, ISET_RI, IDAR, IDSISR, IMASK, IKVM_REAL
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.else
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INT_HANDLER \name, IVEC, \ool, IEARLY, \virt, IHSRR, IAREA, ISET_RI, IDAR, IDSISR, IMASK, IKVM_VIRT
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.endif
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.endm
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/*
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* On entry r13 points to the paca, r9-r13 are saved in the paca,
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* r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
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