staging: vt6656: rf.c: RFbRawSetPower Remove camel case and cleanup.
White space clean up. Camel case changes; pDevice -> priv uRATE -> rate bResult -> ret byPwr -> power Functional change merged as one variable. dwMax7230Pwr -> power_setting dwVT3226Pwr -> power_setting dwVT3342Pwr -> power_setting Author changes moved to Revision history. Signed-off-by: Malcolm Priestley <tvboxspy@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -29,6 +29,8 @@
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* IFRFbWriteEmbedded - Embedded write RF register via MAC
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*
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* Revision History:
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* RF_VT3226: RobertYu:20051111, VT3226C0 and before
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* RF_VT3226D0: RobertYu:20051228
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*
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*/
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@ -783,136 +785,146 @@ int RFbSetPower(struct vnt_private *priv, u32 rate, u32 channel)
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*
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*/
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int RFbRawSetPower(struct vnt_private *pDevice, u8 byPwr, u32 uRATE)
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int RFbRawSetPower(struct vnt_private *priv, u8 power, u32 rate)
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{
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int bResult = true;
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u32 power_setting = 0;
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int ret = true;
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if (pDevice->byCurPwr == byPwr)
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return true;
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if (priv->byCurPwr == power)
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return true;
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pDevice->byCurPwr = byPwr;
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priv->byCurPwr = power;
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switch (pDevice->byRFType) {
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switch (priv->byRFType) {
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case RF_AL2230:
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if (priv->byCurPwr >= AL2230_PWR_IDX_LEN)
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return false;
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case RF_AL2230 :
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if (pDevice->byCurPwr >= AL2230_PWR_IDX_LEN)
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return false;
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bResult &= IFRFbWriteEmbedded(pDevice, dwAL2230PowerTable[pDevice->byCurPwr]);
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if (uRATE <= RATE_11M)
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bResult &= IFRFbWriteEmbedded(pDevice, 0x0001B400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
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else
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bResult &= IFRFbWriteEmbedded(pDevice, 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
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break;
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ret &= IFRFbWriteEmbedded(priv,
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dwAL2230PowerTable[priv->byCurPwr]);
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case RF_AL2230S :
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if (pDevice->byCurPwr >= AL2230_PWR_IDX_LEN)
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return false;
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bResult &= IFRFbWriteEmbedded(pDevice, dwAL2230PowerTable[pDevice->byCurPwr]);
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if (uRATE <= RATE_11M) {
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bResult &= IFRFbWriteEmbedded(pDevice, 0x040C1400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
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bResult &= IFRFbWriteEmbedded(pDevice, 0x00299B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
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}else {
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bResult &= IFRFbWriteEmbedded(pDevice, 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
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bResult &= IFRFbWriteEmbedded(pDevice, 0x00099B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
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}
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break;
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if (rate <= RATE_11M)
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ret &= IFRFbWriteEmbedded(priv, 0x0001b400 +
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(BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
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else
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ret &= IFRFbWriteEmbedded(priv, 0x0005a400 +
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(BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
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break;
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case RF_AL2230S:
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if (priv->byCurPwr >= AL2230_PWR_IDX_LEN)
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return false;
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case RF_AIROHA7230:
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{
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u32 dwMax7230Pwr;
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ret &= IFRFbWriteEmbedded(priv,
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dwAL2230PowerTable[priv->byCurPwr]);
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if (uRATE <= RATE_11M) { //RobertYu:20060426, for better 11b mask
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bResult &= IFRFbWriteEmbedded(pDevice, 0x111BB900+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW);
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}
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else {
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bResult &= IFRFbWriteEmbedded(pDevice, 0x221BB900+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW);
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}
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if (rate <= RATE_11M) {
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ret &= IFRFbWriteEmbedded(priv, 0x040c1400 +
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(BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
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ret &= IFRFbWriteEmbedded(priv, 0x00299b00 +
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(BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
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} else {
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ret &= IFRFbWriteEmbedded(priv, 0x0005a400 +
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(BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
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ret &= IFRFbWriteEmbedded(priv, 0x00099b00 +
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(BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
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}
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break;
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if (pDevice->byCurPwr > AL7230_PWR_IDX_LEN) return false;
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case RF_AIROHA7230:
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if (rate <= RATE_11M)
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ret &= IFRFbWriteEmbedded(priv, 0x111bb900 +
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(BY_AL7230_REG_LEN << 3)+IFREGCTL_REGW);
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else
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ret &= IFRFbWriteEmbedded(priv, 0x221bb900 +
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(BY_AL7230_REG_LEN << 3)+IFREGCTL_REGW);
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// 0x080F1B00 for 3 wire control TxGain(D10) and 0x31 as TX Gain value
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dwMax7230Pwr = 0x080C0B00 | ( (pDevice->byCurPwr) << 12 ) |
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(BY_AL7230_REG_LEN << 3 ) | IFREGCTL_REGW;
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if (priv->byCurPwr > AL7230_PWR_IDX_LEN)
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return false;
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bResult &= IFRFbWriteEmbedded(pDevice, dwMax7230Pwr);
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break;
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}
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break;
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/*
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* 0x080F1B00 for 3 wire control TxGain(D10)
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* and 0x31 as TX Gain value
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*/
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power_setting = 0x080c0b00 | ((priv->byCurPwr) << 12) |
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(BY_AL7230_REG_LEN << 3) | IFREGCTL_REGW;
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case RF_VT3226: //RobertYu:20051111, VT3226C0 and before
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{
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u32 dwVT3226Pwr;
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ret &= IFRFbWriteEmbedded(priv, power_setting);
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if (pDevice->byCurPwr >= VT3226_PWR_IDX_LEN)
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return false;
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dwVT3226Pwr = ((0x3F-pDevice->byCurPwr) << 20 ) | ( 0x17 << 8 ) /* Reg7 */ |
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(BY_VT3226_REG_LEN << 3 ) | IFREGCTL_REGW;
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bResult &= IFRFbWriteEmbedded(pDevice, dwVT3226Pwr);
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break;
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}
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break;
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case RF_VT3226D0: //RobertYu:20051228
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{
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u32 dwVT3226Pwr;
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case RF_VT3226:
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if (priv->byCurPwr >= VT3226_PWR_IDX_LEN)
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return false;
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power_setting = ((0x3f - priv->byCurPwr) << 20) | (0x17 << 8) |
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(BY_VT3226_REG_LEN << 3) | IFREGCTL_REGW;
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if (pDevice->byCurPwr >= VT3226_PWR_IDX_LEN)
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return false;
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ret &= IFRFbWriteEmbedded(priv, power_setting);
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if (uRATE <= RATE_11M) {
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break;
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case RF_VT3226D0:
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if (priv->byCurPwr >= VT3226_PWR_IDX_LEN)
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return false;
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dwVT3226Pwr = ((0x3F-pDevice->byCurPwr) << 20 ) | ( 0xE07 << 8 ) /* Reg7 */ | //RobertYu:20060420, TWIF 1.10
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(BY_VT3226_REG_LEN << 3 ) | IFREGCTL_REGW;
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bResult &= IFRFbWriteEmbedded(pDevice, dwVT3226Pwr);
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if (rate <= RATE_11M) {
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power_setting = ((0x3f-priv->byCurPwr) << 20) |
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(0xe07 << 8) | (BY_VT3226_REG_LEN << 3) |
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IFREGCTL_REGW;
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bResult &= IFRFbWriteEmbedded(pDevice, 0x03C6A200+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW);
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if (pDevice->vnt_mgmt.eScanState != WMAC_NO_SCANNING) {
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/* scanning, channel number is pDevice->uScanChannel */
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DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO
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ret &= IFRFbWriteEmbedded(priv, power_setting);
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ret &= IFRFbWriteEmbedded(priv, 0x03c6a200 +
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(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW);
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if (priv->vnt_mgmt.eScanState != WMAC_NO_SCANNING) {
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DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO
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"RFbRawSetPower> 11B mode uCurrChannel[%d]\n",
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pDevice->vnt_mgmt.uScanChannel);
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bResult &= IFRFbWriteEmbedded(pDevice,
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dwVT3226D0LoCurrentTable[pDevice->
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vnt_mgmt.uScanChannel - 1]);
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priv->vnt_mgmt.uScanChannel);
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ret &= IFRFbWriteEmbedded(priv,
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dwVT3226D0LoCurrentTable[priv->
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vnt_mgmt.uScanChannel - 1]);
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} else {
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DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO
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"RFbRawSetPower> 11B mode uCurrChannel[%d]\n",
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priv->vnt_mgmt.uCurrChannel);
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ret &= IFRFbWriteEmbedded(priv,
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dwVT3226D0LoCurrentTable[priv->
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vnt_mgmt.uCurrChannel - 1]);
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}
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ret &= IFRFbWriteEmbedded(priv, 0x015C0800 +
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(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW);
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} else {
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DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO
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"RFbRawSetPower> 11B mode uCurrChannel[%d]\n",
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pDevice->vnt_mgmt.uCurrChannel);
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bResult &= IFRFbWriteEmbedded(pDevice,
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dwVT3226D0LoCurrentTable[pDevice->
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vnt_mgmt.uCurrChannel - 1]);
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"@@@@ RFbRawSetPower> 11G mode\n");
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power_setting = ((0x3f-priv->byCurPwr) << 20) |
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(0x7 << 8) | (BY_VT3226_REG_LEN << 3) |
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IFREGCTL_REGW;
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ret &= IFRFbWriteEmbedded(priv, power_setting);
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ret &= IFRFbWriteEmbedded(priv, 0x00C6A200 +
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(BY_VT3226_REG_LEN << 3) + IFREGCTL_REGW);
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ret &= IFRFbWriteEmbedded(priv, 0x016BC600 +
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(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW);
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ret &= IFRFbWriteEmbedded(priv, 0x00900800 +
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(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW);
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}
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break;
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bResult &= IFRFbWriteEmbedded(pDevice, 0x015C0800+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW); //RobertYu:20060420, ok now, new switching power (mini-pci can have bigger power consumption)
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} else {
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DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO"@@@@ RFbRawSetPower> 11G mode\n");
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dwVT3226Pwr = ((0x3F-pDevice->byCurPwr) << 20 ) | ( 0x7 << 8 ) /* Reg7 */ | //RobertYu:20060420, TWIF 1.10
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(BY_VT3226_REG_LEN << 3 ) | IFREGCTL_REGW;
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bResult &= IFRFbWriteEmbedded(pDevice, dwVT3226Pwr);
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bResult &= IFRFbWriteEmbedded(pDevice, 0x00C6A200+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW); //RobertYu:20060327
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bResult &= IFRFbWriteEmbedded(pDevice, 0x016BC600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW); //RobertYu:20060111
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bResult &= IFRFbWriteEmbedded(pDevice, 0x00900800+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW); //RobertYu:20060111
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}
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break;
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}
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case RF_VT3342A0:
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if (priv->byCurPwr >= VT3342_PWR_IDX_LEN)
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return false;
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//{{RobertYu:20060609
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case RF_VT3342A0:
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{
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u32 dwVT3342Pwr;
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power_setting = ((0x3F-priv->byCurPwr) << 20) |
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(0x27 << 8) | (BY_VT3342_REG_LEN << 3) |
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IFREGCTL_REGW;
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if (pDevice->byCurPwr >= VT3342_PWR_IDX_LEN)
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return false;
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ret &= IFRFbWriteEmbedded(priv, power_setting);
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dwVT3342Pwr = ((0x3F-pDevice->byCurPwr) << 20 ) | ( 0x27 << 8 ) /* Reg7 */ |
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(BY_VT3342_REG_LEN << 3 ) | IFREGCTL_REGW;
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bResult &= IFRFbWriteEmbedded(pDevice, dwVT3342Pwr);
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break;
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}
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default :
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break;
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}
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return bResult;
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break;
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default:
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break;
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}
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return ret;
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}
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/*+
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