drm/i915/guc: Propagate the fw xfer timeout
Propagate the timeout on transferring the fw back to the caller where it may act upon it, usually by restarting the xfer before failing. v2: Simplify the wait to only wait upon the guc signaling completion, with an assertion that the fw xfer must have completed for it to be ready! Testcase: igt/drv_selftest/live_hangcheck Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181018195536.11522-1-chris@chris-wilson.co.uk
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drivers/gpu/drm/i915
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@ -125,66 +125,26 @@ static void guc_prepare_xfer(struct intel_guc *guc)
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}
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/* Copy RSA signature from the fw image to HW for verification */
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static int guc_xfer_rsa(struct intel_guc *guc, struct i915_vma *vma)
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static void guc_xfer_rsa(struct intel_guc *guc, struct i915_vma *vma)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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struct intel_uc_fw *guc_fw = &guc->fw;
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struct sg_table *sg = vma->pages;
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u32 rsa[UOS_RSA_SCRATCH_COUNT];
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int i;
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if (sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, sizeof(rsa),
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guc_fw->rsa_offset) != sizeof(rsa))
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return -EINVAL;
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sg_pcopy_to_buffer(vma->pages->sgl, vma->pages->nents,
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rsa, sizeof(rsa), guc->fw.rsa_offset);
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for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++)
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I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
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return 0;
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}
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/*
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* Transfer the firmware image to RAM for execution by the microcontroller.
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*
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* Architecturally, the DMA engine is bidirectional, and can potentially even
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* transfer between GTT locations. This functionality is left out of the API
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* for now as there is no need for it.
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*/
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static int guc_xfer_ucode(struct intel_guc *guc, struct i915_vma *vma)
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static bool guc_xfer_completed(struct intel_guc *guc, u32 *status)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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struct intel_uc_fw *guc_fw = &guc->fw;
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unsigned long offset;
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u32 status;
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int ret;
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/*
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* The header plus uCode will be copied to WOPCM via DMA, excluding any
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* other components
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*/
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I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
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/* Set the source address for the new blob */
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offset = intel_guc_ggtt_offset(guc, vma) + guc_fw->header_offset;
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I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
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I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
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/*
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* Set the DMA destination. Current uCode expects the code to be
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* loaded at 8k; locations below this are used for the stack.
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*/
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I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
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I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
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/* Finally start the DMA */
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I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
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/* Wait for DMA to finish */
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ret = __intel_wait_for_register_fw(dev_priv, DMA_CTRL, START_DMA, 0,
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2, 100, &status);
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DRM_DEBUG_DRIVER("GuC DMA status %#x\n", status);
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return ret;
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/* Did we complete the xfer? */
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*status = I915_READ(DMA_CTRL);
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return !(*status & START_DMA);
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}
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/*
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@ -228,9 +188,51 @@ static int guc_wait_ucode(struct intel_guc *guc)
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ret = -ENOEXEC;
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}
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if (ret == 0 && !guc_xfer_completed(guc, &status)) {
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DRM_ERROR("GuC is ready, but the xfer %08x is incomplete\n",
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status);
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ret = -ENXIO;
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}
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return ret;
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}
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/*
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* Transfer the firmware image to RAM for execution by the microcontroller.
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*
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* Architecturally, the DMA engine is bidirectional, and can potentially even
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* transfer between GTT locations. This functionality is left out of the API
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* for now as there is no need for it.
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*/
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static int guc_xfer_ucode(struct intel_guc *guc, struct i915_vma *vma)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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struct intel_uc_fw *guc_fw = &guc->fw;
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unsigned long offset;
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/*
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* The header plus uCode will be copied to WOPCM via DMA, excluding any
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* other components
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*/
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I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
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/* Set the source address for the new blob */
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offset = intel_guc_ggtt_offset(guc, vma) + guc_fw->header_offset;
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I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
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I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
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/*
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* Set the DMA destination. Current uCode expects the code to be
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* loaded at 8k; locations below this are used for the stack.
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*/
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I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
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I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
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/* Finally start the DMA */
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I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
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return guc_wait_ucode(guc);
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}
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/*
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* Load the GuC firmware blob into the MinuteIA.
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*/
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@ -251,17 +253,9 @@ static int guc_fw_xfer(struct intel_uc_fw *guc_fw, struct i915_vma *vma)
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* by the DMA engine in one operation, whereas the RSA signature is
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* loaded via MMIO.
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*/
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ret = guc_xfer_rsa(guc, vma);
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if (ret)
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DRM_WARN("GuC firmware signature xfer error %d\n", ret);
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guc_xfer_rsa(guc, vma);
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ret = guc_xfer_ucode(guc, vma);
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if (ret)
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DRM_WARN("GuC firmware code xfer error %d\n", ret);
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ret = guc_wait_ucode(guc);
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if (ret)
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DRM_ERROR("GuC firmware xfer error %d\n", ret);
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
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