[IA64] Annotate fsys_bubble_down() with McKinley dispatch info.
This patch changes comments & formatting only. There is no code change. Signed-off-by: David Mosberger-Tang <davidm@hpl.hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
This commit is contained in:
David Mosberger-Tang
Tony Luck
parent
1ba7be7d69
commit
fbf7192ba0
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@ -531,84 +531,114 @@ GLOBAL_ENTRY(fsys_bubble_down)
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.altrp b6
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.altrp b6
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.body
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.body
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/*
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/*
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* We get here for syscalls that don't have a lightweight handler. For those, we
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* We get here for syscalls that don't have a lightweight
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* need to bubble down into the kernel and that requires setting up a minimal
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* handler. For those, we need to bubble down into the kernel
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* pt_regs structure, and initializing the CPU state more or less as if an
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* and that requires setting up a minimal pt_regs structure,
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* interruption had occurred. To make syscall-restarts work, we setup pt_regs
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* and initializing the CPU state more or less as if an
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* such that cr_iip points to the second instruction in syscall_via_break.
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* interruption had occurred. To make syscall-restarts work,
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* Decrementing the IP hence will restart the syscall via break and not
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* we setup pt_regs such that cr_iip points to the second
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* decrementing IP will return us to the caller, as usual. Note that we preserve
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* instruction in syscall_via_break. Decrementing the IP
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* the value of psr.pp rather than initializing it from dcr.pp. This makes it
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* hence will restart the syscall via break and not
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* possible to distinguish fsyscall execution from other privileged execution.
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* decrementing IP will return us to the caller, as usual.
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* Note that we preserve the value of psr.pp rather than
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* initializing it from dcr.pp. This makes it possible to
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* distinguish fsyscall execution from other privileged
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* execution.
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*
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*
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* On entry:
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* On entry:
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* - normal fsyscall handler register usage, except that we also have:
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* - normal fsyscall handler register usage, except
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* that we also have:
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* - r18: address of syscall entry point
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* - r18: address of syscall entry point
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* - r21: ar.fpsr
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* - r21: ar.fpsr
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* - r26: ar.pfs
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* - r26: ar.pfs
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* - r27: ar.rsc
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* - r27: ar.rsc
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* - r29: psr
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* - r29: psr
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*
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* We used to clear some PSR bits here but that requires slow
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* serialization. Fortuntely, that isn't really necessary.
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* The rationale is as follows: we used to clear bits
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* ~PSR_PRESERVED_BITS in PSR.L. Since
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* PSR_PRESERVED_BITS==PSR.{UP,MFL,MFH,PK,DT,PP,SP,RT,IC}, we
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* ended up clearing PSR.{BE,AC,I,DFL,DFH,DI,DB,SI,TB}.
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* However,
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*
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* PSR.BE : already is turned off in __kernel_syscall_via_epc()
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* PSR.AC : don't care (kernel normally turns PSR.AC on)
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* PSR.I : already turned off by the time fsys_bubble_down gets
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* invoked
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* PSR.DFL: always 0 (kernel never turns it on)
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* PSR.DFH: don't care --- kernel never touches f32-f127 on its own
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* initiative
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* PSR.DI : always 0 (kernel never turns it on)
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* PSR.SI : always 0 (kernel never turns it on)
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* PSR.DB : don't care --- kernel never enables kernel-level
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* breakpoints
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* PSR.TB : must be 0 already; if it wasn't zero on entry to
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* __kernel_syscall_via_epc, the branch to fsys_bubble_down
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* will trigger a taken branch; the taken-trap-handler then
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* converts the syscall into a break-based system-call.
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*/
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*/
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/*
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/*
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* Reading psr.l gives us only bits 0-31, psr.it, and psr.mc. The rest we have
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* Reading psr.l gives us only bits 0-31, psr.it, and psr.mc.
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* to synthesize.
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* The rest we have to synthesize.
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*/
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*/
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# define PSR_ONE_BITS ((3 << IA64_PSR_CPL0_BIT) | (0x1 << IA64_PSR_RI_BIT) \
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# define PSR_ONE_BITS ((3 << IA64_PSR_CPL0_BIT) \
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| (0x1 << IA64_PSR_RI_BIT) \
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| IA64_PSR_BN | IA64_PSR_I)
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| IA64_PSR_BN | IA64_PSR_I)
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invala
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invala // M0|1
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movl r14=ia64_ret_from_syscall
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movl r14=ia64_ret_from_syscall // X
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nop.m 0
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nop.m 0
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movl r28=__kernel_syscall_via_break
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movl r28=__kernel_syscall_via_break // X create cr.iip
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;;
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;;
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mov r2=r16 // copy current task addr to addl-addressable register
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mov r2=r16 // A get task addr to addl-addressable register
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adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16
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adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16 // A
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mov r31=pr // save pr (2 cyc)
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mov r31=pr // I0 save pr (2 cyc)
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;;
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;;
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st1 [r16]=r0 // clear current->thread.on_ustack flag
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st1 [r16]=r0 // M2|3 clear current->thread.on_ustack flag
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addl r22=IA64_RBS_OFFSET,r2 // compute base of RBS
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addl r22=IA64_RBS_OFFSET,r2 // A compute base of RBS
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add r3=TI_FLAGS+IA64_TASK_SIZE,r2
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add r3=TI_FLAGS+IA64_TASK_SIZE,r2 // A
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;;
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;;
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ld4 r3=[r3] // r2 = current_thread_info()->flags
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ld4 r3=[r3] // M0|1 r3 = current_thread_info()->flags
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lfetch.fault.excl.nt1 [r22]
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lfetch.fault.excl.nt1 [r22] // M0|1 prefetch register backing-store
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nop.i 0
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nop.i 0
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;;
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;;
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mov ar.rsc=0 // set enforced lazy mode, pl 0, little-endian, loadrs=0
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mov ar.rsc=0 // M2 set enforced lazy mode, pl 0, LE, loadrs=0
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nop.m 0
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nop.m 0
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nop.i 0
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nop.i 0
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;;
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;;
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mov r23=ar.bspstore // save ar.bspstore (12 cyc)
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mov r23=ar.bspstore // M2 (12 cyc) save ar.bspstore
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mov.m r24=ar.rnat // read ar.rnat (5 cyc lat)
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mov.m r24=ar.rnat // M2 (5 cyc) read ar.rnat (dual-issues!)
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nop.i 0
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nop.i 0
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;;
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;;
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mov ar.bspstore=r22 // switch to kernel RBS
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mov ar.bspstore=r22 // M2 (6 cyc) switch to kernel RBS
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movl r8=PSR_ONE_BITS // X
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movl r8=PSR_ONE_BITS // X
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;;
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;;
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mov r25=ar.unat // save ar.unat (5 cyc)
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mov r25=ar.unat // M2 (5 cyc) save ar.unat
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mov r19=b6 // save b6 (2 cyc)
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mov r19=b6 // I0 save b6 (2 cyc)
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mov r20=r1 // save caller's gp in r20
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mov r20=r1 // A save caller's gp in r20
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;;
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;;
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or r29=r8,r29 // construct cr.ipsr value to save
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or r29=r8,r29 // A construct cr.ipsr value to save
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mov b6=r18 // copy syscall entry-point to b6 (7 cyc)
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mov b6=r18 // I0 copy syscall entry-point to b6 (7 cyc)
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addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r2 // compute base of memory stack
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addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r2 // A compute base of memory stack
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mov r18=ar.bsp // save (kernel) ar.bsp (12 cyc)
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mov r18=ar.bsp // M2 save (kernel) ar.bsp (12 cyc)
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cmp.ne pKStk,pUStk=r0,r0 // set pKStk <- 0, pUStk <- 1
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cmp.ne pKStk,pUStk=r0,r0 // A set pKStk <- 0, pUStk <- 1
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br.call.sptk.many b7=ia64_syscall_setup
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br.call.sptk.many b7=ia64_syscall_setup // B
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;;
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;;
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mov ar.rsc=0x3 // set eager mode, pl 0, little-endian, loadrs=0
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mov ar.rsc=0x3 // M2 set eager mode, pl 0, LE, loadrs=0
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mov rp=r14 // set the real return addr
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mov rp=r14 // I0 set the real return addr
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nop.i 0
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nop.i 0
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;;
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;;
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ssm psr.i
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ssm psr.i // M2 we're on kernel stacks now, reenable irqs
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tbit.z p8,p0=r3,TIF_SYSCALL_TRACE
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tbit.z p8,p0=r3,TIF_SYSCALL_TRACE // I0
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(p10) br.cond.spnt.many ia64_ret_from_syscall // p10==true means out registers are more than 8
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(p10) br.cond.spnt.many ia64_ret_from_syscall // B return if bad call-frame or r15 is a NaT
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nop.m 0
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nop.m 0
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(p8) br.call.sptk.many b6=b6 // ignore this return addr
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(p8) br.call.sptk.many b6=b6 // B (ignore return address)
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br.cond.spnt ia64_trace_syscall
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br.cond.spnt ia64_trace_syscall // B
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END(fsys_bubble_down)
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END(fsys_bubble_down)
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.rodata
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.rodata
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