media: tegra-video: Add support for V4L2_PIX_FMT_NV16
NV16 are two-plane versions of YUV422 format. VI/CSI surface0 registers corresponds to first Y plane and surface1 registers corresponds to seconds UV plane. This patch updates image size for NV16 format to include both planes and programs VI/CSI surface1 registers for UV plane capture. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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@ -287,6 +287,7 @@ static int tegra_channel_capture_frame(struct tegra_vi_channel *chan,
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{
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u32 thresh, value, frame_start, mw_ack_done;
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int bytes_per_line = chan->format.bytesperline;
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u32 sizeimage = chan->format.sizeimage;
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int err;
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/* program buffer address by using surface 0 */
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@ -295,6 +296,18 @@ static int tegra_channel_capture_frame(struct tegra_vi_channel *chan,
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vi_csi_write(chan, TEGRA_VI_CSI_SURFACE0_OFFSET_LSB, buf->addr);
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vi_csi_write(chan, TEGRA_VI_CSI_SURFACE0_STRIDE, bytes_per_line);
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/*
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* Program surface 1 for UV plane with offset sizeimage from Y plane.
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*/
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if (chan->fmtinfo->fourcc == V4L2_PIX_FMT_NV16) {
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vi_csi_write(chan, TEGRA_VI_CSI_SURFACE1_OFFSET_MSB,
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((u64)buf->addr + sizeimage / 2) >> 32);
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vi_csi_write(chan, TEGRA_VI_CSI_SURFACE1_OFFSET_LSB,
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buf->addr + sizeimage / 2);
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vi_csi_write(chan, TEGRA_VI_CSI_SURFACE1_STRIDE,
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bytes_per_line);
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}
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/*
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* Tegra VI block interacts with host1x syncpt for synchronizing
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* programmed condition of capture state and hardware operation.
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@ -484,6 +484,8 @@ static void tegra_channel_fmt_align(struct tegra_vi_channel *chan,
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pix->bytesperline = clamp(bpl, min_bpl, max_bpl);
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pix->sizeimage = pix->bytesperline * pix->height;
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if (pix->pixelformat == V4L2_PIX_FMT_NV16)
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pix->sizeimage *= 2;
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}
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static int __tegra_channel_try_format(struct tegra_vi_channel *chan,
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