usb: dwc3: dwc3-octeon: Verify clock divider
Although valid USB clock divider will be calculated for all valid Octeon core frequencies, make code formally correct limiting divider not to be greater that 7 so it fits into H_CLKDIV_SEL field. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Reported-by: Linux Kernel Functional Testing <lkft@linaro.org> Closes: https://qa-reports.linaro.org/lkft/linux-next-master/build/next-20230808/testrun/18882876/suite/build/test/gcc-8-cavium_octeon_defconfig/log Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com> Link: https://lore.kernel.org/r/ZNIM7tlBNdHFzXZG@lenoch Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -251,11 +251,11 @@ static int dwc3_octeon_get_divider(void)
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while (div < ARRAY_SIZE(clk_div)) {
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uint64_t rate = octeon_get_io_clock_rate() / clk_div[div];
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if (rate <= 300000000 && rate >= 150000000)
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break;
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return div;
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div++;
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}
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return div;
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return -EINVAL;
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}
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static int dwc3_octeon_setup(struct dwc3_octeon *octeon,
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@ -289,6 +289,10 @@ static int dwc3_octeon_setup(struct dwc3_octeon *octeon,
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/* Step 4b: Select controller clock frequency. */
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div = dwc3_octeon_get_divider();
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if (div < 0) {
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dev_err(dev, "clock divider invalid\n");
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return div;
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}
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val = dwc3_octeon_readq(uctl_ctl_reg);
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val &= ~USBDRD_UCTL_CTL_H_CLKDIV_SEL;
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val |= FIELD_PREP(USBDRD_UCTL_CTL_H_CLKDIV_SEL, div);
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