drm/amd/display: refactor init_hw to isolate pipe related init
[Why] Pipe related init is possible to optimized if we know what we intend to program, and if we can determine it matches what is already programmed for the pipe. [How] First step is to isolate the pipe related init code Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Anthony Koo
Alex Deucher
parent
9c0fb8d45b
commit
fb55546ea4
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@ -2275,6 +2275,11 @@ static void dce110_enable_per_frame_crtc_position_reset(
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}
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static void init_pipes(struct dc *dc, struct dc_state *context)
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{
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// Do nothing
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}
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static void init_hw(struct dc *dc)
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{
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int i;
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@ -2642,6 +2647,7 @@ static const struct hw_sequencer_funcs dce110_funcs = {
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.program_gamut_remap = program_gamut_remap,
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.program_output_csc = program_output_csc,
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.init_hw = init_hw,
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.init_pipes = init_pipes,
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.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
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.apply_ctx_for_surface = dce110_apply_ctx_for_surface,
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.update_plane_addr = update_plane_addr,
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@ -956,6 +956,64 @@ static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
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pipe_ctx->pipe_idx);
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}
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static void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
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{
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int i;
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for (i = 0; i < dc->res_pool->pipe_count; i++) {
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struct timing_generator *tg = dc->res_pool->timing_generators[i];
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if (tg->funcs->is_tg_enabled(tg))
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tg->funcs->lock(tg);
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/* Blank controller using driver code instead of
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* command table.
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*/
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if (tg->funcs->is_tg_enabled(tg)) {
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tg->funcs->set_blank(tg, true);
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hwss_wait_for_blank_complete(tg);
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}
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}
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dc->res_pool->mpc->funcs->mpc_init(dc->res_pool->mpc);
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for (i = 0; i < dc->res_pool->pipe_count; i++) {
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struct timing_generator *tg = dc->res_pool->timing_generators[i];
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struct hubp *hubp = dc->res_pool->hubps[i];
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struct dpp *dpp = dc->res_pool->dpps[i];
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struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
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dpp->funcs->dpp_reset(dpp);
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pipe_ctx->stream_res.tg = tg;
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pipe_ctx->pipe_idx = i;
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pipe_ctx->plane_res.hubp = hubp;
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pipe_ctx->plane_res.dpp = dpp;
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pipe_ctx->plane_res.mpcc_inst = dpp->inst;
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hubp->mpcc_id = dpp->inst;
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hubp->opp_id = 0xf;
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hubp->power_gated = false;
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dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
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dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
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dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
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pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
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hwss1_plane_atomic_disconnect(dc, pipe_ctx);
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if (tg->funcs->is_tg_enabled(tg))
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tg->funcs->unlock(tg);
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dcn10_disable_plane(dc, pipe_ctx);
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pipe_ctx->stream_res.tg = NULL;
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pipe_ctx->plane_res.hubp = NULL;
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tg->funcs->tg_init(tg);
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}
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}
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static void dcn10_init_hw(struct dc *dc)
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{
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int i;
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@ -963,7 +1021,6 @@ static void dcn10_init_hw(struct dc *dc)
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struct dmcu *dmcu = dc->res_pool->dmcu;
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struct dce_hwseq *hws = dc->hwseq;
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struct dc_bios *dcb = dc->ctx->dc_bios;
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struct dc_state *context = dc->current_state;
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if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
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REG_WRITE(REFCLK_CNTL, 0);
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@ -980,11 +1037,15 @@ static void dcn10_init_hw(struct dc *dc)
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}
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enable_power_gating_plane(dc->hwseq, true);
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} else {
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/* end of FPGA. Below if real ASIC */
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return;
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}
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if (!dcb->funcs->is_accelerated_mode(dcb)) {
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bool allow_self_fresh_force_enable =
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hububu1_is_allow_self_refresh_enabled(dc->res_pool->hubbub);
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hububu1_is_allow_self_refresh_enabled(
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dc->res_pool->hubbub);
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bios_golden_init(dc);
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@ -1018,76 +1079,6 @@ static void dcn10_init_hw(struct dc *dc)
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link->link_enc->funcs->is_dig_enabled(link->link_enc))
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link->link_status.link_active = true;
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}
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}
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for (i = 0; i < dc->res_pool->pipe_count; i++) {
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struct timing_generator *tg = dc->res_pool->timing_generators[i];
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if (tg->funcs->is_tg_enabled(tg))
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tg->funcs->lock(tg);
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}
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/* Blank controller using driver code instead of
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* command table.
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*/
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for (i = 0; i < dc->res_pool->pipe_count; i++) {
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struct timing_generator *tg = dc->res_pool->timing_generators[i];
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if (tg->funcs->is_tg_enabled(tg)) {
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tg->funcs->set_blank(tg, true);
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hwss_wait_for_blank_complete(tg);
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}
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}
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/* Reset all MPCC muxes */
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dc->res_pool->mpc->funcs->mpc_init(dc->res_pool->mpc);
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for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
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struct timing_generator *tg = dc->res_pool->timing_generators[i];
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struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
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struct hubp *hubp = dc->res_pool->hubps[i];
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struct dpp *dpp = dc->res_pool->dpps[i];
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pipe_ctx->stream_res.tg = tg;
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pipe_ctx->pipe_idx = i;
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pipe_ctx->plane_res.hubp = hubp;
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pipe_ctx->plane_res.dpp = dpp;
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pipe_ctx->plane_res.mpcc_inst = dpp->inst;
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hubp->mpcc_id = dpp->inst;
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hubp->opp_id = 0xf;
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hubp->power_gated = false;
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dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
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dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
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dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
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pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
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hwss1_plane_atomic_disconnect(dc, pipe_ctx);
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}
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for (i = 0; i < dc->res_pool->pipe_count; i++) {
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struct timing_generator *tg = dc->res_pool->timing_generators[i];
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if (tg->funcs->is_tg_enabled(tg))
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tg->funcs->unlock(tg);
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}
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for (i = 0; i < dc->res_pool->pipe_count; i++) {
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struct timing_generator *tg = dc->res_pool->timing_generators[i];
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struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
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dcn10_disable_plane(dc, pipe_ctx);
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pipe_ctx->stream_res.tg = NULL;
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pipe_ctx->plane_res.hubp = NULL;
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tg->funcs->tg_init(tg);
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}
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/* end of FPGA. Below if real ASIC */
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if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
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return;
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for (i = 0; i < dc->res_pool->audio_count; i++) {
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struct audio *audio = dc->res_pool->audios[i];
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@ -1118,6 +1109,9 @@ static void dcn10_init_hw(struct dc *dc)
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enable_power_gating_plane(dc->hwseq, true);
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memset(&dc->res_pool->clk_mgr->clks, 0, sizeof(dc->res_pool->clk_mgr->clks));
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if (dc->hwss.init_pipes)
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dc->hwss.init_pipes(dc, dc->current_state);
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}
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static void reset_hw_ctx_wrap(
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@ -2718,6 +2712,7 @@ static void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx)
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static const struct hw_sequencer_funcs dcn10_funcs = {
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.program_gamut_remap = program_gamut_remap,
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.init_hw = dcn10_init_hw,
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.init_pipes = dcn10_init_pipes,
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.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
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.apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
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.update_plane_addr = dcn10_update_plane_addr,
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@ -70,6 +70,8 @@ struct hw_sequencer_funcs {
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void (*init_hw)(struct dc *dc);
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void (*init_pipes)(struct dc *dc, struct dc_state *context);
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enum dc_status (*apply_ctx_to_hw)(
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struct dc *dc, struct dc_state *context);
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