x86/hyperv: Add Write/Read MSR registers via ghcb page
Hyperv provides GHCB protocol to write Synthetic Interrupt Controller MSR registers in Isolation VM with AMD SEV SNP and these registers are emulated by hypervisor directly. Hyperv requires to write SINTx MSR registers twice. First writes MSR via GHCB page to communicate with hypervisor and then writes wrmsr instruction to talk with paravisor which runs in VMPL0. Guest OS ID MSR also needs to be set via GHCB page. Reviewed-by: Michael Kelley <mikelley@microsoft.com> Signed-off-by: Tianyu Lan <Tianyu.Lan@microsoft.com> Link: https://lore.kernel.org/r/20211025122116.264793-7-ltykernel@gmail.com Signed-off-by: Wei Liu <wei.liu@kernel.org>
This commit is contained in:
Tianyu Lan
Wei Liu
parent
d4dccf353d
commit
faff44069f
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@ -37,7 +37,7 @@ EXPORT_SYMBOL_GPL(hv_current_partition_id);
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void *hv_hypercall_pg;
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EXPORT_SYMBOL_GPL(hv_hypercall_pg);
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void __percpu **hv_ghcb_pg;
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union hv_ghcb __percpu **hv_ghcb_pg;
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/* Storage to save the hypercall page temporarily for hibernation */
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static void *hv_hypercall_pg_saved;
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@ -406,7 +406,7 @@ void __init hyperv_init(void)
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}
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if (hv_isolation_type_snp()) {
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hv_ghcb_pg = alloc_percpu(void *);
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hv_ghcb_pg = alloc_percpu(union hv_ghcb *);
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if (!hv_ghcb_pg)
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goto free_vp_assist_page;
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}
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@ -424,6 +424,9 @@ void __init hyperv_init(void)
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guest_id = generate_guest_id(0, LINUX_VERSION_CODE, 0);
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wrmsrl(HV_X64_MSR_GUEST_OS_ID, guest_id);
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/* Hyper-V requires to write guest os id via ghcb in SNP IVM. */
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hv_ghcb_msr_write(HV_X64_MSR_GUEST_OS_ID, guest_id);
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hv_hypercall_pg = __vmalloc_node_range(PAGE_SIZE, 1, VMALLOC_START,
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VMALLOC_END, GFP_KERNEL, PAGE_KERNEL_ROX,
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VM_FLUSH_RESET_PERMS, NUMA_NO_NODE,
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@ -501,6 +504,7 @@ void __init hyperv_init(void)
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clean_guest_os_id:
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wrmsrl(HV_X64_MSR_GUEST_OS_ID, 0);
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hv_ghcb_msr_write(HV_X64_MSR_GUEST_OS_ID, 0);
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cpuhp_remove_state(cpuhp);
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free_ghcb_page:
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free_percpu(hv_ghcb_pg);
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@ -522,6 +526,7 @@ void hyperv_cleanup(void)
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/* Reset our OS id */
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wrmsrl(HV_X64_MSR_GUEST_OS_ID, 0);
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hv_ghcb_msr_write(HV_X64_MSR_GUEST_OS_ID, 0);
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/*
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* Reset hypercall page reference before reset the page,
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@ -592,30 +597,3 @@ bool hv_is_hyperv_initialized(void)
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return hypercall_msr.enable;
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}
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EXPORT_SYMBOL_GPL(hv_is_hyperv_initialized);
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enum hv_isolation_type hv_get_isolation_type(void)
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{
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if (!(ms_hyperv.priv_high & HV_ISOLATION))
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return HV_ISOLATION_TYPE_NONE;
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return FIELD_GET(HV_ISOLATION_TYPE, ms_hyperv.isolation_config_b);
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}
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EXPORT_SYMBOL_GPL(hv_get_isolation_type);
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bool hv_is_isolation_supported(void)
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{
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if (!cpu_feature_enabled(X86_FEATURE_HYPERVISOR))
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return false;
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if (!hypervisor_is_type(X86_HYPER_MS_HYPERV))
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return false;
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return hv_get_isolation_type() != HV_ISOLATION_TYPE_NONE;
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}
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DEFINE_STATIC_KEY_FALSE(isolation_type_snp);
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bool hv_isolation_type_snp(void)
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{
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return static_branch_unlikely(&isolation_type_snp);
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}
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EXPORT_SYMBOL_GPL(hv_isolation_type_snp);
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@ -6,12 +6,123 @@
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* Tianyu Lan <Tianyu.Lan@microsoft.com>
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*/
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#include <linux/types.h>
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#include <linux/bitfield.h>
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#include <linux/hyperv.h>
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#include <linux/types.h>
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#include <linux/bitfield.h>
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#include <linux/slab.h>
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#include <asm/svm.h>
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#include <asm/sev.h>
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#include <asm/io.h>
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#include <asm/mshyperv.h>
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#include <asm/hypervisor.h>
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#ifdef CONFIG_AMD_MEM_ENCRYPT
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union hv_ghcb {
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struct ghcb ghcb;
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} __packed __aligned(HV_HYP_PAGE_SIZE);
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void hv_ghcb_msr_write(u64 msr, u64 value)
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{
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union hv_ghcb *hv_ghcb;
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void **ghcb_base;
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unsigned long flags;
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struct es_em_ctxt ctxt;
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if (!hv_ghcb_pg)
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return;
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WARN_ON(in_nmi());
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local_irq_save(flags);
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ghcb_base = (void **)this_cpu_ptr(hv_ghcb_pg);
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hv_ghcb = (union hv_ghcb *)*ghcb_base;
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if (!hv_ghcb) {
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local_irq_restore(flags);
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return;
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}
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ghcb_set_rcx(&hv_ghcb->ghcb, msr);
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ghcb_set_rax(&hv_ghcb->ghcb, lower_32_bits(value));
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ghcb_set_rdx(&hv_ghcb->ghcb, upper_32_bits(value));
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if (sev_es_ghcb_hv_call(&hv_ghcb->ghcb, false, &ctxt,
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SVM_EXIT_MSR, 1, 0))
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pr_warn("Fail to write msr via ghcb %llx.\n", msr);
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local_irq_restore(flags);
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}
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EXPORT_SYMBOL_GPL(hv_ghcb_msr_write);
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void hv_ghcb_msr_read(u64 msr, u64 *value)
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{
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union hv_ghcb *hv_ghcb;
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void **ghcb_base;
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unsigned long flags;
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struct es_em_ctxt ctxt;
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/* Check size of union hv_ghcb here. */
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BUILD_BUG_ON(sizeof(union hv_ghcb) != HV_HYP_PAGE_SIZE);
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if (!hv_ghcb_pg)
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return;
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WARN_ON(in_nmi());
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local_irq_save(flags);
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ghcb_base = (void **)this_cpu_ptr(hv_ghcb_pg);
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hv_ghcb = (union hv_ghcb *)*ghcb_base;
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if (!hv_ghcb) {
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local_irq_restore(flags);
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return;
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}
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ghcb_set_rcx(&hv_ghcb->ghcb, msr);
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if (sev_es_ghcb_hv_call(&hv_ghcb->ghcb, false, &ctxt,
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SVM_EXIT_MSR, 0, 0))
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pr_warn("Fail to read msr via ghcb %llx.\n", msr);
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else
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*value = (u64)lower_32_bits(hv_ghcb->ghcb.save.rax)
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| ((u64)lower_32_bits(hv_ghcb->ghcb.save.rdx) << 32);
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local_irq_restore(flags);
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}
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EXPORT_SYMBOL_GPL(hv_ghcb_msr_read);
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#endif
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enum hv_isolation_type hv_get_isolation_type(void)
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{
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if (!(ms_hyperv.priv_high & HV_ISOLATION))
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return HV_ISOLATION_TYPE_NONE;
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return FIELD_GET(HV_ISOLATION_TYPE, ms_hyperv.isolation_config_b);
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}
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EXPORT_SYMBOL_GPL(hv_get_isolation_type);
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/*
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* hv_is_isolation_supported - Check system runs in the Hyper-V
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* isolation VM.
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*/
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bool hv_is_isolation_supported(void)
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{
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if (!cpu_feature_enabled(X86_FEATURE_HYPERVISOR))
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return false;
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if (!hypervisor_is_type(X86_HYPER_MS_HYPERV))
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return false;
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return hv_get_isolation_type() != HV_ISOLATION_TYPE_NONE;
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}
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DEFINE_STATIC_KEY_FALSE(isolation_type_snp);
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/*
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* hv_isolation_type_snp - Check system runs in the AMD SEV-SNP based
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* isolation VM.
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*/
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bool hv_isolation_type_snp(void)
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{
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return static_branch_unlikely(&isolation_type_snp);
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}
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/*
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* hv_mark_gpa_visibility - Set pages visible to host via hvcall.
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@ -11,25 +11,14 @@
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#include <asm/paravirt.h>
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#include <asm/mshyperv.h>
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union hv_ghcb;
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DECLARE_STATIC_KEY_FALSE(isolation_type_snp);
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typedef int (*hyperv_fill_flush_list_func)(
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struct hv_guest_mapping_flush_list *flush,
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void *data);
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static inline void hv_set_register(unsigned int reg, u64 value)
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{
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wrmsrl(reg, value);
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}
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static inline u64 hv_get_register(unsigned int reg)
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{
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u64 value;
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rdmsrl(reg, value);
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return value;
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}
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#define hv_get_raw_timer() rdtsc_ordered()
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void hyperv_vector_handler(struct pt_regs *regs);
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@ -41,7 +30,7 @@ extern void *hv_hypercall_pg;
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extern u64 hv_current_partition_id;
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extern void __percpu **hv_ghcb_pg;
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extern union hv_ghcb __percpu **hv_ghcb_pg;
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int hv_call_deposit_pages(int node, u64 partition_id, u32 num_pages);
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int hv_call_add_logical_proc(int node, u32 lp_index, u32 acpi_id);
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@ -193,6 +182,50 @@ int hv_map_ioapic_interrupt(int ioapic_id, bool level, int vcpu, int vector,
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struct hv_interrupt_entry *entry);
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int hv_unmap_ioapic_interrupt(int ioapic_id, struct hv_interrupt_entry *entry);
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int hv_set_mem_host_visibility(unsigned long addr, int numpages, bool visible);
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#ifdef CONFIG_AMD_MEM_ENCRYPT
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void hv_ghcb_msr_write(u64 msr, u64 value);
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void hv_ghcb_msr_read(u64 msr, u64 *value);
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#else
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static inline void hv_ghcb_msr_write(u64 msr, u64 value) {}
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static inline void hv_ghcb_msr_read(u64 msr, u64 *value) {}
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#endif
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extern bool hv_isolation_type_snp(void);
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static inline bool hv_is_synic_reg(unsigned int reg)
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{
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if ((reg >= HV_REGISTER_SCONTROL) &&
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(reg <= HV_REGISTER_SINT15))
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return true;
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return false;
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}
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static inline u64 hv_get_register(unsigned int reg)
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{
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u64 value;
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if (hv_is_synic_reg(reg) && hv_isolation_type_snp())
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hv_ghcb_msr_read(reg, &value);
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else
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rdmsrl(reg, value);
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return value;
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}
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static inline void hv_set_register(unsigned int reg, u64 value)
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{
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if (hv_is_synic_reg(reg) && hv_isolation_type_snp()) {
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hv_ghcb_msr_write(reg, value);
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/* Write proxy bit via wrmsl instruction */
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if (reg >= HV_REGISTER_SINT0 &&
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reg <= HV_REGISTER_SINT15)
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wrmsrl(reg, value | 1 << 20);
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} else {
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wrmsrl(reg, value);
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}
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}
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#else /* CONFIG_HYPERV */
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static inline void hyperv_init(void) {}
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static inline void hyperv_setup_mmu_ops(void) {}
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@ -209,6 +242,8 @@ static inline int hyperv_flush_guest_mapping_range(u64 as,
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{
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return -1;
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}
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static inline void hv_set_register(unsigned int reg, u64 value) { }
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static inline u64 hv_get_register(unsigned int reg) { return 0; }
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static inline int hv_set_mem_host_visibility(unsigned long addr, int numpages,
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bool visible)
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{
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@ -8,6 +8,7 @@
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/slab.h>
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@ -136,17 +137,24 @@ int hv_synic_alloc(void)
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tasklet_init(&hv_cpu->msg_dpc,
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vmbus_on_msg_dpc, (unsigned long) hv_cpu);
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hv_cpu->synic_message_page =
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(void *)get_zeroed_page(GFP_ATOMIC);
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if (hv_cpu->synic_message_page == NULL) {
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pr_err("Unable to allocate SYNIC message page\n");
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goto err;
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}
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/*
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* Synic message and event pages are allocated by paravisor.
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* Skip these pages allocation here.
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*/
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if (!hv_isolation_type_snp()) {
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hv_cpu->synic_message_page =
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(void *)get_zeroed_page(GFP_ATOMIC);
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if (hv_cpu->synic_message_page == NULL) {
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pr_err("Unable to allocate SYNIC message page\n");
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goto err;
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}
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hv_cpu->synic_event_page = (void *)get_zeroed_page(GFP_ATOMIC);
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if (hv_cpu->synic_event_page == NULL) {
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pr_err("Unable to allocate SYNIC event page\n");
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goto err;
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hv_cpu->synic_event_page =
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(void *)get_zeroed_page(GFP_ATOMIC);
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if (hv_cpu->synic_event_page == NULL) {
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pr_err("Unable to allocate SYNIC event page\n");
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goto err;
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}
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}
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hv_cpu->post_msg_page = (void *)get_zeroed_page(GFP_ATOMIC);
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@ -201,16 +209,35 @@ void hv_synic_enable_regs(unsigned int cpu)
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/* Setup the Synic's message page */
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simp.as_uint64 = hv_get_register(HV_REGISTER_SIMP);
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simp.simp_enabled = 1;
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simp.base_simp_gpa = virt_to_phys(hv_cpu->synic_message_page)
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>> HV_HYP_PAGE_SHIFT;
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if (hv_isolation_type_snp()) {
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hv_cpu->synic_message_page
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= memremap(simp.base_simp_gpa << HV_HYP_PAGE_SHIFT,
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HV_HYP_PAGE_SIZE, MEMREMAP_WB);
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if (!hv_cpu->synic_message_page)
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pr_err("Fail to map syinc message page.\n");
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} else {
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simp.base_simp_gpa = virt_to_phys(hv_cpu->synic_message_page)
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>> HV_HYP_PAGE_SHIFT;
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}
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hv_set_register(HV_REGISTER_SIMP, simp.as_uint64);
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/* Setup the Synic's event page */
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siefp.as_uint64 = hv_get_register(HV_REGISTER_SIEFP);
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siefp.siefp_enabled = 1;
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siefp.base_siefp_gpa = virt_to_phys(hv_cpu->synic_event_page)
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>> HV_HYP_PAGE_SHIFT;
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if (hv_isolation_type_snp()) {
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hv_cpu->synic_event_page =
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memremap(siefp.base_siefp_gpa << HV_HYP_PAGE_SHIFT,
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HV_HYP_PAGE_SIZE, MEMREMAP_WB);
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if (!hv_cpu->synic_event_page)
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pr_err("Fail to map syinc event page.\n");
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} else {
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siefp.base_siefp_gpa = virt_to_phys(hv_cpu->synic_event_page)
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>> HV_HYP_PAGE_SHIFT;
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}
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hv_set_register(HV_REGISTER_SIEFP, siefp.as_uint64);
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@ -257,6 +284,8 @@ int hv_synic_init(unsigned int cpu)
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*/
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void hv_synic_disable_regs(unsigned int cpu)
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{
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struct hv_per_cpu_context *hv_cpu
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= per_cpu_ptr(hv_context.cpu_context, cpu);
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union hv_synic_sint shared_sint;
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union hv_synic_simp simp;
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union hv_synic_siefp siefp;
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@ -273,14 +302,27 @@ void hv_synic_disable_regs(unsigned int cpu)
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shared_sint.as_uint64);
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simp.as_uint64 = hv_get_register(HV_REGISTER_SIMP);
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/*
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* In Isolation VM, sim and sief pages are allocated by
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* paravisor. These pages also will be used by kdump
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* kernel. So just reset enable bit here and keep page
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* addresses.
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*/
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simp.simp_enabled = 0;
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simp.base_simp_gpa = 0;
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if (hv_isolation_type_snp())
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memunmap(hv_cpu->synic_message_page);
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else
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simp.base_simp_gpa = 0;
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hv_set_register(HV_REGISTER_SIMP, simp.as_uint64);
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siefp.as_uint64 = hv_get_register(HV_REGISTER_SIEFP);
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siefp.siefp_enabled = 0;
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siefp.base_siefp_gpa = 0;
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if (hv_isolation_type_snp())
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memunmap(hv_cpu->synic_event_page);
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else
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siefp.base_siefp_gpa = 0;
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hv_set_register(HV_REGISTER_SIEFP, siefp.as_uint64);
|
||||
|
||||
|
|
|
|||
|
|
@ -249,6 +249,12 @@ bool __weak hv_is_isolation_supported(void)
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(hv_is_isolation_supported);
|
||||
|
||||
bool __weak hv_isolation_type_snp(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(hv_isolation_type_snp);
|
||||
|
||||
void __weak hv_setup_vmbus_handler(void (*handler)(void))
|
||||
{
|
||||
}
|
||||
|
|
|
|||
|
|
@ -54,6 +54,7 @@ extern void __percpu **hyperv_pcpu_output_arg;
|
|||
|
||||
extern u64 hv_do_hypercall(u64 control, void *inputaddr, void *outputaddr);
|
||||
extern u64 hv_do_fast_hypercall8(u16 control, u64 input8);
|
||||
extern bool hv_isolation_type_snp(void);
|
||||
|
||||
/* Helper functions that provide a consistent pattern for checking Hyper-V hypercall status. */
|
||||
static inline int hv_result(u64 status)
|
||||
|
|
|
|||
Loading…
Reference in New Issue