ARM: dts: dra72-evm-revc: enable irqs for dp83867 eth phys
TI DRA72-EVM Rev C has two DP83867 ethernet phys which support IRQ generation in case of phy/link status changes. The INT/PWDN lines from both DP83867 phys are wired to DRA7 gpio6.16, so reflect the same in DT. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -68,6 +68,8 @@
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
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ti,min-output-impedance;
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ti,min-output-impedance;
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interrupt-parent = <&gpio6>;
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interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
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};
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};
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dp83867_1: ethernet-phy@3 {
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dp83867_1: ethernet-phy@3 {
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@ -75,6 +77,8 @@
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
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ti,min-output-imepdance;
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ti,min-output-impedance;
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interrupt-parent = <&gpio6>;
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interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
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};
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};
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};
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};
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