x86, devicetree, irq: Use common mechanism to support irqdomain
Now the ioapic driver provides a common interface to create irqdomain, so replace the private implementation. Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Joerg Roedel <joro@8bytes.org> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Grant Likely <grant.likely@linaro.org> Cc: Rafael J. Wysocki <rjw@rjwysocki.net> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Tony Lindgren <tony@atomide.com> Link: http://lkml.kernel.org/r/1402302011-23642-29-git-send-email-jiang.liu@linux.intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Jiang Liu
Thomas Gleixner
parent
1b5d3e00d4
commit
facd8fdb25
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@ -26,12 +26,10 @@
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extern int of_ioapic;
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extern u64 initial_dtb;
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extern void add_dtb(u64 data);
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extern void x86_add_irq_domains(void);
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void x86_of_pci_init(void);
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void x86_dtb_init(void);
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#else
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static inline void add_dtb(u64 data) { }
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static inline void x86_add_irq_domains(void) { }
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static inline void x86_of_pci_init(void) { }
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static inline void x86_dtb_init(void) { }
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#define of_ioapic 0
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@ -166,10 +166,82 @@ static void __init dtb_lapic_setup(void)
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#ifdef CONFIG_X86_IO_APIC
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static unsigned int ioapic_id;
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struct of_ioapic_type {
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u32 out_type;
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u32 trigger;
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u32 polarity;
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};
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static struct of_ioapic_type of_ioapic_type[] =
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{
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{
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.out_type = IRQ_TYPE_EDGE_RISING,
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.trigger = IOAPIC_EDGE,
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.polarity = 1,
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},
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{
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.out_type = IRQ_TYPE_LEVEL_LOW,
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.trigger = IOAPIC_LEVEL,
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.polarity = 0,
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},
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{
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.out_type = IRQ_TYPE_LEVEL_HIGH,
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.trigger = IOAPIC_LEVEL,
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.polarity = 1,
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},
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{
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.out_type = IRQ_TYPE_EDGE_FALLING,
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.trigger = IOAPIC_EDGE,
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.polarity = 0,
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},
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};
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static int ioapic_xlate(struct irq_domain *domain,
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struct device_node *controller,
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const u32 *intspec, u32 intsize,
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irq_hw_number_t *out_hwirq, u32 *out_type)
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{
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struct io_apic_irq_attr attr;
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struct of_ioapic_type *it;
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u32 line, idx;
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int rc;
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if (WARN_ON(intsize < 2))
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return -EINVAL;
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line = intspec[0];
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if (intspec[1] >= ARRAY_SIZE(of_ioapic_type))
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return -EINVAL;
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it = &of_ioapic_type[intspec[1]];
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idx = (u32)(long)domain->host_data;
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set_io_apic_irq_attr(&attr, idx, line, it->trigger, it->polarity);
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rc = io_apic_setup_irq_pin_once(irq_find_mapping(domain, line),
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cpu_to_node(0), &attr);
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if (rc)
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return rc;
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*out_hwirq = line;
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*out_type = it->out_type;
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return 0;
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}
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const struct irq_domain_ops ioapic_irq_domain_ops = {
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.xlate = ioapic_xlate,
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};
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static void __init dtb_add_ioapic(struct device_node *dn)
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{
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struct resource r;
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int ret;
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struct ioapic_domain_cfg cfg = {
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.type = IOAPIC_DOMAIN_DYNAMIC,
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.ops = &ioapic_irq_domain_ops,
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.dev = dn,
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};
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ret = of_address_to_resource(dn, 0, &r);
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if (ret) {
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@ -177,7 +249,7 @@ static void __init dtb_add_ioapic(struct device_node *dn)
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dn->full_name);
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return;
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}
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mp_register_ioapic(++ioapic_id, r.start, gsi_top, NULL);
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mp_register_ioapic(++ioapic_id, r.start, gsi_top, &cfg);
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}
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static void __init dtb_ioapic_setup(void)
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@ -239,148 +311,3 @@ void __init x86_dtb_init(void)
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dtb_setup_hpet();
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dtb_apic_setup();
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}
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#ifdef CONFIG_X86_IO_APIC
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struct of_ioapic_type {
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u32 out_type;
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u32 trigger;
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u32 polarity;
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};
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static struct of_ioapic_type of_ioapic_type[] =
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{
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{
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.out_type = IRQ_TYPE_EDGE_RISING,
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.trigger = IOAPIC_EDGE,
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.polarity = 1,
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},
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{
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.out_type = IRQ_TYPE_LEVEL_LOW,
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.trigger = IOAPIC_LEVEL,
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.polarity = 0,
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},
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{
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.out_type = IRQ_TYPE_LEVEL_HIGH,
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.trigger = IOAPIC_LEVEL,
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.polarity = 1,
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},
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{
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.out_type = IRQ_TYPE_EDGE_FALLING,
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.trigger = IOAPIC_EDGE,
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.polarity = 0,
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},
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};
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static int ioapic_xlate(struct irq_domain *domain,
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struct device_node *controller,
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const u32 *intspec, u32 intsize,
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irq_hw_number_t *out_hwirq, u32 *out_type)
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{
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struct io_apic_irq_attr attr;
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struct of_ioapic_type *it;
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u32 line, idx;
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int rc;
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if (WARN_ON(intsize < 2))
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return -EINVAL;
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line = intspec[0];
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if (intspec[1] >= ARRAY_SIZE(of_ioapic_type))
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return -EINVAL;
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it = &of_ioapic_type[intspec[1]];
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idx = (u32) domain->host_data;
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set_io_apic_irq_attr(&attr, idx, line, it->trigger, it->polarity);
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rc = io_apic_setup_irq_pin_once(irq_find_mapping(domain, line),
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cpu_to_node(0), &attr);
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if (rc)
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return rc;
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*out_hwirq = line;
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*out_type = it->out_type;
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return 0;
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}
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const struct irq_domain_ops ioapic_irq_domain_ops = {
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.xlate = ioapic_xlate,
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};
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static void dt_add_ioapic_domain(unsigned int ioapic_num,
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struct device_node *np)
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{
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struct irq_domain *id;
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struct mp_ioapic_gsi *gsi_cfg;
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int ret;
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int num, legacy_irqs = nr_legacy_irqs();
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gsi_cfg = mp_ioapic_gsi_routing(ioapic_num);
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num = gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1;
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id = irq_domain_add_linear(np, num, &ioapic_irq_domain_ops,
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(void *)ioapic_num);
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BUG_ON(!id);
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if (gsi_cfg->gsi_base == 0) {
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/*
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* The first nr_legacy_irqs() irq descs are allocated in
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* early_irq_init() and need just a mapping. The
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* remaining irqs need both. All of them are preallocated
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* and assigned so we can keep the 1:1 mapping which the ioapic
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* is having.
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*/
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irq_domain_associate_many(id, 0, 0, legacy_irqs);
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if (num > legacy_irqs) {
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ret = irq_create_strict_mappings(id, legacy_irqs,
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legacy_irqs, num - legacy_irqs);
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if (ret)
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pr_err("Error creating mapping for the "
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"remaining IRQs: %d\n", ret);
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}
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irq_set_default_host(id);
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} else {
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ret = irq_create_strict_mappings(id, gsi_cfg->gsi_base, 0, num);
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if (ret)
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pr_err("Error creating IRQ mapping: %d\n", ret);
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}
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}
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static void __init ioapic_add_ofnode(struct device_node *np)
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{
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struct resource r;
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int i, ret;
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ret = of_address_to_resource(np, 0, &r);
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if (ret) {
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printk(KERN_ERR "Failed to obtain address for %s\n",
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np->full_name);
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return;
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}
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for (i = 0; i < nr_ioapics; i++) {
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if (r.start == mpc_ioapic_addr(i)) {
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dt_add_ioapic_domain(i, np);
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return;
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}
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}
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printk(KERN_ERR "IOxAPIC at %s is not registered.\n", np->full_name);
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}
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void __init x86_add_irq_domains(void)
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{
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struct device_node *dp;
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if (!of_have_populated_dt())
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return;
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for_each_node_with_property(dp, "interrupt-controller") {
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if (of_device_is_compatible(dp, "intel,ce4100-ioapic"))
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ioapic_add_ofnode(dp);
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}
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}
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#else
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void __init x86_add_irq_domains(void) { }
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#endif
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@ -86,12 +86,6 @@ void __init init_IRQ(void)
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{
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int i;
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/*
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* We probably need a better place for this, but it works for
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* now ...
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*/
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x86_add_irq_domains();
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/*
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* On cpu 0, Assign IRQ0_VECTOR..IRQ15_VECTOR's to IRQ 0..15.
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* If these IRQ's are handled by legacy interrupt-controllers like PIC,
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