Merge branch 'for-4.5-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata
Pull libata fixes from Tejun Heo: "Assorted fixes for libata drivers. - Turns out HDIO_GET_32BIT ioctl was subtly broken all along. - Recent update to ahci external port handling was incorrectly marking hotpluggable ports as external making userland handle devices connected to those ports incorrectly. - ahci_xgene needs its own irq handler to work around a hardware erratum. libahci updated to allow irq handler override. - Misc driver specific updates" * 'for-4.5-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata: ata: ahci: don't mark HotPlugCapable Ports as external/removable ahci: Workaround for ThunderX Errata#22536 libata: Align ata_device's id on a cacheline Adding Intel Lewisburg device IDs for SATA pata-rb532-cf: get rid of the irq_to_gpio() call libata: fix HDIO_GET_32BIT ioctl ahci_xgene: Implement the workaround to fix the missing of the edge interrupt for the HOST_IRQ_STAT. ata: Remove the AHCI_HFLAG_EDGE_IRQ support from libahci. libahci: Implement the capability to override the generic ahci interrupt handler.
This commit is contained in:
commit
fab3e94a62
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@ -367,15 +367,21 @@ static const struct pci_device_id ahci_pci_tbl[] = {
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{ PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
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{ PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
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{ PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
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{ PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
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{ PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
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{ PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
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{ PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
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{ PCI_VDEVICE(INTEL, 0xa184), board_ahci }, /* Lewisburg RAID*/
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{ PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
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{ PCI_VDEVICE(INTEL, 0xa18e), board_ahci }, /* Lewisburg RAID*/
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{ PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
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{ PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
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{ PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
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{ PCI_VDEVICE(INTEL, 0xa204), board_ahci }, /* Lewisburg RAID*/
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{ PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
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{ PCI_VDEVICE(INTEL, 0xa20e), board_ahci }, /* Lewisburg RAID*/
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{ PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
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{ PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
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/* JMicron 360/1/3/5/6, match class to avoid IDE function */
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{ PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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@ -1325,6 +1331,44 @@ static inline void ahci_gtf_filter_workaround(struct ata_host *host)
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{}
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#endif
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#ifdef CONFIG_ARM64
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/*
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* Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
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* Workaround is to make sure all pending IRQs are served before leaving
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* handler.
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*/
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static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
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{
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struct ata_host *host = dev_instance;
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struct ahci_host_priv *hpriv;
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unsigned int rc = 0;
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void __iomem *mmio;
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u32 irq_stat, irq_masked;
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unsigned int handled = 1;
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VPRINTK("ENTER\n");
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hpriv = host->private_data;
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mmio = hpriv->mmio;
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irq_stat = readl(mmio + HOST_IRQ_STAT);
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if (!irq_stat)
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return IRQ_NONE;
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do {
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irq_masked = irq_stat & hpriv->port_map;
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spin_lock(&host->lock);
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rc = ahci_handle_port_intr(host, irq_masked);
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if (!rc)
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handled = 0;
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writel(irq_stat, mmio + HOST_IRQ_STAT);
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irq_stat = readl(mmio + HOST_IRQ_STAT);
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spin_unlock(&host->lock);
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} while (irq_stat);
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VPRINTK("EXIT\n");
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return IRQ_RETVAL(handled);
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}
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#endif
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/*
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* ahci_init_msix() - optionally enable per-port MSI-X otherwise defer
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* to single msi.
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@ -1560,6 +1604,11 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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if (ahci_broken_devslp(pdev))
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hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
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#ifdef CONFIG_ARM64
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if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
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hpriv->irq_handler = ahci_thunderx_irq_handler;
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#endif
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/* save initial config */
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ahci_pci_save_initial_config(pdev, hpriv);
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@ -240,8 +240,7 @@ enum {
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error-handling stage) */
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AHCI_HFLAG_NO_DEVSLP = (1 << 17), /* no device sleep */
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AHCI_HFLAG_NO_FBS = (1 << 18), /* no FBS */
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AHCI_HFLAG_EDGE_IRQ = (1 << 19), /* HOST_IRQ_STAT behaves as
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Edge Triggered */
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#ifdef CONFIG_PCI_MSI
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AHCI_HFLAG_MULTI_MSI = (1 << 20), /* multiple PCI MSIs */
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AHCI_HFLAG_MULTI_MSIX = (1 << 21), /* per-port MSI-X */
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@ -361,6 +360,7 @@ struct ahci_host_priv {
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* be overridden anytime before the host is activated.
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*/
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void (*start_engine)(struct ata_port *ap);
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irqreturn_t (*irq_handler)(int irq, void *dev_instance);
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};
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#ifdef CONFIG_PCI_MSI
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@ -424,6 +424,7 @@ int ahci_reset_em(struct ata_host *host);
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void ahci_print_info(struct ata_host *host, const char *scc_s);
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int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht);
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void ahci_error_handler(struct ata_port *ap);
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u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked);
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static inline void __iomem *__ahci_port_base(struct ata_host *host,
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unsigned int port_no)
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@ -548,6 +548,88 @@ softreset_retry:
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return rc;
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}
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/**
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* xgene_ahci_handle_broken_edge_irq - Handle the broken irq.
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* @ata_host: Host that recieved the irq
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* @irq_masked: HOST_IRQ_STAT value
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*
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* For hardware with broken edge trigger latch
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* the HOST_IRQ_STAT register misses the edge interrupt
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* when clearing of HOST_IRQ_STAT register and hardware
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* reporting the PORT_IRQ_STAT register at the
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* same clock cycle.
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* As such, the algorithm below outlines the workaround.
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*
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* 1. Read HOST_IRQ_STAT register and save the state.
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* 2. Clear the HOST_IRQ_STAT register.
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* 3. Read back the HOST_IRQ_STAT register.
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* 4. If HOST_IRQ_STAT register equals to zero, then
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* traverse the rest of port's PORT_IRQ_STAT register
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* to check if an interrupt is triggered at that point else
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* go to step 6.
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* 5. If PORT_IRQ_STAT register of rest ports is not equal to zero
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* then update the state of HOST_IRQ_STAT saved in step 1.
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* 6. Handle port interrupts.
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* 7. Exit
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*/
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static int xgene_ahci_handle_broken_edge_irq(struct ata_host *host,
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u32 irq_masked)
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{
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struct ahci_host_priv *hpriv = host->private_data;
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void __iomem *port_mmio;
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int i;
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if (!readl(hpriv->mmio + HOST_IRQ_STAT)) {
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for (i = 0; i < host->n_ports; i++) {
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if (irq_masked & (1 << i))
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continue;
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port_mmio = ahci_port_base(host->ports[i]);
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if (readl(port_mmio + PORT_IRQ_STAT))
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irq_masked |= (1 << i);
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}
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}
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return ahci_handle_port_intr(host, irq_masked);
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}
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static irqreturn_t xgene_ahci_irq_intr(int irq, void *dev_instance)
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{
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struct ata_host *host = dev_instance;
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struct ahci_host_priv *hpriv;
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unsigned int rc = 0;
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void __iomem *mmio;
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u32 irq_stat, irq_masked;
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VPRINTK("ENTER\n");
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hpriv = host->private_data;
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mmio = hpriv->mmio;
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/* sigh. 0xffffffff is a valid return from h/w */
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irq_stat = readl(mmio + HOST_IRQ_STAT);
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if (!irq_stat)
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return IRQ_NONE;
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irq_masked = irq_stat & hpriv->port_map;
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spin_lock(&host->lock);
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/*
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* HOST_IRQ_STAT behaves as edge triggered latch meaning that
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* it should be cleared before all the port events are cleared.
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*/
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writel(irq_stat, mmio + HOST_IRQ_STAT);
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rc = xgene_ahci_handle_broken_edge_irq(host, irq_masked);
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spin_unlock(&host->lock);
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VPRINTK("EXIT\n");
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return IRQ_RETVAL(rc);
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}
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static struct ata_port_operations xgene_ahci_v1_ops = {
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.inherits = &ahci_ops,
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.host_stop = xgene_ahci_host_stop,
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hpriv->flags = AHCI_HFLAG_NO_NCQ;
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break;
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case XGENE_AHCI_V2:
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hpriv->flags |= AHCI_HFLAG_YES_FBS | AHCI_HFLAG_EDGE_IRQ;
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hpriv->flags |= AHCI_HFLAG_YES_FBS;
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hpriv->irq_handler = xgene_ahci_irq_intr;
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break;
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default:
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break;
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@ -113,6 +113,7 @@ static ssize_t ahci_store_em_buffer(struct device *dev,
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const char *buf, size_t size);
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static ssize_t ahci_show_em_supported(struct device *dev,
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struct device_attribute *attr, char *buf);
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static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance);
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static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
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static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
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@ -512,6 +513,9 @@ void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
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if (!hpriv->start_engine)
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hpriv->start_engine = ahci_start_engine;
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if (!hpriv->irq_handler)
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hpriv->irq_handler = ahci_single_level_irq_intr;
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}
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EXPORT_SYMBOL_GPL(ahci_save_initial_config);
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@ -1164,8 +1168,7 @@ static void ahci_port_init(struct device *dev, struct ata_port *ap,
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/* mark esata ports */
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tmp = readl(port_mmio + PORT_CMD);
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if ((tmp & PORT_CMD_HPCP) ||
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((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS)))
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if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS))
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ap->pflags |= ATA_PFLAG_EXTERNAL;
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}
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@ -1846,7 +1849,7 @@ static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
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return IRQ_HANDLED;
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}
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static u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
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u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
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{
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unsigned int i, handled = 0;
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@ -1872,43 +1875,7 @@ static u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
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return handled;
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}
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static irqreturn_t ahci_single_edge_irq_intr(int irq, void *dev_instance)
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{
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struct ata_host *host = dev_instance;
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struct ahci_host_priv *hpriv;
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unsigned int rc = 0;
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void __iomem *mmio;
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u32 irq_stat, irq_masked;
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VPRINTK("ENTER\n");
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hpriv = host->private_data;
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mmio = hpriv->mmio;
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/* sigh. 0xffffffff is a valid return from h/w */
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irq_stat = readl(mmio + HOST_IRQ_STAT);
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if (!irq_stat)
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return IRQ_NONE;
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irq_masked = irq_stat & hpriv->port_map;
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spin_lock(&host->lock);
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/*
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* HOST_IRQ_STAT behaves as edge triggered latch meaning that
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* it should be cleared before all the port events are cleared.
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*/
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writel(irq_stat, mmio + HOST_IRQ_STAT);
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rc = ahci_handle_port_intr(host, irq_masked);
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spin_unlock(&host->lock);
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VPRINTK("EXIT\n");
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return IRQ_RETVAL(rc);
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}
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EXPORT_SYMBOL_GPL(ahci_handle_port_intr);
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static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
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{
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@ -2535,14 +2502,18 @@ int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht)
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int irq = hpriv->irq;
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int rc;
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if (hpriv->flags & (AHCI_HFLAG_MULTI_MSI | AHCI_HFLAG_MULTI_MSIX))
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if (hpriv->flags & (AHCI_HFLAG_MULTI_MSI | AHCI_HFLAG_MULTI_MSIX)) {
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if (hpriv->irq_handler)
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dev_warn(host->dev, "both AHCI_HFLAG_MULTI_MSI flag set \
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and custom irq handler implemented\n");
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rc = ahci_host_activate_multi_irqs(host, sht);
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else if (hpriv->flags & AHCI_HFLAG_EDGE_IRQ)
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rc = ata_host_activate(host, irq, ahci_single_edge_irq_intr,
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IRQF_SHARED, sht);
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else
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rc = ata_host_activate(host, irq, ahci_single_level_irq_intr,
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} else {
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rc = ata_host_activate(host, irq, hpriv->irq_handler,
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IRQF_SHARED, sht);
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}
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return rc;
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}
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EXPORT_SYMBOL_GPL(ahci_host_activate);
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@ -675,19 +675,18 @@ static int ata_ioc32(struct ata_port *ap)
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int ata_sas_scsi_ioctl(struct ata_port *ap, struct scsi_device *scsidev,
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int cmd, void __user *arg)
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{
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int val = -EINVAL, rc = -EINVAL;
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unsigned long val;
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int rc = -EINVAL;
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unsigned long flags;
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switch (cmd) {
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case ATA_IOC_GET_IO32:
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case HDIO_GET_32BIT:
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spin_lock_irqsave(ap->lock, flags);
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val = ata_ioc32(ap);
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spin_unlock_irqrestore(ap->lock, flags);
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if (copy_to_user(arg, &val, 1))
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return -EFAULT;
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return 0;
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return put_user(val, (unsigned long __user *)arg);
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case ATA_IOC_SET_IO32:
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case HDIO_SET_32BIT:
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val = (unsigned long) arg;
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rc = 0;
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spin_lock_irqsave(ap->lock, flags);
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@ -32,6 +32,8 @@
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#include <linux/libata.h>
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#include <scsi/scsi_host.h>
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#include <asm/mach-rc32434/rb.h>
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#define DRV_NAME "pata-rb532-cf"
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#define DRV_VERSION "0.1.0"
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#define DRV_DESC "PATA driver for RouterBOARD 532 Compact Flash"
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@ -107,6 +109,7 @@ static int rb532_pata_driver_probe(struct platform_device *pdev)
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int gpio;
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struct resource *res;
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struct ata_host *ah;
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struct cf_device *pdata;
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struct rb532_cf_info *info;
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int ret;
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@ -122,7 +125,13 @@ static int rb532_pata_driver_probe(struct platform_device *pdev)
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return -ENOENT;
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}
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gpio = irq_to_gpio(irq);
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pdata = dev_get_platdata(&pdev->dev);
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if (!pdata) {
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dev_err(&pdev->dev, "no platform data specified\n");
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return -EINVAL;
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}
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gpio = pdata->gpio_pin;
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if (gpio < 0) {
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dev_err(&pdev->dev, "no GPIO found for irq%d\n", irq);
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return -ENOENT;
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@ -487,8 +487,8 @@ enum ata_tf_protocols {
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};
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enum ata_ioctls {
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ATA_IOC_GET_IO32 = 0x309,
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ATA_IOC_SET_IO32 = 0x324,
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ATA_IOC_GET_IO32 = 0x309, /* HDIO_GET_32BIT */
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ATA_IOC_SET_IO32 = 0x324, /* HDIO_SET_32BIT */
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};
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/* core structures */
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@ -720,7 +720,7 @@ struct ata_device {
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union {
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u16 id[ATA_ID_WORDS]; /* IDENTIFY xxx DEVICE data */
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u32 gscr[SATA_PMP_GSCR_DWORDS]; /* PMP GSCR block */
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};
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} ____cacheline_aligned;
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/* DEVSLP Timing Variables from Identify Device Data Log */
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u8 devslp_timing[ATA_LOG_DEVSLP_SIZE];
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||||
|
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