iio: resolver: ad2s90: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Fixes tag is probably not where the issue was first introduced, but
is likely to be far beyond the point where anyone considers
backporting this fix.
Fixes: 58f08b0af8
("staging:iio:resolver:ad2s90 general cleanup")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-90-jic23@kernel.org
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@ -24,7 +24,7 @@
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struct ad2s90_state {
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struct mutex lock; /* lock to protect rx buffer */
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struct spi_device *sdev;
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u8 rx[2] ____cacheline_aligned;
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u8 rx[2] __aligned(IIO_DMA_MINALIGN);
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};
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static int ad2s90_read_raw(struct iio_dev *indio_dev,
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