mtd: nand: fsl_ifc: Fix nand waitfunc return value
As per the IFC hardware manual, Most significant 2 bytes in
nand_fsr register are the outcome of NAND READ STATUS command.
So status value need to be shifted and aligned as per the nand
framework requirement.
Fixes: 82771882d9
("NAND Machine support for Integrated Flash Controller")
Cc: stable@vger.kernel.org # v3.18+
Signed-off-by: Jagdish Gediya <jagdish.gediya@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
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@ -626,6 +626,7 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
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struct fsl_ifc_ctrl *ctrl = priv->ctrl;
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struct fsl_ifc_ctrl *ctrl = priv->ctrl;
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struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
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struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
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u32 nand_fsr;
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u32 nand_fsr;
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int status;
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/* Use READ_STATUS command, but wait for the device to be ready */
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/* Use READ_STATUS command, but wait for the device to be ready */
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ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
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ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
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@ -640,12 +641,12 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
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fsl_ifc_run_command(mtd);
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fsl_ifc_run_command(mtd);
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nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
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nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
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status = nand_fsr >> 24;
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/*
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/*
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* The chip always seems to report that it is
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* The chip always seems to report that it is
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* write-protected, even when it is not.
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* write-protected, even when it is not.
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*/
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*/
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return nand_fsr | NAND_STATUS_WP;
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return status | NAND_STATUS_WP;
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}
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}
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/*
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/*
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