ARM: 6458/1: pcmcia: Adds nanoEngine PCMCIA support.
This patch adds nanoEngine PCMCIA support, with support for two sockets. In order to have a fully functional pcmcia subsystem in a BSE nanoEngine board you should carefully read this: http://cambuca.ldhs.cetuc.puc-rio.br/nanoengine/ Acked-by: Dominik Brodowski <linux@dominikbrodowski.net> Signed-off-by: Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Marcelo Roberto Jimenez
Russell King
parent
17b38ebb6a
commit
fa87672ab3
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@ -0,0 +1,30 @@
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/*
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* arch/arm/mach-sa1100/include/mach/nanoengine.h
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*
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* This file contains the hardware specific definitions for nanoEngine.
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* Only include this file from SA1100-specific files.
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*
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* Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef __ASM_ARCH_NANOENGINE_H
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#define __ASM_ARCH_NANOENGINE_H
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#define GPIO_PC_READY0 GPIO_GPIO(11) /* ready for socket 0 (active high)*/
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#define GPIO_PC_READY1 GPIO_GPIO(12) /* ready for socket 1 (active high) */
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#define GPIO_PC_CD0 GPIO_GPIO(13) /* detect for socket 0 (active low) */
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#define GPIO_PC_CD1 GPIO_GPIO(14) /* detect for socket 1 (active low) */
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#define GPIO_PC_RESET0 GPIO_GPIO(15) /* reset socket 0 */
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#define GPIO_PC_RESET1 GPIO_GPIO(16) /* reset socket 1 */
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#define NANOENGINE_IRQ_GPIO_PC_READY0 IRQ_GPIO11
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#define NANOENGINE_IRQ_GPIO_PC_READY1 IRQ_GPIO12
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#define NANOENGINE_IRQ_GPIO_PC_CD0 IRQ_GPIO13
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#define NANOENGINE_IRQ_GPIO_PC_CD1 IRQ_GPIO14
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#endif
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@ -3,7 +3,7 @@
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*
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* Bright Star Engineering's nanoEngine board init code.
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*
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* Copyright (C) 2009 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
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* Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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@ -50,8 +50,9 @@ sa1111_cs-$(CONFIG_SA1100_JORNADA720) += sa1100_jornada720.o
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sa1100_cs-y += sa1100_generic.o
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sa1100_cs-$(CONFIG_SA1100_ASSABET) += sa1100_assabet.o
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sa1100_cs-$(CONFIG_SA1100_CERF) += sa1100_cerf.o
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sa1100_cs-$(CONFIG_SA1100_COLLIE) += pxa2xx_sharpsl.o
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sa1100_cs-$(CONFIG_SA1100_COLLIE) += pxa2xx_sharpsl.o
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sa1100_cs-$(CONFIG_SA1100_H3600) += sa1100_h3600.o
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sa1100_cs-$(CONFIG_SA1100_NANOENGINE) += sa1100_nanoengine.o
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sa1100_cs-$(CONFIG_SA1100_SHANNON) += sa1100_shannon.o
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sa1100_cs-$(CONFIG_SA1100_SIMPAD) += sa1100_simpad.o
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@ -53,6 +53,9 @@ static int (*sa11x0_pcmcia_hw_init[])(struct device *dev) = {
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#if defined(CONFIG_SA1100_H3100) || defined(CONFIG_SA1100_H3600)
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pcmcia_h3600_init,
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#endif
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#ifdef CONFIG_SA1100_NANOENGINE
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pcmcia_nanoengine_init,
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#endif
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#ifdef CONFIG_SA1100_SHANNON
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pcmcia_shannon_init,
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#endif
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@ -13,6 +13,7 @@ extern int pcmcia_freebird_init(struct device *);
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extern int pcmcia_gcplus_init(struct device *);
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extern int pcmcia_graphicsmaster_init(struct device *);
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extern int pcmcia_h3600_init(struct device *);
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extern int pcmcia_nanoengine_init(struct device *);
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extern int pcmcia_pangolin_init(struct device *);
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extern int pcmcia_pfs168_init(struct device *);
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extern int pcmcia_shannon_init(struct device *);
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@ -0,0 +1,219 @@
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/*
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* drivers/pcmcia/sa1100_nanoengine.c
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*
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* PCMCIA implementation routines for BSI nanoEngine.
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*
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* In order to have a fully functional pcmcia subsystem in a BSE nanoEngine
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* board you should carefully read this:
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* http://cambuca.ldhs.cetuc.puc-rio.br/nanoengine/
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*
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* Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
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*
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* Based on original work for kernel 2.4 by
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* Miguel Freitas <miguel@cpti.cetuc.puc-rio.br>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/signal.h>
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#include <asm/mach-types.h>
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#include <asm/irq.h>
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#include <mach/hardware.h>
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#include <mach/nanoengine.h>
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#include "sa1100_generic.h"
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static struct pcmcia_irqs irqs_skt0[] = {
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/* socket, IRQ, name */
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{ 0, NANOENGINE_IRQ_GPIO_PC_CD0, "PC CD0" },
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};
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static struct pcmcia_irqs irqs_skt1[] = {
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/* socket, IRQ, name */
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{ 1, NANOENGINE_IRQ_GPIO_PC_CD1, "PC CD1" },
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};
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struct nanoengine_pins {
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unsigned input_pins;
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unsigned output_pins;
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unsigned clear_outputs;
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unsigned transition_pins;
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unsigned pci_irq;
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struct pcmcia_irqs *pcmcia_irqs;
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unsigned pcmcia_irqs_size;
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};
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static struct nanoengine_pins nano_skts[] = {
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{
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.input_pins = GPIO_PC_READY0 | GPIO_PC_CD0,
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.output_pins = GPIO_PC_RESET0,
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.clear_outputs = GPIO_PC_RESET0,
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.transition_pins = NANOENGINE_IRQ_GPIO_PC_CD0,
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.pci_irq = NANOENGINE_IRQ_GPIO_PC_READY0,
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.pcmcia_irqs = irqs_skt0,
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.pcmcia_irqs_size = ARRAY_SIZE(irqs_skt0)
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}, {
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.input_pins = GPIO_PC_READY1 | GPIO_PC_CD1,
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.output_pins = GPIO_PC_RESET1,
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.clear_outputs = GPIO_PC_RESET1,
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.transition_pins = NANOENGINE_IRQ_GPIO_PC_CD1,
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.pci_irq = NANOENGINE_IRQ_GPIO_PC_READY1,
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.pcmcia_irqs = irqs_skt1,
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.pcmcia_irqs_size = ARRAY_SIZE(irqs_skt1)
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}
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};
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unsigned num_nano_pcmcia_sockets = ARRAY_SIZE(nano_skts);
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static int nanoengine_pcmcia_hw_init(struct soc_pcmcia_socket *skt)
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{
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unsigned i = skt->nr;
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if (i >= num_nano_pcmcia_sockets)
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return -ENXIO;
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GPDR &= ~nano_skts[i].input_pins;
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GPDR |= nano_skts[i].output_pins;
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GPCR = nano_skts[i].clear_outputs;
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set_irq_type(nano_skts[i].transition_pins, IRQ_TYPE_EDGE_BOTH);
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skt->socket.pci_irq = nano_skts[i].pci_irq;
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return soc_pcmcia_request_irqs(skt,
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nano_skts[i].pcmcia_irqs, nano_skts[i].pcmcia_irqs_size);
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}
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/*
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* Release all resources.
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*/
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static void nanoengine_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt)
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{
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unsigned i = skt->nr;
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if (i >= num_nano_pcmcia_sockets)
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return;
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soc_pcmcia_free_irqs(skt,
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nano_skts[i].pcmcia_irqs, nano_skts[i].pcmcia_irqs_size);
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}
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static int nanoengine_pcmcia_configure_socket(
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struct soc_pcmcia_socket *skt, const socket_state_t *state)
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{
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unsigned reset;
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unsigned i = skt->nr;
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if (i >= num_nano_pcmcia_sockets)
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return -ENXIO;
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switch (i) {
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case 0:
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reset = GPIO_PC_RESET0;
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break;
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case 1:
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reset = GPIO_PC_RESET1;
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break;
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default:
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return -ENXIO;
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}
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if (state->flags & SS_RESET)
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GPSR = reset;
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else
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GPCR = reset;
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return 0;
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}
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static void nanoengine_pcmcia_socket_state(
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struct soc_pcmcia_socket *skt, struct pcmcia_state *state)
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{
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unsigned long levels = GPLR;
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unsigned i = skt->nr;
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if (i >= num_nano_pcmcia_sockets)
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return;
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memset(state, 0, sizeof(struct pcmcia_state));
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switch (i) {
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case 0:
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state->ready = (levels & GPIO_PC_READY0) ? 1 : 0;
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state->detect = !(levels & GPIO_PC_CD0) ? 1 : 0;
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break;
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case 1:
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state->ready = (levels & GPIO_PC_READY1) ? 1 : 0;
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state->detect = !(levels & GPIO_PC_CD1) ? 1 : 0;
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break;
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default:
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return;
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}
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state->bvd1 = 1;
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state->bvd2 = 1;
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state->wrprot = 0; /* Not available */
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state->vs_3v = 1; /* Can only apply 3.3V */
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state->vs_Xv = 0;
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}
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/*
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* Enable card status IRQs on (re-)initialisation. This can
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* be called at initialisation, power management event, or
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* pcmcia event.
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*/
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static void nanoengine_pcmcia_socket_init(struct soc_pcmcia_socket *skt)
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{
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unsigned i = skt->nr;
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if (i >= num_nano_pcmcia_sockets)
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return;
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soc_pcmcia_enable_irqs(skt,
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nano_skts[i].pcmcia_irqs, nano_skts[i].pcmcia_irqs_size);
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}
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/*
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* Disable card status IRQs on suspend.
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*/
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static void nanoengine_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt)
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{
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unsigned i = skt->nr;
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if (i >= num_nano_pcmcia_sockets)
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return;
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soc_pcmcia_disable_irqs(skt,
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nano_skts[i].pcmcia_irqs, nano_skts[i].pcmcia_irqs_size);
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}
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static struct pcmcia_low_level nanoengine_pcmcia_ops = {
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.owner = THIS_MODULE,
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.hw_init = nanoengine_pcmcia_hw_init,
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.hw_shutdown = nanoengine_pcmcia_hw_shutdown,
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.configure_socket = nanoengine_pcmcia_configure_socket,
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.socket_state = nanoengine_pcmcia_socket_state,
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.socket_init = nanoengine_pcmcia_socket_init,
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.socket_suspend = nanoengine_pcmcia_socket_suspend,
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};
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int pcmcia_nanoengine_init(struct device *dev)
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{
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int ret = -ENODEV;
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if (machine_is_nanoengine())
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ret = sa11xx_drv_pcmcia_probe(
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dev, &nanoengine_pcmcia_ops, 0, 2);
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return ret;
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}
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