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drm/amd/display: Allow clock lower on dce100 

dce100 was set to always pass safe_to_lower = false
to the clock manager

Thus, on suspend the clocks were not being set to 0
which is incorrect behaviour

This was causing s3 resume to blackscreen on intel
CPUs with dce100 GPUs attached

(Note that the hash in this Fixes: tag is the hash on Alex's tree)
Fixes: ae7d8aeb38d7 ("drm/amd/display: remove safe_to_lower flag from dc, use 2 functions instead")

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
David Francis 2018-11-09 11:50:18 -05:00 committed by Alex Deucher
parent 8ccb596fc5
commit fa3547dd92
1 changed files with 13 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
View File

@ -117,6 +117,18 @@ void dce100_prepare_bandwidth(
false);
}
void dce100_optimize_bandwidth(
struct dc *dc,
struct dc_state *context)
{
dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
dc->res_pool->clk_mgr->funcs->update_clocks(
dc->res_pool->clk_mgr,
context,
true);
}
/**************************************************************************/
void dce100_hw_sequencer_construct(struct dc *dc)
@ -125,6 +137,6 @@ void dce100_hw_sequencer_construct(struct dc *dc)
dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;
dc->hwss.optimize_bandwidth = dce100_prepare_bandwidth;
dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;
}