platform/x86: intel_pmc_core: Move to intel sub-directory
Move Intel PMC core driver to intel sub-directory to improve readability. Signed-off-by: Kate Hsuan <hpa@redhat.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com> Link: https://lore.kernel.org/r/20210820110458.73018-7-andriy.shevchenko@linux.intel.com Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This commit is contained in:
Kate Hsuan
Hans de Goede
parent
386d17b22e
commit
fa082a7cf5
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@ -9483,7 +9483,7 @@ M: David E Box <david.e.box@intel.com>
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L: platform-driver-x86@vger.kernel.org
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S: Maintained
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F: Documentation/ABI/testing/sysfs-platform-intel-pmc
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F: drivers/platform/x86/intel_pmc_core*
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F: drivers/platform/x86/intel/pmc/
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INTEL PMIC GPIO DRIVERS
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M: Andy Shevchenko <andy@kernel.org>
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@ -1159,27 +1159,6 @@ config INTEL_UNCORE_FREQ_CONTROL
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To compile this driver as a module, choose M here: the module
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will be called intel-uncore-frequency.
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config INTEL_PMC_CORE
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tristate "Intel PMC Core driver"
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depends on PCI
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depends on ACPI
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help
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The Intel Platform Controller Hub for Intel Core SoCs provides access
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to Power Management Controller registers via various interfaces. This
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driver can utilize debugging capabilities and supported features as
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exposed by the Power Management Controller. It also may perform some
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tasks in the PMC in order to enable transition into the SLPS0 state.
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It should be selected on all Intel platforms supported by the driver.
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Supported features:
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- SLP_S0_RESIDENCY counter
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- PCH IP Power Gating status
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- LTR Ignore / LTR Show
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- MPHY/PLL gating status (Sunrisepoint PCH only)
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- SLPS0 Debug registers (Cannonlake/Icelake PCH)
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- Low Power Mode registers (Tigerlake and beyond)
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- PMC quirks as needed to enable SLPS0/S0ix
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config INTEL_SCU_IPC
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bool
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@ -127,7 +127,6 @@ obj-$(CONFIG_INTEL_TURBO_MAX_3) += intel_turbo_max_3.o
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obj-$(CONFIG_INTEL_UNCORE_FREQ_CONTROL) += intel-uncore-frequency.o
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# Intel PMIC / PMC / P-Unit devices
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obj-$(CONFIG_INTEL_PMC_CORE) += intel_pmc_core.o intel_pmc_core_pltdrv.o
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obj-$(CONFIG_INTEL_SCU_IPC) += intel_scu_ipc.o
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obj-$(CONFIG_INTEL_SCU_PCI) += intel_scu_pcidrv.o
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obj-$(CONFIG_INTEL_SCU_PLATFORM) += intel_scu_pltdrv.o
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@ -19,6 +19,7 @@ if X86_PLATFORM_DRIVERS_INTEL
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source "drivers/platform/x86/intel/int1092/Kconfig"
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source "drivers/platform/x86/intel/int33fe/Kconfig"
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source "drivers/platform/x86/intel/int3472/Kconfig"
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source "drivers/platform/x86/intel/pmc/Kconfig"
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source "drivers/platform/x86/intel/pmt/Kconfig"
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config INTEL_BXTWC_PMIC_TMU
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@ -7,6 +7,7 @@
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obj-$(CONFIG_INTEL_SAR_INT1092) += int1092/
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obj-$(CONFIG_INTEL_CHT_INT33FE) += int33fe/
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obj-$(CONFIG_INTEL_SKL_INT3472) += int3472/
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obj-$(CONFIG_INTEL_PMC_CORE) += pmc/
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obj-$(CONFIG_INTEL_PMT_CLASS) += pmt/
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# Intel PMIC / PMC / P-Unit drivers
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@ -0,0 +1,25 @@
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# SPDX-License-Identifier: GPL-2.0
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#
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# Intel x86 Platform-Specific Drivers
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#
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config INTEL_PMC_CORE
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tristate "Intel PMC Core driver"
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depends on PCI
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depends on ACPI
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help
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The Intel Platform Controller Hub for Intel Core SoCs provides access
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to Power Management Controller registers via various interfaces. This
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driver can utilize debugging capabilities and supported features as
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exposed by the Power Management Controller. It also may perform some
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tasks in the PMC in order to enable transition into the SLPS0 state.
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It should be selected on all Intel platforms supported by the driver.
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Supported features:
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- SLP_S0_RESIDENCY counter
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- PCH IP Power Gating status
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- LTR Ignore / LTR Show
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- MPHY/PLL gating status (Sunrisepoint PCH only)
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- SLPS0 Debug registers (Cannonlake/Icelake PCH)
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- Low Power Mode registers (Tigerlake and beyond)
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- PMC quirks as needed to enable SLPS0/S0ix
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@ -0,0 +1,9 @@
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# SPDX-License-Identifier: GPL-2.0
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#
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# Intel x86 Platform-Specific Drivers
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#
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intel_pmc_core-y := core.o
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obj-$(CONFIG_INTEL_PMC_CORE) += intel_pmc_core.o
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intel_pmc_core_pltdrv-y := pltdrv.o
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obj-$(CONFIG_INTEL_PMC_CORE) += intel_pmc_core_pltdrv.o
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@ -31,7 +31,7 @@
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#include <asm/msr.h>
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#include <asm/tsc.h>
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#include "intel_pmc_core.h"
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#include "core.h"
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#define ACPI_S0IX_DSM_UUID "57a6512e-3979-4e9d-9708-ff13b2508972"
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#define ACPI_GET_LOW_MODE_REGISTERS 1
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