drm/i915/skl: Implement WaDisableVFUnitClockGating
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -6102,6 +6102,7 @@ enum skl_disp_power_wells {
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# define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
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#define GEN6_UCGCTL2 0x9404
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# define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31)
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# define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
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# define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
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# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
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@ -75,6 +75,10 @@ static void skl_init_clock_gating(struct drm_device *dev)
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I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
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GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
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GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
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/* WaDisableVFUnitClockGating:skl */
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I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
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GEN6_VFUNIT_CLOCK_GATE_DISABLE);
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}
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if (INTEL_REVID(dev) <= SKL_REVID_D0) {
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