drm/bridge: tc358768: fix TCLK_ZEROCNT computation
Correct computation of TCLK_ZEROCNT register.
This register must be set to a value that ensure that
(TCLK-PREPARECNT + TCLK-ZERO) > 300ns
with the actual value of (TCLK-PREPARECNT + TCLK-ZERO) being
(1 to 2) + (TCLK_ZEROCNT + 1)) x HSByteClkCycle + (PHY output delay)
with PHY output delay being about
(2 to 3) x MIPIBitClk cycle in the BitClk conversion.
Fixes: ff1ca6397b
("drm/bridge: Add tc358768 driver")
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Robert Foss <rfoss@kernel.org>
Signed-off-by: Robert Foss <rfoss@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20230427142934.55435-5-francesco@dolcini.it
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@ -743,10 +743,10 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge)
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/* 38ns < TCLK_PREPARE < 95ns */
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val = tc358768_ns_to_cnt(65, dsibclk_nsk) - 1;
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/* TCLK_PREPARE > 300ns */
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val2 = tc358768_ns_to_cnt(300 + tc358768_to_ns(3 * ui_nsk),
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dsibclk_nsk);
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val |= (val2 - tc358768_to_ns(phy_delay_nsk - dsibclk_nsk)) << 8;
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/* TCLK_PREPARE + TCLK_ZERO > 300ns */
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val2 = tc358768_ns_to_cnt(300 - tc358768_to_ns(2 * ui_nsk),
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dsibclk_nsk) - 2;
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val |= val2 << 8;
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dev_dbg(priv->dev, "TCLK_HEADERCNT: 0x%x\n", val);
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tc358768_write(priv, TC358768_TCLK_HEADERCNT, val);
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