intel-pinctrl for v5.17-3
* Intel Baytrail and Cherryview IRQ related fixes The following is an automated git shortlog grouped by driver: baytrail: - Set IRQCHIP_SET_TYPE_MASKED flag on the irqchip cherryview: - Use temporary variable for struct device - Do not allow the same interrupt line to be used by 2 pins - Don't use selection 0 to mark an interrupt line as unused -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEqaflIX74DDDzMJJtb7wzTHR8rCgFAmG6DMEACgkQb7wzTHR8 rCjNaw/+MnE7sIpBZ1143N+T7qidGSLZkOW13OQOnreSIhjUVRrxFGAj5Iy6kRJA dIsZn/ALXiAlfM1iFar9vhVLznoA9uzfWRu3mfTmCfmgiv+N2XDMg+bVrwoHf5s3 FLrTuNJKL34MAXAuTgIaGWEcpAwfrYUwY0saka3fgsj70lE8/+WWG7ZxU57E3ra4 /q+2QGM/3oyqe1R2n9TJbrsWUS2aXZE3EMWzyiAmWJcsC9cbYjKBz75mpuyysBAH chikafxJ9aovhQhtus6Hbnq2IsD3G0FpOinhZRsArZoIntEgXO/GDNDvulY9qB8Z anJHRjCD8rPv8dJk9XK+ad/uqkPZct1IpbtWSnl9s1T4Gf+SJGrEd61Kyc7Pau9h 4IMINIlCTqmPKyw7qEIsbGlQfTtvhAhNT3uRbQDjKyde+HhVtYEngwcPWGyFAPNx rj39KYkekcENZ+IQzhKmLJ3/LxFwiiU3lYtOU9oa1Xulfa/BHtdaBCbUIjuenXF6 FKJkBfqHtwE3xOIH42F9ETA9zv8alVMp6kOt4JMTY7DNyKCzaHRM4KPWT9m1NaDa JF8djmjVIQzl102MQKJxjE4y3RWyHH3e/V+itFBE/142t8CR4XTJdUgkZzGqo6V3 aGvr4oyia66b4sKureuvYLnEHnHFH2lxbgyg4YuSczwEKCvyBFo= =8Crg -----END PGP SIGNATURE----- Merge tag 'intel-pinctrl-v5.17-3' of gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v5.17-3 * Intel Baytrail and Cherryview IRQ related fixes The following is an automated git shortlog grouped by driver: baytrail: - Set IRQCHIP_SET_TYPE_MASKED flag on the irqchip cherryview: - Use temporary variable for struct device - Do not allow the same interrupt line to be used by 2 pins - Don't use selection 0 to mark an interrupt line as unused
This commit is contained in:
Linus Walleij
commit
f9b94d2426
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@ -1577,7 +1577,7 @@ static int byt_gpio_probe(struct intel_pinctrl *vg)
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vg->irqchip.irq_mask = byt_irq_mask,
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vg->irqchip.irq_unmask = byt_irq_unmask,
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vg->irqchip.irq_set_type = byt_irq_type,
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vg->irqchip.flags = IRQCHIP_SKIP_SET_WAKE,
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vg->irqchip.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED,
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girq = &gc->irq;
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girq->chip = &vg->irqchip;
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@ -73,6 +73,8 @@ struct intel_pad_context {
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u32 padctrl1;
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};
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#define CHV_INVALID_HWIRQ ((unsigned int)INVALID_HWIRQ)
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/**
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* struct intel_community_context - community context for Cherryview
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* @intr_lines: Mapping between 16 HW interrupt wires and GPIO offset (in GPIO number space)
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@ -709,6 +711,7 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
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unsigned int function, unsigned int group)
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{
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struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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struct device *dev = pctrl->dev;
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const struct intel_pingroup *grp;
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unsigned long flags;
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int i;
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@ -720,9 +723,8 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
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/* Check first that the pad is not locked */
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for (i = 0; i < grp->npins; i++) {
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if (chv_pad_locked(pctrl, grp->pins[i])) {
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dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n",
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grp->pins[i]);
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raw_spin_unlock_irqrestore(&chv_lock, flags);
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dev_warn(dev, "unable to set mode for locked pin %u\n", grp->pins[i]);
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return -EBUSY;
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}
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}
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@ -757,8 +759,8 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
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value |= CHV_PADCTRL1_INVRXTX_TXENABLE;
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chv_writel(pctrl, pin, CHV_PADCTRL1, value);
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dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n",
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pin, mode, invert_oe ? "" : "not ");
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dev_dbg(dev, "configured pin %u mode %u OE %sinverted\n", pin, mode,
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invert_oe ? "" : "not ");
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}
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raw_spin_unlock_irqrestore(&chv_lock, flags);
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@ -812,7 +814,7 @@ static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
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/* Reset the interrupt mapping */
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for (i = 0; i < ARRAY_SIZE(cctx->intr_lines); i++) {
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if (cctx->intr_lines[i] == offset) {
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cctx->intr_lines[i] = 0;
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cctx->intr_lines[i] = CHV_INVALID_HWIRQ;
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break;
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}
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}
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@ -1058,6 +1060,7 @@ static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
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unsigned long *configs, unsigned int nconfigs)
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{
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struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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struct device *dev = pctrl->dev;
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enum pin_config_param param;
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int i, ret;
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u32 arg;
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@ -1094,8 +1097,7 @@ static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
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return -ENOTSUPP;
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}
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dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin,
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param, arg);
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dev_dbg(dev, "pin %d set config %d arg %u\n", pin, param, arg);
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}
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return 0;
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@ -1302,6 +1304,7 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
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if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) {
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
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struct device *dev = pctrl->dev;
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struct intel_community_context *cctx = &pctrl->context.communities[0];
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unsigned int pin = irqd_to_hwirq(d);
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irq_flow_handler_t handler;
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@ -1319,8 +1322,10 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
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else
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handler = handle_edge_irq;
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if (!cctx->intr_lines[intsel]) {
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if (cctx->intr_lines[intsel] == CHV_INVALID_HWIRQ) {
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irq_set_handler_locked(d, handler);
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dev_dbg(dev, "using interrupt line %u for IRQ_TYPE_NONE on pin %u\n",
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intsel, pin);
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cctx->intr_lines[intsel] = pin;
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}
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raw_spin_unlock_irqrestore(&chv_lock, flags);
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@ -1330,17 +1335,74 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
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return 0;
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}
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static int chv_gpio_set_intr_line(struct intel_pinctrl *pctrl, unsigned int pin)
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{
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struct device *dev = pctrl->dev;
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struct intel_community_context *cctx = &pctrl->context.communities[0];
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const struct intel_community *community = &pctrl->communities[0];
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u32 value, intsel;
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int i;
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value = chv_readl(pctrl, pin, CHV_PADCTRL0);
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intsel = (value & CHV_PADCTRL0_INTSEL_MASK) >> CHV_PADCTRL0_INTSEL_SHIFT;
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if (cctx->intr_lines[intsel] == pin)
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return 0;
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if (cctx->intr_lines[intsel] == CHV_INVALID_HWIRQ) {
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dev_dbg(dev, "using interrupt line %u for pin %u\n", intsel, pin);
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cctx->intr_lines[intsel] = pin;
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return 0;
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}
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/*
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* The interrupt line selected by the BIOS is already in use by
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* another pin, this is a known BIOS bug found on several models.
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* But this may also be caused by Linux deciding to use a pin as
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* IRQ which was not expected to be used as such by the BIOS authors,
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* so log this at info level only.
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*/
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dev_info(dev, "interrupt line %u is used by both pin %u and pin %u\n", intsel,
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cctx->intr_lines[intsel], pin);
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if (chv_pad_locked(pctrl, pin))
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return -EBUSY;
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/*
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* The BIOS fills the interrupt lines from 0 counting up, start at
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* the other end to find a free interrupt line to workaround this.
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*/
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for (i = community->nirqs - 1; i >= 0; i--) {
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if (cctx->intr_lines[i] == CHV_INVALID_HWIRQ)
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break;
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}
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if (i < 0)
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return -EBUSY;
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dev_info(dev, "changing the interrupt line for pin %u to %d\n", pin, i);
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value = (value & ~CHV_PADCTRL0_INTSEL_MASK) | (i << CHV_PADCTRL0_INTSEL_SHIFT);
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chv_writel(pctrl, pin, CHV_PADCTRL0, value);
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cctx->intr_lines[i] = pin;
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return 0;
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}
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static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
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struct intel_community_context *cctx = &pctrl->context.communities[0];
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unsigned int pin = irqd_to_hwirq(d);
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unsigned long flags;
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u32 value;
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int ret;
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raw_spin_lock_irqsave(&chv_lock, flags);
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ret = chv_gpio_set_intr_line(pctrl, pin);
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if (ret)
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goto out_unlock;
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/*
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* Pins which can be used as shared interrupt are configured in
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* BIOS. Driver trusts BIOS configurations and assigns different
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@ -1375,26 +1437,22 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
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chv_writel(pctrl, pin, CHV_PADCTRL1, value);
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}
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value = chv_readl(pctrl, pin, CHV_PADCTRL0);
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value &= CHV_PADCTRL0_INTSEL_MASK;
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value >>= CHV_PADCTRL0_INTSEL_SHIFT;
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cctx->intr_lines[value] = pin;
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if (type & IRQ_TYPE_EDGE_BOTH)
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irq_set_handler_locked(d, handle_edge_irq);
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else if (type & IRQ_TYPE_LEVEL_MASK)
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irq_set_handler_locked(d, handle_level_irq);
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out_unlock:
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raw_spin_unlock_irqrestore(&chv_lock, flags);
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return 0;
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return ret;
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}
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static void chv_gpio_irq_handler(struct irq_desc *desc)
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{
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
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struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
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struct device *dev = pctrl->dev;
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const struct intel_community *community = &pctrl->communities[0];
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struct intel_community_context *cctx = &pctrl->context.communities[0];
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struct irq_chip *chip = irq_desc_get_chip(desc);
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@ -1412,6 +1470,11 @@ static void chv_gpio_irq_handler(struct irq_desc *desc)
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unsigned int offset;
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offset = cctx->intr_lines[intr_line];
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if (offset == CHV_INVALID_HWIRQ) {
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dev_err(dev, "interrupt on unused interrupt line %u\n", intr_line);
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continue;
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}
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generic_handle_domain_irq(gc->irq.domain, offset);
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}
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@ -1512,17 +1575,16 @@ static int chv_gpio_irq_init_hw(struct gpio_chip *chip)
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static int chv_gpio_add_pin_ranges(struct gpio_chip *chip)
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{
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struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
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struct device *dev = pctrl->dev;
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const struct intel_community *community = &pctrl->communities[0];
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const struct intel_padgroup *gpp;
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int ret, i;
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for (i = 0; i < community->ngpps; i++) {
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gpp = &community->gpps[i];
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ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev),
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gpp->base, gpp->base,
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gpp->size);
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ret = gpiochip_add_pin_range(chip, dev_name(dev), gpp->base, gpp->base, gpp->size);
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if (ret) {
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dev_err(pctrl->dev, "failed to add GPIO pin range\n");
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dev_err(dev, "failed to add GPIO pin range\n");
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return ret;
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}
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}
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@ -1535,15 +1597,16 @@ static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq)
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const struct intel_community *community = &pctrl->communities[0];
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const struct intel_padgroup *gpp;
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struct gpio_chip *chip = &pctrl->chip;
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struct device *dev = pctrl->dev;
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bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
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int ret, i, irq_base;
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*chip = chv_gpio_chip;
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chip->ngpio = pctrl->soc->pins[pctrl->soc->npins - 1].number + 1;
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chip->label = dev_name(pctrl->dev);
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chip->label = dev_name(dev);
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chip->add_pin_ranges = chv_gpio_add_pin_ranges;
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chip->parent = pctrl->dev;
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chip->parent = dev;
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chip->base = -1;
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pctrl->irq = irq;
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@ -1565,17 +1628,16 @@ static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq)
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if (need_valid_mask) {
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chip->irq.init_valid_mask = chv_init_irq_valid_mask;
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} else {
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irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0,
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pctrl->soc->npins, NUMA_NO_NODE);
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irq_base = devm_irq_alloc_descs(dev, -1, 0, pctrl->soc->npins, NUMA_NO_NODE);
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if (irq_base < 0) {
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dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n");
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dev_err(dev, "Failed to allocate IRQ numbers\n");
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return irq_base;
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}
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}
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ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
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ret = devm_gpiochip_add_data(dev, chip, pctrl);
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if (ret) {
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dev_err(pctrl->dev, "Failed to register gpiochip\n");
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dev_err(dev, "Failed to register gpiochip\n");
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return ret;
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}
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@ -1617,11 +1679,13 @@ static acpi_status chv_pinctrl_mmio_access_handler(u32 function,
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static int chv_pinctrl_probe(struct platform_device *pdev)
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{
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const struct intel_pinctrl_soc_data *soc_data;
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struct intel_community_context *cctx;
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struct intel_community *community;
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struct device *dev = &pdev->dev;
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struct acpi_device *adev = ACPI_COMPANION(dev);
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struct intel_pinctrl *pctrl;
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acpi_status status;
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unsigned int i;
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int ret, irq;
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soc_data = intel_pinctrl_get_soc_data(pdev);
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@ -1663,6 +1727,10 @@ static int chv_pinctrl_probe(struct platform_device *pdev)
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if (!pctrl->context.communities)
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return -ENOMEM;
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cctx = &pctrl->context.communities[0];
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for (i = 0; i < ARRAY_SIZE(cctx->intr_lines); i++)
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cctx->intr_lines[i] = CHV_INVALID_HWIRQ;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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@ -1767,15 +1835,15 @@ static int chv_pinctrl_resume_noirq(struct device *dev)
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val &= ~CHV_PADCTRL0_GPIORXSTATE;
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if (ctx->padctrl0 != val) {
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chv_writel(pctrl, desc->number, CHV_PADCTRL0, ctx->padctrl0);
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dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n",
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desc->number, chv_readl(pctrl, desc->number, CHV_PADCTRL0));
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dev_dbg(dev, "restored pin %2u ctrl0 0x%08x\n", desc->number,
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chv_readl(pctrl, desc->number, CHV_PADCTRL0));
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}
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val = chv_readl(pctrl, desc->number, CHV_PADCTRL1);
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if (ctx->padctrl1 != val) {
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chv_writel(pctrl, desc->number, CHV_PADCTRL1, ctx->padctrl1);
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dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n",
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desc->number, chv_readl(pctrl, desc->number, CHV_PADCTRL1));
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dev_dbg(dev, "restored pin %2u ctrl1 0x%08x\n", desc->number,
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chv_readl(pctrl, desc->number, CHV_PADCTRL1));
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}
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}
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Loading…
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