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Merge branch 'alx_stats' 

Sabrina Dubroca says:

====================
alx: add statistics

Currently, the alx driver doesn't support statistics [1,2]. The
original alx driver [3] that Johannes Berg modified provided
statistics. This patch is an adaptation of the statistics code from
the original driver to the alx driver included in the kernel.

v4:
 - modified the assignements of hw stats to netstats (Ben Hutchings)
 - added comments to describe the stats fields (copied from atlx)

v3:
 - renamed __alx_update_hw_stats to alx_update_hw_stats (Stephen Hemminger)

v2:
 - use u64 instead of unsigned long  (Ben Hutchings)
 - implement ndo_get_stats64 instead of ndo_get_stats (Ben Hutchings)
 - use EINVAL instead of ENOTSUPP  (Ben Hutchings)
 - add BUILD_BUG_ON to check the size of the stats (Johannes Berg, Ben
   Hutchings)
 - add a comment regarding persistence of the stats (Stephen Hemminger)
 - align assignments in __alx_update_hw_stats

[1] https://bugzilla.kernel.org/show_bug.cgi?id=63401
[2] http://www.spinics.net/lists/netdev/msg245544.html
[3] https://github.com/mcgrof/alx
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2014-01-11 20:53:03 -08:00
parent 6d71f1644f b7e6ce18cb
commit f9577a376e
6 changed files with 335 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/net/ethernet/atheros/alx/alx.h
View File

@ -106,6 +106,9 @@ struct alx_priv {
u16 msg_enable; u16 msg_enable;
bool msi; bool msi;
/* protects hw.stats */
spinlock_t stats_lock;
}; };
extern const struct ethtool_ops alx_ethtool_ops; extern const struct ethtool_ops alx_ethtool_ops;

101
drivers/net/ethernet/atheros/alx/ethtool.c
View File

@ -46,6 +46,66 @@
#include "reg.h" #include "reg.h"
#include "hw.h" #include "hw.h"
/* The order of these strings must match the order of the fields in
* struct alx_hw_stats
* See hw.h
*/
static const char alx_gstrings_stats[][ETH_GSTRING_LEN] = {
"rx_packets",
"rx_bcast_packets",
"rx_mcast_packets",
"rx_pause_packets",
"rx_ctrl_packets",
"rx_fcs_errors",
"rx_length_errors",
"rx_bytes",
"rx_runt_packets",
"rx_fragments",
"rx_64B_or_less_packets",
"rx_65B_to_127B_packets",
"rx_128B_to_255B_packets",
"rx_256B_to_511B_packets",
"rx_512B_to_1023B_packets",
"rx_1024B_to_1518B_packets",
"rx_1519B_to_mtu_packets",
"rx_oversize_packets",
"rx_rxf_ov_drop_packets",
"rx_rrd_ov_drop_packets",
"rx_align_errors",
"rx_bcast_bytes",
"rx_mcast_bytes",
"rx_address_errors",
"tx_packets",
"tx_bcast_packets",
"tx_mcast_packets",
"tx_pause_packets",
"tx_exc_defer_packets",
"tx_ctrl_packets",
"tx_defer_packets",
"tx_bytes",
"tx_64B_or_less_packets",
"tx_65B_to_127B_packets",
"tx_128B_to_255B_packets",
"tx_256B_to_511B_packets",
"tx_512B_to_1023B_packets",
"tx_1024B_to_1518B_packets",
"tx_1519B_to_mtu_packets",
"tx_single_collision",
"tx_multiple_collisions",
"tx_late_collision",
"tx_abort_collision",
"tx_underrun",
"tx_trd_eop",
"tx_length_errors",
"tx_trunc_packets",
"tx_bcast_bytes",
"tx_mcast_bytes",
"tx_update",
};
#define ALX_NUM_STATS ARRAY_SIZE(alx_gstrings_stats)
static u32 alx_get_supported_speeds(struct alx_hw *hw) static u32 alx_get_supported_speeds(struct alx_hw *hw)
{ {
u32 supported = SUPPORTED_10baseT_Half | u32 supported = SUPPORTED_10baseT_Half |
@ -201,6 +261,44 @@ static void alx_set_msglevel(struct net_device *netdev, u32 data)
alx->msg_enable = data; alx->msg_enable = data;
} }
static void alx_get_ethtool_stats(struct net_device *netdev,
struct ethtool_stats *estats, u64 *data)
{
struct alx_priv *alx = netdev_priv(netdev);
struct alx_hw *hw = &alx->hw;
spin_lock(&alx->stats_lock);
alx_update_hw_stats(hw);
BUILD_BUG_ON(sizeof(hw->stats) - offsetof(struct alx_hw_stats, rx_ok) <
ALX_NUM_STATS * sizeof(u64));
memcpy(data, &hw->stats.rx_ok, ALX_NUM_STATS * sizeof(u64));
spin_unlock(&alx->stats_lock);
}
static void alx_get_strings(struct net_device *netdev, u32 stringset, u8 *buf)
{
switch (stringset) {
case ETH_SS_STATS:
memcpy(buf, &alx_gstrings_stats, sizeof(alx_gstrings_stats));
break;
default:
WARN_ON(1);
break;
}
}
static int alx_get_sset_count(struct net_device *netdev, int sset)
{
switch (sset) {
case ETH_SS_STATS:
return ALX_NUM_STATS;
default:
return -EINVAL;
}
}
const struct ethtool_ops alx_ethtool_ops = { const struct ethtool_ops alx_ethtool_ops = {
.get_settings = alx_get_settings, .get_settings = alx_get_settings,
.set_settings = alx_set_settings, .set_settings = alx_set_settings,
@ -209,4 +307,7 @@ const struct ethtool_ops alx_ethtool_ops = {
.get_msglevel = alx_get_msglevel, .get_msglevel = alx_get_msglevel,
.set_msglevel = alx_set_msglevel, .set_msglevel = alx_set_msglevel,
.get_link = ethtool_op_get_link, .get_link = ethtool_op_get_link,
.get_strings = alx_get_strings,
.get_sset_count = alx_get_sset_count,
.get_ethtool_stats = alx_get_ethtool_stats,
}; };

58
drivers/net/ethernet/atheros/alx/hw.c
View File

@ -1050,3 +1050,61 @@ bool alx_get_phy_info(struct alx_hw *hw)
return true; return true;
} }
void alx_update_hw_stats(struct alx_hw *hw)
{
/* RX stats */
hw->stats.rx_ok += alx_read_mem32(hw, ALX_MIB_RX_OK);
hw->stats.rx_bcast += alx_read_mem32(hw, ALX_MIB_RX_BCAST);
hw->stats.rx_mcast += alx_read_mem32(hw, ALX_MIB_RX_MCAST);
hw->stats.rx_pause += alx_read_mem32(hw, ALX_MIB_RX_PAUSE);
hw->stats.rx_ctrl += alx_read_mem32(hw, ALX_MIB_RX_CTRL);
hw->stats.rx_fcs_err += alx_read_mem32(hw, ALX_MIB_RX_FCS_ERR);
hw->stats.rx_len_err += alx_read_mem32(hw, ALX_MIB_RX_LEN_ERR);
hw->stats.rx_byte_cnt += alx_read_mem32(hw, ALX_MIB_RX_BYTE_CNT);
hw->stats.rx_runt += alx_read_mem32(hw, ALX_MIB_RX_RUNT);
hw->stats.rx_frag += alx_read_mem32(hw, ALX_MIB_RX_FRAG);
hw->stats.rx_sz_64B += alx_read_mem32(hw, ALX_MIB_RX_SZ_64B);
hw->stats.rx_sz_127B += alx_read_mem32(hw, ALX_MIB_RX_SZ_127B);
hw->stats.rx_sz_255B += alx_read_mem32(hw, ALX_MIB_RX_SZ_255B);
hw->stats.rx_sz_511B += alx_read_mem32(hw, ALX_MIB_RX_SZ_511B);
hw->stats.rx_sz_1023B += alx_read_mem32(hw, ALX_MIB_RX_SZ_1023B);
hw->stats.rx_sz_1518B += alx_read_mem32(hw, ALX_MIB_RX_SZ_1518B);
hw->stats.rx_sz_max += alx_read_mem32(hw, ALX_MIB_RX_SZ_MAX);
hw->stats.rx_ov_sz += alx_read_mem32(hw, ALX_MIB_RX_OV_SZ);
hw->stats.rx_ov_rxf += alx_read_mem32(hw, ALX_MIB_RX_OV_RXF);
hw->stats.rx_ov_rrd += alx_read_mem32(hw, ALX_MIB_RX_OV_RRD);
hw->stats.rx_align_err += alx_read_mem32(hw, ALX_MIB_RX_ALIGN_ERR);
hw->stats.rx_bc_byte_cnt += alx_read_mem32(hw, ALX_MIB_RX_BCCNT);
hw->stats.rx_mc_byte_cnt += alx_read_mem32(hw, ALX_MIB_RX_MCCNT);
hw->stats.rx_err_addr += alx_read_mem32(hw, ALX_MIB_RX_ERRADDR);
/* TX stats */
hw->stats.tx_ok += alx_read_mem32(hw, ALX_MIB_TX_OK);
hw->stats.tx_bcast += alx_read_mem32(hw, ALX_MIB_TX_BCAST);
hw->stats.tx_mcast += alx_read_mem32(hw, ALX_MIB_TX_MCAST);
hw->stats.tx_pause += alx_read_mem32(hw, ALX_MIB_TX_PAUSE);
hw->stats.tx_exc_defer += alx_read_mem32(hw, ALX_MIB_TX_EXC_DEFER);
hw->stats.tx_ctrl += alx_read_mem32(hw, ALX_MIB_TX_CTRL);
hw->stats.tx_defer += alx_read_mem32(hw, ALX_MIB_TX_DEFER);
hw->stats.tx_byte_cnt += alx_read_mem32(hw, ALX_MIB_TX_BYTE_CNT);
hw->stats.tx_sz_64B += alx_read_mem32(hw, ALX_MIB_TX_SZ_64B);
hw->stats.tx_sz_127B += alx_read_mem32(hw, ALX_MIB_TX_SZ_127B);
hw->stats.tx_sz_255B += alx_read_mem32(hw, ALX_MIB_TX_SZ_255B);
hw->stats.tx_sz_511B += alx_read_mem32(hw, ALX_MIB_TX_SZ_511B);
hw->stats.tx_sz_1023B += alx_read_mem32(hw, ALX_MIB_TX_SZ_1023B);
hw->stats.tx_sz_1518B += alx_read_mem32(hw, ALX_MIB_TX_SZ_1518B);
hw->stats.tx_sz_max += alx_read_mem32(hw, ALX_MIB_TX_SZ_MAX);
hw->stats.tx_single_col += alx_read_mem32(hw, ALX_MIB_TX_SINGLE_COL);
hw->stats.tx_multi_col += alx_read_mem32(hw, ALX_MIB_TX_MULTI_COL);
hw->stats.tx_late_col += alx_read_mem32(hw, ALX_MIB_TX_LATE_COL);
hw->stats.tx_abort_col += alx_read_mem32(hw, ALX_MIB_TX_ABORT_COL);
hw->stats.tx_underrun += alx_read_mem32(hw, ALX_MIB_TX_UNDERRUN);
hw->stats.tx_trd_eop += alx_read_mem32(hw, ALX_MIB_TX_TRD_EOP);
hw->stats.tx_len_err += alx_read_mem32(hw, ALX_MIB_TX_LEN_ERR);
hw->stats.tx_trunc += alx_read_mem32(hw, ALX_MIB_TX_TRUNC);
hw->stats.tx_bc_byte_cnt += alx_read_mem32(hw, ALX_MIB_TX_BCCNT);
hw->stats.tx_mc_byte_cnt += alx_read_mem32(hw, ALX_MIB_TX_MCCNT);
hw->stats.update += alx_read_mem32(hw, ALX_MIB_UPDATE);
}

71
drivers/net/ethernet/atheros/alx/hw.h
View File

@ -381,6 +381,73 @@ struct alx_rrd {
ALX_ISR_RX_Q6 | \ ALX_ISR_RX_Q6 | \
ALX_ISR_RX_Q7) ALX_ISR_RX_Q7)
/* Statistics counters collected by the MAC
*
* The order of the fields must match the strings in alx_gstrings_stats
* All stats fields should be u64
* See ethtool.c
*/
struct alx_hw_stats {
/* rx */
u64 rx_ok; /* good RX packets */
u64 rx_bcast; /* good RX broadcast packets */
u64 rx_mcast; /* good RX multicast packets */
u64 rx_pause; /* RX pause frames */
u64 rx_ctrl; /* RX control packets other than pause frames */
u64 rx_fcs_err; /* RX packets with bad FCS */
u64 rx_len_err; /* RX packets with length != actual size */
u64 rx_byte_cnt; /* good bytes received. FCS is NOT included */
u64 rx_runt; /* RX packets < 64 bytes with good FCS */
u64 rx_frag; /* RX packets < 64 bytes with bad FCS */
u64 rx_sz_64B; /* 64 byte RX packets */
u64 rx_sz_127B; /* 65-127 byte RX packets */
u64 rx_sz_255B; /* 128-255 byte RX packets */
u64 rx_sz_511B; /* 256-511 byte RX packets */
u64 rx_sz_1023B; /* 512-1023 byte RX packets */
u64 rx_sz_1518B; /* 1024-1518 byte RX packets */
u64 rx_sz_max; /* 1519 byte to MTU RX packets */
u64 rx_ov_sz; /* truncated RX packets, size > MTU */
u64 rx_ov_rxf; /* frames dropped due to RX FIFO overflow */
u64 rx_ov_rrd; /* frames dropped due to RRD overflow */
u64 rx_align_err; /* alignment errors */
u64 rx_bc_byte_cnt; /* RX broadcast bytes, excluding FCS */
u64 rx_mc_byte_cnt; /* RX multicast bytes, excluding FCS */
u64 rx_err_addr; /* packets dropped due to address filtering */
/* tx */
u64 tx_ok; /* good TX packets */
u64 tx_bcast; /* good TX broadcast packets */
u64 tx_mcast; /* good TX multicast packets */
u64 tx_pause; /* TX pause frames */
u64 tx_exc_defer; /* TX packets deferred excessively */
u64 tx_ctrl; /* TX control frames, excluding pause frames */
u64 tx_defer; /* TX packets deferred */
u64 tx_byte_cnt; /* bytes transmitted, FCS is NOT included */
u64 tx_sz_64B; /* 64 byte TX packets */
u64 tx_sz_127B; /* 65-127 byte TX packets */
u64 tx_sz_255B; /* 128-255 byte TX packets */
u64 tx_sz_511B; /* 256-511 byte TX packets */
u64 tx_sz_1023B; /* 512-1023 byte TX packets */
u64 tx_sz_1518B; /* 1024-1518 byte TX packets */
u64 tx_sz_max; /* 1519 byte to MTU TX packets */
u64 tx_single_col; /* packets TX after a single collision */
u64 tx_multi_col; /* packets TX after multiple collisions */
u64 tx_late_col; /* TX packets with late collisions */
u64 tx_abort_col; /* TX packets aborted w/excessive collisions */
u64 tx_underrun; /* TX packets aborted due to TX FIFO underrun
* or TRD FIFO underrun
*/
u64 tx_trd_eop; /* reads beyond the EOP into the next frame
* when TRD was not written timely
*/
u64 tx_len_err; /* TX packets where length != actual size */
u64 tx_trunc; /* TX packets truncated due to size > MTU */
u64 tx_bc_byte_cnt; /* broadcast bytes transmitted, excluding FCS */
u64 tx_mc_byte_cnt; /* multicast bytes transmitted, excluding FCS */
u64 update;
};
/* maximum interrupt vectors for msix */ /* maximum interrupt vectors for msix */
#define ALX_MAX_MSIX_INTRS 16 #define ALX_MAX_MSIX_INTRS 16
@ -424,6 +491,9 @@ struct alx_hw {
/* PHY link patch flag */ /* PHY link patch flag */
bool lnk_patch; bool lnk_patch;
/* cumulated stats from the hardware (registers are cleared on read) */
struct alx_hw_stats stats;
}; };
static inline int alx_hw_revision(struct alx_hw *hw) static inline int alx_hw_revision(struct alx_hw *hw)
@ -491,6 +561,7 @@ bool alx_phy_configured(struct alx_hw *hw);
void alx_configure_basic(struct alx_hw *hw); void alx_configure_basic(struct alx_hw *hw);
void alx_disable_rss(struct alx_hw *hw); void alx_disable_rss(struct alx_hw *hw);
bool alx_get_phy_info(struct alx_hw *hw); bool alx_get_phy_info(struct alx_hw *hw);
void alx_update_hw_stats(struct alx_hw *hw);
static inline u32 alx_speed_to_ethadv(int speed, u8 duplex) static inline u32 alx_speed_to_ethadv(int speed, u8 duplex)
{ {

50
drivers/net/ethernet/atheros/alx/main.c
View File

@ -1166,10 +1166,60 @@ static void alx_poll_controller(struct net_device *netdev)
} }
#endif #endif
static struct rtnl_link_stats64 *alx_get_stats64(struct net_device *dev,
struct rtnl_link_stats64 *net_stats)
{
struct alx_priv *alx = netdev_priv(dev);
struct alx_hw_stats *hw_stats = &alx->hw.stats;
spin_lock(&alx->stats_lock);
alx_update_hw_stats(&alx->hw);
net_stats->tx_bytes = hw_stats->tx_byte_cnt;
net_stats->rx_bytes = hw_stats->rx_byte_cnt;
net_stats->multicast = hw_stats->rx_mcast;
net_stats->collisions = hw_stats->tx_single_col +
hw_stats->tx_multi_col +
hw_stats->tx_late_col +
hw_stats->tx_abort_col;
net_stats->rx_errors = hw_stats->rx_frag +
hw_stats->rx_fcs_err +
hw_stats->rx_len_err +
hw_stats->rx_ov_sz +
hw_stats->rx_ov_rrd +
hw_stats->rx_align_err +
hw_stats->rx_ov_rxf;
net_stats->rx_fifo_errors = hw_stats->rx_ov_rxf;
net_stats->rx_length_errors = hw_stats->rx_len_err;
net_stats->rx_crc_errors = hw_stats->rx_fcs_err;
net_stats->rx_frame_errors = hw_stats->rx_align_err;
net_stats->rx_dropped = hw_stats->rx_ov_rrd;
net_stats->tx_errors = hw_stats->tx_late_col +
hw_stats->tx_abort_col +
hw_stats->tx_underrun +
hw_stats->tx_trunc;
net_stats->tx_aborted_errors = hw_stats->tx_abort_col;
net_stats->tx_fifo_errors = hw_stats->tx_underrun;
net_stats->tx_window_errors = hw_stats->tx_late_col;
net_stats->tx_packets = hw_stats->tx_ok + net_stats->tx_errors;
net_stats->rx_packets = hw_stats->rx_ok + net_stats->rx_errors;
spin_unlock(&alx->stats_lock);
return net_stats;
}
static const struct net_device_ops alx_netdev_ops = { static const struct net_device_ops alx_netdev_ops = {
.ndo_open = alx_open, .ndo_open = alx_open,
.ndo_stop = alx_stop, .ndo_stop = alx_stop,
.ndo_start_xmit = alx_start_xmit, .ndo_start_xmit = alx_start_xmit,
.ndo_get_stats64 = alx_get_stats64,
.ndo_set_rx_mode = alx_set_rx_mode, .ndo_set_rx_mode = alx_set_rx_mode,
.ndo_validate_addr = eth_validate_addr, .ndo_validate_addr = eth_validate_addr,
.ndo_set_mac_address = alx_set_mac_address, .ndo_set_mac_address = alx_set_mac_address,

60
drivers/net/ethernet/atheros/alx/reg.h
View File

@ -404,15 +404,59 @@
/* MIB */ /* MIB */
#define ALX_MIB_BASE 0x1700 #define ALX_MIB_BASE 0x1700
#define ALX_MIB_RX_OK (ALX_MIB_BASE + 0)
#define ALX_MIB_RX_ERRADDR (ALX_MIB_BASE + 92)
#define ALX_MIB_TX_OK (ALX_MIB_BASE + 96)
#define ALX_MIB_TX_MCCNT (ALX_MIB_BASE + 192)
#define ALX_RX_STATS_BIN ALX_MIB_RX_OK #define ALX_MIB_RX_OK (ALX_MIB_BASE + 0)
#define ALX_RX_STATS_END ALX_MIB_RX_ERRADDR #define ALX_MIB_RX_BCAST (ALX_MIB_BASE + 4)
#define ALX_TX_STATS_BIN ALX_MIB_TX_OK #define ALX_MIB_RX_MCAST (ALX_MIB_BASE + 8)
#define ALX_TX_STATS_END ALX_MIB_TX_MCCNT #define ALX_MIB_RX_PAUSE (ALX_MIB_BASE + 12)
#define ALX_MIB_RX_CTRL (ALX_MIB_BASE + 16)
#define ALX_MIB_RX_FCS_ERR (ALX_MIB_BASE + 20)
#define ALX_MIB_RX_LEN_ERR (ALX_MIB_BASE + 24)
#define ALX_MIB_RX_BYTE_CNT (ALX_MIB_BASE + 28)
#define ALX_MIB_RX_RUNT (ALX_MIB_BASE + 32)
#define ALX_MIB_RX_FRAG (ALX_MIB_BASE + 36)
#define ALX_MIB_RX_SZ_64B (ALX_MIB_BASE + 40)
#define ALX_MIB_RX_SZ_127B (ALX_MIB_BASE + 44)
#define ALX_MIB_RX_SZ_255B (ALX_MIB_BASE + 48)
#define ALX_MIB_RX_SZ_511B (ALX_MIB_BASE + 52)
#define ALX_MIB_RX_SZ_1023B (ALX_MIB_BASE + 56)
#define ALX_MIB_RX_SZ_1518B (ALX_MIB_BASE + 60)
#define ALX_MIB_RX_SZ_MAX (ALX_MIB_BASE + 64)
#define ALX_MIB_RX_OV_SZ (ALX_MIB_BASE + 68)
#define ALX_MIB_RX_OV_RXF (ALX_MIB_BASE + 72)
#define ALX_MIB_RX_OV_RRD (ALX_MIB_BASE + 76)
#define ALX_MIB_RX_ALIGN_ERR (ALX_MIB_BASE + 80)
#define ALX_MIB_RX_BCCNT (ALX_MIB_BASE + 84)
#define ALX_MIB_RX_MCCNT (ALX_MIB_BASE + 88)
#define ALX_MIB_RX_ERRADDR (ALX_MIB_BASE + 92)
#define ALX_MIB_TX_OK (ALX_MIB_BASE + 96)
#define ALX_MIB_TX_BCAST (ALX_MIB_BASE + 100)
#define ALX_MIB_TX_MCAST (ALX_MIB_BASE + 104)
#define ALX_MIB_TX_PAUSE (ALX_MIB_BASE + 108)
#define ALX_MIB_TX_EXC_DEFER (ALX_MIB_BASE + 112)
#define ALX_MIB_TX_CTRL (ALX_MIB_BASE + 116)
#define ALX_MIB_TX_DEFER (ALX_MIB_BASE + 120)
#define ALX_MIB_TX_BYTE_CNT (ALX_MIB_BASE + 124)
#define ALX_MIB_TX_SZ_64B (ALX_MIB_BASE + 128)
#define ALX_MIB_TX_SZ_127B (ALX_MIB_BASE + 132)
#define ALX_MIB_TX_SZ_255B (ALX_MIB_BASE + 136)
#define ALX_MIB_TX_SZ_511B (ALX_MIB_BASE + 140)
#define ALX_MIB_TX_SZ_1023B (ALX_MIB_BASE + 144)
#define ALX_MIB_TX_SZ_1518B (ALX_MIB_BASE + 148)
#define ALX_MIB_TX_SZ_MAX (ALX_MIB_BASE + 152)
#define ALX_MIB_TX_SINGLE_COL (ALX_MIB_BASE + 156)
#define ALX_MIB_TX_MULTI_COL (ALX_MIB_BASE + 160)
#define ALX_MIB_TX_LATE_COL (ALX_MIB_BASE + 164)
#define ALX_MIB_TX_ABORT_COL (ALX_MIB_BASE + 168)
#define ALX_MIB_TX_UNDERRUN (ALX_MIB_BASE + 172)
#define ALX_MIB_TX_TRD_EOP (ALX_MIB_BASE + 176)
#define ALX_MIB_TX_LEN_ERR (ALX_MIB_BASE + 180)
#define ALX_MIB_TX_TRUNC (ALX_MIB_BASE + 184)
#define ALX_MIB_TX_BCCNT (ALX_MIB_BASE + 188)
#define ALX_MIB_TX_MCCNT (ALX_MIB_BASE + 192)
#define ALX_MIB_UPDATE (ALX_MIB_BASE + 196)
#define ALX_ISR 0x1600 #define ALX_ISR 0x1600
#define ALX_ISR_DIS BIT(31) #define ALX_ISR_DIS BIT(31)