Merge remote-tracking branch 'asoc/topic/rt5645' into asoc-next
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commit
f950aa96d1
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@ -21,6 +21,8 @@ struct rt5645_platform_data {
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/* 0 = IN2P; 1 = GPIO6; 2 = GPIO10; 3 = GPIO12 */
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unsigned int jd_mode;
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/* Invert JD when jack insert */
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bool jd_invert;
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};
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#endif
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@ -2829,6 +2829,9 @@ static int rt5645_jack_detect(struct snd_soc_codec *codec, int jack_insert)
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snd_soc_dapm_sync(dapm);
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rt5645->jack_type = SND_JACK_HEADPHONE;
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}
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if (rt5645->pdata.jd_invert)
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regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
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RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);
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} else { /* jack out */
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rt5645->jack_type = 0;
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@ -2847,6 +2850,9 @@ static int rt5645_jack_detect(struct snd_soc_codec *codec, int jack_insert)
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snd_soc_dapm_disable_pin(dapm, "LDO2");
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snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
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snd_soc_dapm_sync(dapm);
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if (rt5645->pdata.jd_invert)
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regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
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RT5645_JD_1_1_MASK, RT5645_JD_1_1_NOR);
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}
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return rt5645->jack_type;
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@ -3212,6 +3218,32 @@ static const struct dmi_system_id dmi_platform_intel_braswell[] = {
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{ }
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};
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static struct rt5645_platform_data buddy_platform_data = {
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.dmic1_data_pin = RT5645_DMIC_DATA_GPIO5,
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.dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
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.jd_mode = 3,
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.jd_invert = true,
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};
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static int buddy_quirk_cb(const struct dmi_system_id *id)
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{
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rt5645_pdata = &buddy_platform_data;
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return 1;
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}
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static struct dmi_system_id dmi_platform_intel_broadwell[] __initdata = {
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{
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.ident = "Chrome Buddy",
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.callback = buddy_quirk_cb,
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.matches = {
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DMI_MATCH(DMI_PRODUCT_NAME, "Buddy"),
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},
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},
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{ }
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};
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static int rt5645_parse_dt(struct rt5645_priv *rt5645, struct device *dev)
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{
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rt5645->pdata.in2_diff = device_property_read_bool(dev,
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@ -3244,7 +3276,8 @@ static int rt5645_i2c_probe(struct i2c_client *i2c,
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if (pdata)
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rt5645->pdata = *pdata;
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else if (dmi_check_system(dmi_platform_intel_braswell))
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else if (dmi_check_system(dmi_platform_intel_braswell) ||
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dmi_check_system(dmi_platform_intel_broadwell))
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rt5645->pdata = *rt5645_pdata;
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else
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rt5645_parse_dt(rt5645, &i2c->dev);
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@ -777,8 +777,6 @@
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#define RT5645_PWR_CLS_D_R_BIT 9
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#define RT5645_PWR_CLS_D_L (0x1 << 8)
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#define RT5645_PWR_CLS_D_L_BIT 8
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#define RT5645_PWR_ADC_R (0x1 << 1)
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#define RT5645_PWR_ADC_R_BIT 1
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#define RT5645_PWR_DAC_L2 (0x1 << 7)
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#define RT5645_PWR_DAC_L2_BIT 7
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#define RT5645_PWR_DAC_R2 (0x1 << 6)
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@ -1626,6 +1624,10 @@
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#define RT5645_OT_P_NOR (0x0 << 10)
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#define RT5645_OT_P_INV (0x1 << 10)
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#define RT5645_IRQ_JD_1_1_EN (0x1 << 9)
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#define RT5645_JD_1_1_MASK (0x1 << 7)
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#define RT5645_JD_1_1_SFT 7
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#define RT5645_JD_1_1_NOR (0x0 << 7)
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#define RT5645_JD_1_1_INV (0x1 << 7)
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/* IRQ Control 2 (0xbe) */
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#define RT5645_IRQ_MB1_OC_MASK (0x1 << 15)
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