drm/amd/display: Force ODM combine on 5K+ 420 modes
[Why] All YCbCr420 resolutions 5K and above have tiling and discoloration issues. The issue can be remedied by forcing ODM combine from 5K to 8K. 10K resolution requires ODM 4:1. The mechanism of what the real problem is, that is inherent in ODM combine programming, doesn't seem to be pointed at singular register programming (CLK, MPC, DCSURF, etc.), and needs more in-depth programming sequence review for these new use case scenarios. Until then, workaround to enable ODM combine is proposed. While it is not our policy, HW spreadsheet also recommends turning on ODM for these scenario to lower the voltage. [How] Make pixel encoding and resolution size specific workaround to enable ODM combine on YCbCr420 high resolution modes. Signed-off-by: Chris Park <Chris.Park@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -3986,9 +3986,19 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
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} else if (v->PlaneRequiredDISPCLKWithoutODMCombine > v->MaxDispclkRoundedDownToDFSGranularity) {
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v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
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v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
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/*420 format workaround*/
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if (v->HActive[k] > 7680 && v->OutputFormat[k] == dm_420) {
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v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
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v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
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}
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} else {
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v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
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v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithoutODMCombine;
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/*420 format workaround*/
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if (v->HActive[k] > 4096 && v->OutputFormat[k] == dm_420) {
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v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
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v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
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}
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}
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if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
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