ARM: dts: at91: sama7g5: Add crypto nodes
Describe and enable the AES, SHA and TDES crypto IPs. Tested with the extra run-time self tests of the registered crypto algorithms. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220208105646.226623-1-tudor.ambarus@microchip.com
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@ -337,6 +337,27 @@
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clock-names = "pclk", "gclk";
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};
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aes: crypto@e1810000 {
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compatible = "atmel,at91sam9g46-aes";
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reg = <0xe1810000 0x100>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
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clock-names = "aes_clk";
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dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>,
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<&dma0 AT91_XDMAC_DT_PERID(2)>;
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dma-names = "tx", "rx";
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};
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sha: crypto@e1814000 {
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compatible = "atmel,at91sam9g46-sha";
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reg = <0xe1814000 0x100>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 83>;
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clock-names = "sha_clk";
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dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>;
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dma-names = "tx";
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};
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flx0: flexcom@e1818000 {
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compatible = "atmel,sama5d2-flexcom";
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reg = <0xe1818000 0x200>;
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@ -419,6 +440,17 @@
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status = "disabled";
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};
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tdes: crypto@e2014000 {
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compatible = "atmel,at91sam9g46-tdes";
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reg = <0xe2014000 0x100>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 96>;
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clock-names = "tdes_clk";
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dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>,
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<&dma0 AT91_XDMAC_DT_PERID(53)>;
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dma-names = "tx", "rx";
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};
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flx4: flexcom@e2018000 {
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compatible = "atmel,sama5d2-flexcom";
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reg = <0xe2018000 0x200>;
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