UbiquitousOS
/
OpenCloudOS-Kernel
mirror of https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel.git
11
0
Fork 0
Code Issues Projects Releases Wiki Activity

mmc: meson-gx: rework clk_set function 

Clean-up clk_set function to prepare the next changes (DDR and clk-stop)

Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Jerome Brunet 2017-08-28 16:29:06 +02:00 committed by Ulf Hansson
parent c36cf1257b
commit f89f55df59
1 changed files with 9 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
drivers/mmc/host/meson-gx-mmc.c
View File

@ -139,7 +139,7 @@ struct meson_host {
struct clk *core_clk;
struct clk_mux mux;
struct clk *mux_clk;
unsigned long current_clock;
unsigned long req_rate;
struct clk_divider cfg_div;
struct clk *cfg_div_clk;
@ -275,29 +275,18 @@ static int meson_mmc_clk_set(struct meson_host *host, unsigned long clk_rate)
int ret;
u32 cfg;
if (clk_rate) {
if (WARN_ON(clk_rate > mmc->f_max))
clk_rate = mmc->f_max;
else if (WARN_ON(clk_rate < mmc->f_min))
clk_rate = mmc->f_min;
}
if (clk_rate == host->current_clock)
/* Same request - bail-out */
if (host->req_rate == clk_rate)
return 0;
/* stop clock */
cfg = readl(host->regs + SD_EMMC_CFG);
if (!(cfg & CFG_STOP_CLOCK)) {
cfg |= CFG_STOP_CLOCK;
writel(cfg, host->regs + SD_EMMC_CFG);
}
dev_dbg(host->dev, "change clock rate %u -> %lu\n",
mmc->actual_clock, clk_rate);
cfg |= CFG_STOP_CLOCK;
writel(cfg, host->regs + SD_EMMC_CFG);
host->req_rate = 0;
if (!clk_rate) {
mmc->actual_clock = 0;
host->current_clock = 0;
/* return with clock being stopped */
return 0;
}
@ -309,13 +298,12 @@ static int meson_mmc_clk_set(struct meson_host *host, unsigned long clk_rate)
return ret;
}
host->req_rate = clk_rate;
mmc->actual_clock = clk_get_rate(host->cfg_div_clk);
host->current_clock = clk_rate;
dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock);
if (clk_rate != mmc->actual_clock)
dev_dbg(host->dev,
"divider requested rate %lu != actual rate %u\n",
clk_rate, mmc->actual_clock);
dev_dbg(host->dev, "requested rate was %lu\n", clk_rate);
/* (re)start clock */
cfg = readl(host->regs + SD_EMMC_CFG);