x86/pmc_atom: Expose PMC device state and platform sleep state
Add the following interfaces to exposes PMC device state and sleep state residency via debugfs: /sys/kernel/debugfs/pmc_atom/dev_state /sys/kernel/debugfs/pmc_atom/sleep_state Signed-off-by: Aubrey Li <aubrey.li@linux.intel.com> Link: http://lkml.kernel.org/r/53B0FF59.8000600@linux.intel.com Signed-off-by: Kasagar, Srinidhi <srinidhi.kasagar@intel.com> Reviewed-by: Rudramuni, Vishwesh M <vishwesh.m.rudramuni@intel.com> Reviewed-by: Joe Perches <joe@perches.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
This commit is contained in:
Li, Aubrey
H. Peter Anvin
parent
b00055cade
commit
f855911c1f
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@ -25,6 +25,10 @@
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#define PMC_MMIO_REG_LEN 0x100
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#define PMC_REG_BIT_WIDTH 32
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/* BIOS uses FUNC_DIS to disable specific function */
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#define PMC_FUNC_DIS 0x34
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#define PMC_FUNC_DIS_2 0x38
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/* S0ix wake event control */
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#define PMC_S0IX_WAKE_EN 0x3C
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@ -40,6 +44,57 @@
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BIT_ORED_DEDICATED_IRQ_GPSC | \
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BIT_SHARED_IRQ_GPSS)
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/* The timers acumulate time spent in sleep state */
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#define PMC_S0IR_TMR 0x80
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#define PMC_S0I1_TMR 0x84
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#define PMC_S0I2_TMR 0x88
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#define PMC_S0I3_TMR 0x8C
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#define PMC_S0_TMR 0x90
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/* Sleep state counter is in units of of 32us */
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#define PMC_TMR_SHIFT 5
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/* These registers reflect D3 status of functions */
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#define PMC_D3_STS_0 0xA0
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#define BIT_LPSS1_F0_DMA BIT(0)
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#define BIT_LPSS1_F1_PWM1 BIT(1)
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#define BIT_LPSS1_F2_PWM2 BIT(2)
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#define BIT_LPSS1_F3_HSUART1 BIT(3)
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#define BIT_LPSS1_F4_HSUART2 BIT(4)
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#define BIT_LPSS1_F5_SPI BIT(5)
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#define BIT_LPSS1_F6_XXX BIT(6)
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#define BIT_LPSS1_F7_XXX BIT(7)
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#define BIT_SCC_EMMC BIT(8)
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#define BIT_SCC_SDIO BIT(9)
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#define BIT_SCC_SDCARD BIT(10)
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#define BIT_SCC_MIPI BIT(11)
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#define BIT_HDA BIT(12)
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#define BIT_LPE BIT(13)
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#define BIT_OTG BIT(14)
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#define BIT_USH BIT(15)
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#define BIT_GBE BIT(16)
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#define BIT_SATA BIT(17)
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#define BIT_USB_EHCI BIT(18)
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#define BIT_SEC BIT(19)
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#define BIT_PCIE_PORT0 BIT(20)
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#define BIT_PCIE_PORT1 BIT(21)
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#define BIT_PCIE_PORT2 BIT(22)
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#define BIT_PCIE_PORT3 BIT(23)
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#define BIT_LPSS2_F0_DMA BIT(24)
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#define BIT_LPSS2_F1_I2C1 BIT(25)
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#define BIT_LPSS2_F2_I2C2 BIT(26)
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#define BIT_LPSS2_F3_I2C3 BIT(27)
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#define BIT_LPSS2_F4_I2C4 BIT(28)
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#define BIT_LPSS2_F5_I2C5 BIT(29)
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#define BIT_LPSS2_F6_I2C6 BIT(30)
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#define BIT_LPSS2_F7_I2C7 BIT(31)
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#define PMC_D3_STS_1 0xA4
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#define BIT_SMB BIT(0)
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#define BIT_OTG_SS_PHY BIT(1)
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#define BIT_USH_SS_PHY BIT(2)
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#define BIT_DFX BIT(3)
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/* PMC I/O Registers */
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#define ACPI_BASE_ADDR_OFFSET 0x40
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#define ACPI_BASE_ADDR_MASK 0xFFFFFE00
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@ -19,18 +19,69 @@
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/device.h>
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#include <linux/debugfs.h>
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#include <linux/seq_file.h>
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#include <linux/io.h>
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#include <asm/pmc_atom.h>
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#define DRIVER_NAME KBUILD_MODNAME
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struct pmc_dev {
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u32 base_addr;
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void __iomem *regmap;
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#ifdef CONFIG_DEBUG_FS
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struct dentry *dbgfs_dir;
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#endif /* CONFIG_DEBUG_FS */
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};
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static struct pmc_dev pmc_device;
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static u32 acpi_base_addr;
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struct pmc_dev_map {
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const char *name;
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u32 bit_mask;
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};
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static const struct pmc_dev_map dev_map[] = {
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{"0 - LPSS1_F0_DMA", BIT_LPSS1_F0_DMA},
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{"1 - LPSS1_F1_PWM1", BIT_LPSS1_F1_PWM1},
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{"2 - LPSS1_F2_PWM2", BIT_LPSS1_F2_PWM2},
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{"3 - LPSS1_F3_HSUART1", BIT_LPSS1_F3_HSUART1},
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{"4 - LPSS1_F4_HSUART2", BIT_LPSS1_F4_HSUART2},
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{"5 - LPSS1_F5_SPI", BIT_LPSS1_F5_SPI},
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{"6 - LPSS1_F6_Reserved", BIT_LPSS1_F6_XXX},
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{"7 - LPSS1_F7_Reserved", BIT_LPSS1_F7_XXX},
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{"8 - SCC_EMMC", BIT_SCC_EMMC},
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{"9 - SCC_SDIO", BIT_SCC_SDIO},
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{"10 - SCC_SDCARD", BIT_SCC_SDCARD},
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{"11 - SCC_MIPI", BIT_SCC_MIPI},
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{"12 - HDA", BIT_HDA},
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{"13 - LPE", BIT_LPE},
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{"14 - OTG", BIT_OTG},
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{"15 - USH", BIT_USH},
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{"16 - GBE", BIT_GBE},
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{"17 - SATA", BIT_SATA},
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{"18 - USB_EHCI", BIT_USB_EHCI},
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{"19 - SEC", BIT_SEC},
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{"20 - PCIE_PORT0", BIT_PCIE_PORT0},
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{"21 - PCIE_PORT1", BIT_PCIE_PORT1},
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{"22 - PCIE_PORT2", BIT_PCIE_PORT2},
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{"23 - PCIE_PORT3", BIT_PCIE_PORT3},
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{"24 - LPSS2_F0_DMA", BIT_LPSS2_F0_DMA},
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{"25 - LPSS2_F1_I2C1", BIT_LPSS2_F1_I2C1},
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{"26 - LPSS2_F2_I2C2", BIT_LPSS2_F2_I2C2},
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{"27 - LPSS2_F3_I2C3", BIT_LPSS2_F3_I2C3},
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{"28 - LPSS2_F3_I2C4", BIT_LPSS2_F4_I2C4},
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{"29 - LPSS2_F5_I2C5", BIT_LPSS2_F5_I2C5},
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{"30 - LPSS2_F6_I2C6", BIT_LPSS2_F6_I2C6},
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{"31 - LPSS2_F7_I2C7", BIT_LPSS2_F7_I2C7},
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{"32 - SMB", BIT_SMB},
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{"33 - OTG_SS_PHY", BIT_OTG_SS_PHY},
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{"34 - USH_SS_PHY", BIT_USH_SS_PHY},
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{"35 - DFX", BIT_DFX},
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};
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static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset)
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{
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return readl(pmc->regmap + reg_offset);
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@ -71,9 +122,125 @@ static void pmc_hw_reg_setup(struct pmc_dev *pmc)
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pmc_reg_write(pmc, PMC_S0IX_WAKE_EN, (u32)PMC_WAKE_EN_SETTING);
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}
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#ifdef CONFIG_DEBUG_FS
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static int pmc_dev_state_show(struct seq_file *s, void *unused)
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{
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struct pmc_dev *pmc = s->private;
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u32 func_dis, func_dis_2, func_dis_index;
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u32 d3_sts_0, d3_sts_1, d3_sts_index;
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int dev_num, dev_index, reg_index;
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func_dis = pmc_reg_read(pmc, PMC_FUNC_DIS);
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func_dis_2 = pmc_reg_read(pmc, PMC_FUNC_DIS_2);
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d3_sts_0 = pmc_reg_read(pmc, PMC_D3_STS_0);
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d3_sts_1 = pmc_reg_read(pmc, PMC_D3_STS_1);
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dev_num = ARRAY_SIZE(dev_map);
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for (dev_index = 0; dev_index < dev_num; dev_index++) {
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reg_index = dev_index / PMC_REG_BIT_WIDTH;
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if (reg_index) {
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func_dis_index = func_dis_2;
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d3_sts_index = d3_sts_1;
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} else {
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func_dis_index = func_dis;
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d3_sts_index = d3_sts_0;
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}
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seq_printf(s, "Dev: %-32s\tState: %s [%s]\n",
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dev_map[dev_index].name,
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dev_map[dev_index].bit_mask & func_dis_index ?
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"Disabled" : "Enabled ",
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dev_map[dev_index].bit_mask & d3_sts_index ?
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"D3" : "D0");
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}
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return 0;
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}
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static int pmc_dev_state_open(struct inode *inode, struct file *file)
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{
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return single_open(file, pmc_dev_state_show, inode->i_private);
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}
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static const struct file_operations pmc_dev_state_ops = {
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.open = pmc_dev_state_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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static int pmc_sleep_tmr_show(struct seq_file *s, void *unused)
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{
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struct pmc_dev *pmc = s->private;
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u64 s0ir_tmr, s0i1_tmr, s0i2_tmr, s0i3_tmr, s0_tmr;
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s0ir_tmr = pmc_reg_read(pmc, PMC_S0IR_TMR) << PMC_TMR_SHIFT;
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s0i1_tmr = pmc_reg_read(pmc, PMC_S0I1_TMR) << PMC_TMR_SHIFT;
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s0i2_tmr = pmc_reg_read(pmc, PMC_S0I2_TMR) << PMC_TMR_SHIFT;
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s0i3_tmr = pmc_reg_read(pmc, PMC_S0I3_TMR) << PMC_TMR_SHIFT;
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s0_tmr = pmc_reg_read(pmc, PMC_S0_TMR) << PMC_TMR_SHIFT;
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seq_printf(s, "S0IR Residency:\t%lldus\n", s0ir_tmr);
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seq_printf(s, "S0I1 Residency:\t%lldus\n", s0i1_tmr);
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seq_printf(s, "S0I2 Residency:\t%lldus\n", s0i2_tmr);
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seq_printf(s, "S0I3 Residency:\t%lldus\n", s0i3_tmr);
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seq_printf(s, "S0 Residency:\t%lldus\n", s0_tmr);
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return 0;
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}
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static int pmc_sleep_tmr_open(struct inode *inode, struct file *file)
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{
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return single_open(file, pmc_sleep_tmr_show, inode->i_private);
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}
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static const struct file_operations pmc_sleep_tmr_ops = {
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.open = pmc_sleep_tmr_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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static void pmc_dbgfs_unregister(struct pmc_dev *pmc)
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{
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if (!pmc->dbgfs_dir)
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return;
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debugfs_remove_recursive(pmc->dbgfs_dir);
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pmc->dbgfs_dir = NULL;
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}
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static int pmc_dbgfs_register(struct pmc_dev *pmc, struct pci_dev *pdev)
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{
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struct dentry *dir, *f;
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dir = debugfs_create_dir("pmc_atom", NULL);
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if (!dir)
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return -ENOMEM;
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f = debugfs_create_file("dev_state", S_IFREG | S_IRUGO,
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dir, pmc, &pmc_dev_state_ops);
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if (!f) {
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dev_err(&pdev->dev, "dev_states register failed\n");
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goto err;
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}
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f = debugfs_create_file("sleep_state", S_IFREG | S_IRUGO,
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dir, pmc, &pmc_sleep_tmr_ops);
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if (!f) {
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dev_err(&pdev->dev, "sleep_state register failed\n");
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goto err;
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}
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pmc->dbgfs_dir = dir;
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return 0;
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err:
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pmc_dbgfs_unregister(pmc);
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return -ENODEV;
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}
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#endif /* CONFIG_DEBUG_FS */
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static int pmc_setup_dev(struct pci_dev *pdev)
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{
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struct pmc_dev *pmc = &pmc_device;
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int ret;
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/* Obtain ACPI base address */
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pci_read_config_dword(pdev, ACPI_BASE_ADDR_OFFSET, &acpi_base_addr);
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@ -94,6 +261,14 @@ static int pmc_setup_dev(struct pci_dev *pdev)
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/* PMC hardware registers setup */
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pmc_hw_reg_setup(pmc);
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#ifdef CONFIG_DEBUG_FS
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ret = pmc_dbgfs_register(pmc, pdev);
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if (ret) {
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iounmap(pmc->regmap);
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return ret;
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}
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#endif /* CONFIG_DEBUG_FS */
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return 0;
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}
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