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drm/nouveau/kms/nv50-: use NVIDIA's headers for wndw image_set() 

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
This commit is contained in:
Ben Skeggs 2020-06-20 13:08:47 +10:00
parent 66f7b7bddf
commit f844eb485e
12 changed files with 557 additions and 135 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

52
drivers/gpu/drm/nouveau/dispnv50/base507c.c
View File

@ -70,25 +70,43 @@ base507c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
if ((ret = PUSH_WAIT(push, 13))) if ((ret = PUSH_WAIT(push, 13)))
return ret; return ret;
PUSH_NVSQ(push, NV507C, 0x0084, asyw->image.mode << 8 | PUSH_MTHD(push, NV507C, SET_PRESENT_CONTROL,
asyw->image.interval << 4); NVVAL(NV507C, SET_PRESENT_CONTROL, BEGIN_MODE, asyw->image.mode) |
PUSH_NVSQ(push, NV507C, 0x00c0, asyw->image.handle[0]); NVVAL(NV507C, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval));
if (asyw->image.format == 0xca) {
PUSH_NVSQ(push, NV507C, 0x0110, 1, PUSH_MTHD(push, NV507C, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]);
0x0114, 0x6400);
if (asyw->image.format == NV507C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16) {
PUSH_MTHD(push, NV507C, SET_PROCESSING,
NVDEF(NV507C, SET_PROCESSING, USE_GAIN_OFS, ENABLE),
SET_CONVERSION,
NVVAL(NV507C, SET_CONVERSION, GAIN, 0) |
NVVAL(NV507C, SET_CONVERSION, OFS, 0x64));
} else { } else {
PUSH_NVSQ(push, NV507C, 0x0110, 0, PUSH_MTHD(push, NV507C, SET_PROCESSING,
0x0114, 0); NVDEF(NV507C, SET_PROCESSING, USE_GAIN_OFS, DISABLE));
} }
PUSH_NVSQ(push, NV507C, 0x0800, asyw->image.offset[0] >> 8,
0x0804, 0x00000000, PUSH_MTHD(push, NV507C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8);
0x0808, asyw->image.h << 16 | asyw->image.w,
0x080c, asyw->image.layout << 20 | PUSH_MTHD(push, NV507C, SURFACE_SET_SIZE(0),
(asyw->image.pitch[0] >> 8) << 8 | NVVAL(NV507C, SURFACE_SET_SIZE, WIDTH, asyw->image.w) |
asyw->image.blocks[0] << 8 | NVVAL(NV507C, SURFACE_SET_SIZE, HEIGHT, asyw->image.h),
asyw->image.blockh,
0x0810, asyw->image.kind << 16 | SURFACE_SET_STORAGE(0),
asyw->image.format << 8); NVVAL(NV507C, SURFACE_SET_STORAGE, MEMORY_LAYOUT, asyw->image.layout) |
NVVAL(NV507C, SURFACE_SET_STORAGE, PITCH, asyw->image.pitch[0] >> 8) |
NVVAL(NV507C, SURFACE_SET_STORAGE, PITCH, asyw->image.blocks[0]) |
NVVAL(NV507C, SURFACE_SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh),
SURFACE_SET_PARAMS(0),
NVVAL(NV507C, SURFACE_SET_PARAMS, FORMAT, asyw->image.format) |
NVDEF(NV507C, SURFACE_SET_PARAMS, SUPER_SAMPLE, X1_AA) |
NVDEF(NV507C, SURFACE_SET_PARAMS, GAMMA, LINEAR) |
NVDEF(NV507C, SURFACE_SET_PARAMS, LAYOUT, FRM) |
NVVAL(NV507C, SURFACE_SET_PARAMS, KIND, asyw->image.kind) |
NVDEF(NV507C, SURFACE_SET_PARAMS, PART_STRIDE, PARTSTRIDE_256));
return 0; return 0;
} }

52
drivers/gpu/drm/nouveau/dispnv50/base827c.c
View File

@ -23,6 +23,8 @@
#include <nvif/push507c.h> #include <nvif/push507c.h>
#include <nvhw/class/cl827c.h>
static int static int
base827c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) base827c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
{ {
@ -32,24 +34,42 @@ base827c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
if ((ret = PUSH_WAIT(push, 13))) if ((ret = PUSH_WAIT(push, 13)))
return ret; return ret;
PUSH_NVSQ(push, NV827C, 0x0084, asyw->image.mode << 8 | PUSH_MTHD(push, NV827C, SET_PRESENT_CONTROL,
asyw->image.interval << 4); NVVAL(NV827C, SET_PRESENT_CONTROL, BEGIN_MODE, asyw->image.mode) |
PUSH_NVSQ(push, NV827C, 0x00c0, asyw->image.handle[0]); NVVAL(NV827C, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval));
if (asyw->image.format == 0xca) {
PUSH_NVSQ(push, NV827C, 0x0110, 1, PUSH_MTHD(push, NV827C, SET_CONTEXT_DMAS_ISO(0), asyw->image.handle, 1);
0x0114, 0x6400);
if (asyw->image.format == NV827C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16) {
PUSH_MTHD(push, NV827C, SET_PROCESSING,
NVDEF(NV827C, SET_PROCESSING, USE_GAIN_OFS, ENABLE),
SET_CONVERSION,
NVVAL(NV827C, SET_CONVERSION, GAIN, 0) |
NVVAL(NV827C, SET_CONVERSION, OFS, 0x64));
} else { } else {
PUSH_NVSQ(push, NV827C, 0x0110, 0, PUSH_MTHD(push, NV827C, SET_PROCESSING,
0x0114, 0); NVDEF(NV827C, SET_PROCESSING, USE_GAIN_OFS, DISABLE));
} }
PUSH_NVSQ(push, NV827C, 0x0800, asyw->image.offset[0] >> 8,
0x0804, 0x00000000, PUSH_MTHD(push, NV827C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8,
0x0808, asyw->image.h << 16 | asyw->image.w, SURFACE_SET_OFFSET(0, 1), 0x00000000,
0x080c, asyw->image.layout << 20 |
(asyw->image.pitch[0] >> 8) << 8 | SURFACE_SET_SIZE(0),
asyw->image.blocks[0] << 8 | NVVAL(NV827C, SURFACE_SET_SIZE, WIDTH, asyw->image.w) |
asyw->image.blockh, NVVAL(NV827C, SURFACE_SET_SIZE, HEIGHT, asyw->image.h),
0x0810, asyw->image.format << 8);
SURFACE_SET_STORAGE(0),
NVVAL(NV827C, SURFACE_SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh) |
NVVAL(NV827C, SURFACE_SET_STORAGE, PITCH, asyw->image.pitch[0] >> 8) |
NVVAL(NV827C, SURFACE_SET_STORAGE, PITCH, asyw->image.blocks[0]) |
NVVAL(NV827C, SURFACE_SET_STORAGE, MEMORY_LAYOUT, asyw->image.layout),
SURFACE_SET_PARAMS(0),
NVVAL(NV827C, SURFACE_SET_PARAMS, FORMAT, asyw->image.format) |
NVDEF(NV827C, SURFACE_SET_PARAMS, SUPER_SAMPLE, X1_AA) |
NVDEF(NV827C, SURFACE_SET_PARAMS, GAMMA, LINEAR) |
NVDEF(NV827C, SURFACE_SET_PARAMS, LAYOUT, FRM));
return 0; return 0;
} }

36
drivers/gpu/drm/nouveau/dispnv50/base907c.c
View File

@ -34,17 +34,31 @@ base907c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
if ((ret = PUSH_WAIT(push, 10))) if ((ret = PUSH_WAIT(push, 10)))
return ret; return ret;
PUSH_NVSQ(push, NV907C, 0x0084, asyw->image.mode << 8 | PUSH_MTHD(push, NV907C, SET_PRESENT_CONTROL,
asyw->image.interval << 4); NVVAL(NV907C, SET_PRESENT_CONTROL, BEGIN_MODE, asyw->image.mode) |
PUSH_NVSQ(push, NV907C, 0x00c0, asyw->image.handle[0]); NVDEF(NV907C, SET_PRESENT_CONTROL, TIMESTAMP_MODE, DISABLE) |
PUSH_NVSQ(push, NV907C, 0x0400, asyw->image.offset[0] >> 8, NVVAL(NV907C, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval));
0x0404, 0x00000000,
0x0408, asyw->image.h << 16 | asyw->image.w, PUSH_MTHD(push, NV907C, SET_CONTEXT_DMAS_ISO(0), asyw->image.handle, 1);
0x040c, asyw->image.layout << 24 |
(asyw->image.pitch[0] >> 8) << 8 | PUSH_MTHD(push, NV907C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8,
asyw->image.blocks[0] << 8 | SURFACE_SET_OFFSET(0, 1), 0x00000000,
asyw->image.blockh,
0x0410, asyw->image.format << 8); SURFACE_SET_SIZE(0),
NVVAL(NV907C, SURFACE_SET_SIZE, WIDTH, asyw->image.w) |
NVVAL(NV907C, SURFACE_SET_SIZE, HEIGHT, asyw->image.h),
SURFACE_SET_STORAGE(0),
NVVAL(NV907C, SURFACE_SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh) |
NVVAL(NV907C, SURFACE_SET_STORAGE, PITCH, asyw->image.pitch[0] >> 8) |
NVVAL(NV907C, SURFACE_SET_STORAGE, PITCH, asyw->image.blocks[0]) |
NVVAL(NV907C, SURFACE_SET_STORAGE, MEMORY_LAYOUT, asyw->image.layout),
SURFACE_SET_PARAMS(0),
NVVAL(NV907C, SURFACE_SET_PARAMS, FORMAT, asyw->image.format) |
NVDEF(NV907C, SURFACE_SET_PARAMS, SUPER_SAMPLE, X1_AA) |
NVDEF(NV907C, SURFACE_SET_PARAMS, GAMMA, LINEAR) |
NVDEF(NV907C, SURFACE_SET_PARAMS, LAYOUT, FRM));
return 0; return 0;
} }

40
drivers/gpu/drm/nouveau/dispnv50/ovly507e.c
View File

@ -30,6 +30,8 @@
#include <nvif/event.h> #include <nvif/event.h>
#include <nvif/push507c.h> #include <nvif/push507c.h>
#include <nvhw/class/cl507e.h>
int int
ovly507e_scale_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) ovly507e_scale_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
{ {
@ -54,18 +56,32 @@ ovly507e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
if ((ret = PUSH_WAIT(push, 12))) if ((ret = PUSH_WAIT(push, 12)))
return ret; return ret;
PUSH_NVSQ(push, NV507E, 0x0084, asyw->image.interval << 4); PUSH_MTHD(push, NV507E, SET_PRESENT_CONTROL,
PUSH_NVSQ(push, NV507E, 0x00c0, asyw->image.handle[0]); NVDEF(NV507E, SET_PRESENT_CONTROL, BEGIN_MODE, ASAP) |
PUSH_NVSQ(push, NV507E, 0x0100, 0x00000002); NVVAL(NV507E, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval));
PUSH_NVSQ(push, NV507E, 0x0800, asyw->image.offset[0] >> 8);
PUSH_NVSQ(push, NV507E, 0x0808, asyw->image.h << 16 | asyw->image.w, PUSH_MTHD(push, NV507E, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]);
0x080c, asyw->image.layout << 20 |
(asyw->image.pitch[0] >> 8) << 8 | PUSH_MTHD(push, NV507E, SET_COMPOSITION_CONTROL,
asyw->image.blocks[0] << 8 | NVDEF(NV507E, SET_COMPOSITION_CONTROL, MODE, OPAQUE_SUSPEND_BASE));
asyw->image.blockh,
0x0810, asyw->image.kind << 16 | PUSH_MTHD(push, NV507E, SURFACE_SET_OFFSET, asyw->image.offset[0] >> 8);
asyw->image.format << 8 |
asyw->image.colorspace); PUSH_MTHD(push, NV507E, SURFACE_SET_SIZE,
NVVAL(NV507E, SURFACE_SET_SIZE, WIDTH, asyw->image.w) |
NVVAL(NV507E, SURFACE_SET_SIZE, HEIGHT, asyw->image.h),
SURFACE_SET_STORAGE,
NVVAL(NV507E, SURFACE_SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh) |
NVVAL(NV507E, SURFACE_SET_STORAGE, PITCH, (asyw->image.pitch[0] >> 8)) |
NVVAL(NV507E, SURFACE_SET_STORAGE, PITCH, asyw->image.blocks[0]) |
NVVAL(NV507E, SURFACE_SET_STORAGE, MEMORY_LAYOUT, asyw->image.layout),
SURFACE_SET_PARAMS,
NVVAL(NV507E, SURFACE_SET_PARAMS, FORMAT, asyw->image.format) |
NVVAL(NV507E, SURFACE_SET_PARAMS, COLOR_SPACE, asyw->image.colorspace) |
NVVAL(NV507E, SURFACE_SET_PARAMS, KIND, asyw->image.kind) |
NVDEF(NV507E, SURFACE_SET_PARAMS, PART_STRIDE, PARTSTRIDE_256));
return 0; return 0;
} }

35
drivers/gpu/drm/nouveau/dispnv50/ovly827e.c
View File

@ -38,17 +38,30 @@ ovly827e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
if ((ret = PUSH_WAIT(push, 12))) if ((ret = PUSH_WAIT(push, 12)))
return ret; return ret;
PUSH_NVSQ(push, NV827E, 0x0084, asyw->image.interval << 4); PUSH_MTHD(push, NV827E, SET_PRESENT_CONTROL,
PUSH_NVSQ(push, NV827E, 0x00c0, asyw->image.handle[0]); NVDEF(NV827E, SET_PRESENT_CONTROL, BEGIN_MODE, ASAP) |
PUSH_NVSQ(push, NV827E, 0x0100, 0x00000002); NVVAL(NV827E, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval));
PUSH_NVSQ(push, NV827E, 0x0800, asyw->image.offset[0] >> 8);
PUSH_NVSQ(push, NV827E, 0x0808, asyw->image.h << 16 | asyw->image.w, PUSH_MTHD(push, NV827E, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]);
0x080c, asyw->image.layout << 20 |
(asyw->image.pitch[0] >> 8) << 8 | PUSH_MTHD(push, NV827E, SET_COMPOSITION_CONTROL,
asyw->image.blocks[0] << 8 | NVDEF(NV827E, SET_COMPOSITION_CONTROL, MODE, OPAQUE_SUSPEND_BASE));
asyw->image.blockh,
0x0810, asyw->image.format << 8 | PUSH_MTHD(push, NV827E, SURFACE_SET_OFFSET, asyw->image.offset[0] >> 8);
asyw->image.colorspace);
PUSH_MTHD(push, NV827E, SURFACE_SET_SIZE,
NVVAL(NV827E, SURFACE_SET_SIZE, WIDTH, asyw->image.w) |
NVVAL(NV827E, SURFACE_SET_SIZE, HEIGHT, asyw->image.h),
SURFACE_SET_STORAGE,
NVVAL(NV827E, SURFACE_SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh) |
NVVAL(NV827E, SURFACE_SET_STORAGE, PITCH, (asyw->image.pitch[0] >> 8)) |
NVVAL(NV827E, SURFACE_SET_STORAGE, PITCH, asyw->image.blocks[0]) |
NVVAL(NV827E, SURFACE_SET_STORAGE, MEMORY_LAYOUT, asyw->image.layout),
SURFACE_SET_PARAMS,
NVVAL(NV827E, SURFACE_SET_PARAMS, FORMAT, asyw->image.format) |
NVVAL(NV827E, SURFACE_SET_PARAMS, COLOR_SPACE, asyw->image.colorspace));
return 0; return 0;
} }

37
drivers/gpu/drm/nouveau/dispnv50/ovly907e.c
View File

@ -24,6 +24,8 @@
#include <nvif/push507c.h> #include <nvif/push507c.h>
#include <nvhw/class/cl907e.h>
static int static int
ovly907e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) ovly907e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
{ {
@ -33,17 +35,30 @@ ovly907e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
if ((ret = PUSH_WAIT(push, 12))) if ((ret = PUSH_WAIT(push, 12)))
return ret; return ret;
PUSH_NVSQ(push, NV907E, 0x0084, asyw->image.interval << 4); PUSH_MTHD(push, NV907E, SET_PRESENT_CONTROL,
PUSH_NVSQ(push, NV907E, 0x00c0, asyw->image.handle[0]); NVDEF(NV907E, SET_PRESENT_CONTROL, BEGIN_MODE, ASAP) |
PUSH_NVSQ(push, NV907E, 0x0100, 0x00000002); NVVAL(NV907E, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval));
PUSH_NVSQ(push, NV907E, 0x0400, asyw->image.offset[0] >> 8);
PUSH_NVSQ(push, NV907E, 0x0408, asyw->image.h << 16 | asyw->image.w, PUSH_MTHD(push, NV907E, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]);
0x040c, asyw->image.layout << 24 |
(asyw->image.pitch[0] >> 8) << 8 | PUSH_MTHD(push, NV907E, SET_COMPOSITION_CONTROL,
asyw->image.blocks[0] << 8 | NVDEF(NV907E, SET_COMPOSITION_CONTROL, MODE, OPAQUE));
asyw->image.blockh,
0x0410, asyw->image.format << 8 | PUSH_MTHD(push, NV907E, SURFACE_SET_OFFSET, asyw->image.offset[0] >> 8);
asyw->image.colorspace);
PUSH_MTHD(push, NV907E, SURFACE_SET_SIZE,
NVVAL(NV907E, SURFACE_SET_SIZE, WIDTH, asyw->image.w) |
NVVAL(NV907E, SURFACE_SET_SIZE, HEIGHT, asyw->image.h),
SURFACE_SET_STORAGE,
NVVAL(NV907E, SURFACE_SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh) |
NVVAL(NV907E, SURFACE_SET_STORAGE, PITCH, (asyw->image.pitch[0] >> 8)) |
NVVAL(NV907E, SURFACE_SET_STORAGE, PITCH, asyw->image.blocks[0]) |
NVVAL(NV907E, SURFACE_SET_STORAGE, MEMORY_LAYOUT, asyw->image.layout),
SURFACE_SET_PARAMS,
NVVAL(NV907E, SURFACE_SET_PARAMS, FORMAT, asyw->image.format) |
NVVAL(NV907E, SURFACE_SET_PARAMS, COLOR_SPACE, asyw->image.colorspace));
return 0; return 0;
} }

75
drivers/gpu/drm/nouveau/dispnv50/wndw.c
View File

@ -26,6 +26,10 @@
#include <nvif/class.h> #include <nvif/class.h>
#include <nvif/cl0002.h> #include <nvif/cl0002.h>
#include <nvhw/class/cl507c.h>
#include <nvhw/class/cl507e.h>
#include <nvhw/class/clc37e.h>
#include <drm/drm_atomic_helper.h> #include <drm/drm_atomic_helper.h>
#include <drm/drm_fourcc.h> #include <drm/drm_fourcc.h>
@ -137,7 +141,7 @@ nv50_wndw_flush_set(struct nv50_wndw *wndw, u32 *interlock,
struct nv50_wndw_atom *asyw) struct nv50_wndw_atom *asyw)
{ {
if (interlock[NV50_DISP_INTERLOCK_CORE]) { if (interlock[NV50_DISP_INTERLOCK_CORE]) {
asyw->image.mode = 0; asyw->image.mode = NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING;
asyw->image.interval = 1; asyw->image.interval = 1;
} }
@ -201,13 +205,18 @@ static int
nv50_wndw_atomic_check_acquire_yuv(struct nv50_wndw_atom *asyw) nv50_wndw_atomic_check_acquire_yuv(struct nv50_wndw_atom *asyw)
{ {
switch (asyw->state.fb->format->format) { switch (asyw->state.fb->format->format) {
case DRM_FORMAT_YUYV: asyw->image.format = 0x28; break; case DRM_FORMAT_YUYV:
case DRM_FORMAT_UYVY: asyw->image.format = 0x29; break; asyw->image.format = NV507E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8;
break;
case DRM_FORMAT_UYVY:
asyw->image.format = NV507E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8;
break;
default: default:
WARN_ON(1); WARN_ON(1);
return -EINVAL; return -EINVAL;
} }
asyw->image.colorspace = 1;
asyw->image.colorspace = NV507E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601;
return 0; return 0;
} }
@ -215,24 +224,41 @@ static int
nv50_wndw_atomic_check_acquire_rgb(struct nv50_wndw_atom *asyw) nv50_wndw_atomic_check_acquire_rgb(struct nv50_wndw_atom *asyw)
{ {
switch (asyw->state.fb->format->format) { switch (asyw->state.fb->format->format) {
case DRM_FORMAT_C8 : asyw->image.format = 0x1e; break; case DRM_FORMAT_C8:
case DRM_FORMAT_XRGB8888 : asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_I8;
case DRM_FORMAT_ARGB8888 : asyw->image.format = 0xcf; break; break;
case DRM_FORMAT_RGB565 : asyw->image.format = 0xe8; break; case DRM_FORMAT_XRGB8888:
case DRM_FORMAT_XRGB1555 : case DRM_FORMAT_ARGB8888:
case DRM_FORMAT_ARGB1555 : asyw->image.format = 0xe9; break; asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8;
case DRM_FORMAT_XBGR2101010 : break;
case DRM_FORMAT_ABGR2101010 : asyw->image.format = 0xd1; break; case DRM_FORMAT_RGB565:
case DRM_FORMAT_XBGR8888 : asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_R5G6B5;
case DRM_FORMAT_ABGR8888 : asyw->image.format = 0xd5; break; break;
case DRM_FORMAT_XRGB2101010 : case DRM_FORMAT_XRGB1555:
case DRM_FORMAT_ARGB2101010 : asyw->image.format = 0xdf; break; case DRM_FORMAT_ARGB1555:
asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5;
break;
case DRM_FORMAT_XBGR2101010:
case DRM_FORMAT_ABGR2101010:
asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10;
break;
case DRM_FORMAT_XBGR8888:
case DRM_FORMAT_ABGR8888:
asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8;
break;
case DRM_FORMAT_XRGB2101010:
case DRM_FORMAT_ARGB2101010:
asyw->image.format = NVC37E_SET_PARAMS_FORMAT_A2R10G10B10;
break;
case DRM_FORMAT_XBGR16161616F: case DRM_FORMAT_XBGR16161616F:
case DRM_FORMAT_ABGR16161616F: asyw->image.format = 0xca; break; case DRM_FORMAT_ABGR16161616F:
asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16;
break;
default: default:
return -EINVAL; return -EINVAL;
} }
asyw->image.colorspace = 0;
asyw->image.colorspace = NV507E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB;
return 0; return 0;
} }
@ -265,7 +291,7 @@ nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw, bool modeset,
} }
if (asyw->image.kind) { if (asyw->image.kind) {
asyw->image.layout = 0; asyw->image.layout = NV507C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR;
if (drm->client.device.info.chipset >= 0xc0) if (drm->client.device.info.chipset >= 0xc0)
asyw->image.blockh = tile_mode >> 4; asyw->image.blockh = tile_mode >> 4;
else else
@ -273,8 +299,8 @@ nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw, bool modeset,
asyw->image.blocks[0] = fb->pitches[0] / 64; asyw->image.blocks[0] = fb->pitches[0] / 64;
asyw->image.pitch[0] = 0; asyw->image.pitch[0] = 0;
} else { } else {
asyw->image.layout = 1; asyw->image.layout = NV507C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH;
asyw->image.blockh = 0; asyw->image.blockh = NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB;
asyw->image.blocks[0] = 0; asyw->image.blocks[0] = 0;
asyw->image.pitch[0] = fb->pitches[0]; asyw->image.pitch[0] = fb->pitches[0];
} }
@ -283,7 +309,12 @@ nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw, bool modeset,
asyw->image.interval = 1; asyw->image.interval = 1;
else else
asyw->image.interval = 0; asyw->image.interval = 0;
asyw->image.mode = asyw->image.interval ? 0 : 1;
if (asyw->image.interval)
asyw->image.mode = NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING;
else
asyw->image.mode = NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE;
asyw->set.image = wndw->func->image_set != NULL; asyw->set.image = wndw->func->image_set != NULL;
} }

59
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
View File

@ -141,24 +141,47 @@ wndwc37e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
if ((ret = PUSH_WAIT(push, 17))) if ((ret = PUSH_WAIT(push, 17)))
return ret; return ret;
PUSH_NVSQ(push, NVC37E, 0x0308, asyw->image.mode << 4 | PUSH_MTHD(push, NVC37E, SET_PRESENT_CONTROL,
asyw->image.interval); NVVAL(NVC37E, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval) |
PUSH_NVSQ(push, NVC37E, 0x0224, asyw->image.h << 16 | asyw->image.w, NVVAL(NVC37E, SET_PRESENT_CONTROL, BEGIN_MODE, asyw->image.mode) |
0x0228, asyw->image.layout << 4 | NVDEF(NVC37E, SET_PRESENT_CONTROL, TIMESTAMP_MODE, DISABLE));
asyw->image.blockh,
0x022c, asyw->csc.valid << 17 | PUSH_MTHD(push, NVC37E, SET_SIZE,
asyw->image.colorspace << 8 | NVVAL(NVC37E, SET_SIZE, WIDTH, asyw->image.w) |
asyw->image.format, NVVAL(NVC37E, SET_SIZE, HEIGHT, asyw->image.h),
0x0230, asyw->image.blocks[0] |
(asyw->image.pitch[0] >> 6)); SET_STORAGE,
PUSH_NVSQ(push, NVC37E, 0x0240, asyw->image.handle[0]); NVVAL(NVC37E, SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh) |
PUSH_NVSQ(push, NVC37E, 0x0260, asyw->image.offset[0] >> 8); NVVAL(NVC37E, SET_STORAGE, MEMORY_LAYOUT, asyw->image.layout),
PUSH_NVSQ(push, NVC37E, 0x0290,(asyw->state.src_y >> 16) << 16 |
(asyw->state.src_x >> 16)); SET_PARAMS,
PUSH_NVSQ(push, NVC37E, 0x0298,(asyw->state.src_h >> 16) << 16 | NVVAL(NVC37E, SET_PARAMS, FORMAT, asyw->image.format) |
(asyw->state.src_w >> 16)); NVVAL(NVC37E, SET_PARAMS, COLOR_SPACE, asyw->image.colorspace) |
PUSH_NVSQ(push, NVC37E, 0x02a4, asyw->state.crtc_h << 16 | NVDEF(NVC37E, SET_PARAMS, INPUT_RANGE, BYPASS) |
asyw->state.crtc_w); NVDEF(NVC37E, SET_PARAMS, UNDERREPLICATE, DISABLE) |
NVDEF(NVC37E, SET_PARAMS, DE_GAMMA, NONE) |
NVVAL(NVC37E, SET_PARAMS, CSC, asyw->csc.valid) |
NVDEF(NVC37E, SET_PARAMS, CLAMP_BEFORE_BLEND, DISABLE) |
NVDEF(NVC37E, SET_PARAMS, SWAP_UV, DISABLE),
SET_PLANAR_STORAGE(0),
NVVAL(NVC37E, SET_PLANAR_STORAGE, PITCH, asyw->image.blocks[0]) |
NVVAL(NVC37E, SET_PLANAR_STORAGE, PITCH, asyw->image.pitch[0] >> 6));
PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_ISO(0), asyw->image.handle, 1);
PUSH_MTHD(push, NVC37E, SET_OFFSET(0), asyw->image.offset[0] >> 8);
PUSH_MTHD(push, NVC37E, SET_POINT_IN(0),
NVVAL(NVC37E, SET_POINT_IN, X, asyw->state.src_x >> 16) |
NVVAL(NVC37E, SET_POINT_IN, Y, asyw->state.src_y >> 16));
PUSH_MTHD(push, NVC37E, SET_SIZE_IN,
NVVAL(NVC37E, SET_SIZE_IN, WIDTH, asyw->state.src_w >> 16) |
NVVAL(NVC37E, SET_SIZE_IN, HEIGHT, asyw->state.src_h >> 16));
PUSH_MTHD(push, NVC37E, SET_SIZE_OUT,
NVVAL(NVC37E, SET_SIZE_OUT, WIDTH, asyw->state.crtc_w) |
NVVAL(NVC37E, SET_SIZE_OUT, HEIGHT, asyw->state.crtc_h));
return 0; return 0;
} }

54
drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c
View File

@ -40,23 +40,43 @@ wndwc57e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
if ((ret = PUSH_WAIT(push, 17))) if ((ret = PUSH_WAIT(push, 17)))
return ret; return ret;
PUSH_NVSQ(push, NVC57E, 0x0308, asyw->image.mode << 4 | PUSH_MTHD(push, NVC57E, SET_PRESENT_CONTROL,
asyw->image.interval); NVVAL(NVC57E, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval) |
PUSH_NVSQ(push, NVC57E, 0x0224, asyw->image.h << 16 | asyw->image.w, NVVAL(NVC57E, SET_PRESENT_CONTROL, BEGIN_MODE, asyw->image.mode) |
0x0228, asyw->image.layout << 4 | NVDEF(NVC57E, SET_PRESENT_CONTROL, TIMESTAMP_MODE, DISABLE));
asyw->image.blockh,
0x022c, asyw->image.colorspace << 8 | PUSH_MTHD(push, NVC57E, SET_SIZE,
asyw->image.format, NVVAL(NVC57E, SET_SIZE, WIDTH, asyw->image.w) |
0x0230, asyw->image.blocks[0] | NVVAL(NVC57E, SET_SIZE, HEIGHT, asyw->image.h),
(asyw->image.pitch[0] >> 6));
PUSH_NVSQ(push, NVC57E, 0x0240, asyw->image.handle[0]); SET_STORAGE,
PUSH_NVSQ(push, NVC57E, 0x0260, asyw->image.offset[0] >> 8); NVVAL(NVC57E, SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh) |
PUSH_NVSQ(push, NVC57E, 0x0290,(asyw->state.src_y >> 16) << 16 | NVVAL(NVC57E, SET_STORAGE, MEMORY_LAYOUT, asyw->image.layout),
(asyw->state.src_x >> 16));
PUSH_NVSQ(push, NVC57E, 0x0298,(asyw->state.src_h >> 16) << 16 | SET_PARAMS,
(asyw->state.src_w >> 16)); NVVAL(NVC57E, SET_PARAMS, FORMAT, asyw->image.format) |
PUSH_NVSQ(push, NVC57E, 0x02a4, asyw->state.crtc_h << 16 | NVDEF(NVC57E, SET_PARAMS, CLAMP_BEFORE_BLEND, DISABLE) |
asyw->state.crtc_w); NVDEF(NVC57E, SET_PARAMS, SWAP_UV, DISABLE) |
NVDEF(NVC57E, SET_PARAMS, FMT_ROUNDING_MODE, ROUND_TO_NEAREST),
SET_PLANAR_STORAGE(0),
NVVAL(NVC57E, SET_PLANAR_STORAGE, PITCH, asyw->image.blocks[0]) |
NVVAL(NVC57E, SET_PLANAR_STORAGE, PITCH, asyw->image.pitch[0] >> 6));
PUSH_MTHD(push, NVC57E, SET_CONTEXT_DMA_ISO(0), asyw->image.handle, 1);
PUSH_MTHD(push, NVC57E, SET_OFFSET(0), asyw->image.offset[0] >> 8);
PUSH_MTHD(push, NVC57E, SET_POINT_IN(0),
NVVAL(NVC57E, SET_POINT_IN, X, asyw->state.src_x >> 16) |
NVVAL(NVC57E, SET_POINT_IN, Y, asyw->state.src_y >> 16));
PUSH_MTHD(push, NVC57E, SET_SIZE_IN,
NVVAL(NVC57E, SET_SIZE_IN, WIDTH, asyw->state.src_w >> 16) |
NVVAL(NVC57E, SET_SIZE_IN, HEIGHT, asyw->state.src_h >> 16));
PUSH_MTHD(push, NVC57E, SET_SIZE_OUT,
NVVAL(NVC57E, SET_SIZE_OUT, WIDTH, asyw->state.crtc_w) |
NVVAL(NVC57E, SET_SIZE_OUT, HEIGHT, asyw->state.crtc_h));
return 0; return 0;
} }

93
drivers/gpu/drm/nouveau/include/nvhw/class/cl507e.h Normal file
View File

@ -0,0 +1,93 @@
/*
* Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl507e_h_
#define _cl507e_h_
// class methods
#define NV507E_SET_PRESENT_CONTROL (0x00000084)
#define NV507E_SET_PRESENT_CONTROL_BEGIN_MODE 1:0
#define NV507E_SET_PRESENT_CONTROL_BEGIN_MODE_ASAP (0x00000000)
#define NV507E_SET_PRESENT_CONTROL_BEGIN_MODE_TIMESTAMP (0x00000003)
#define NV507E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4
#define NV507E_SET_CONTEXT_DMA_ISO (0x000000C0)
#define NV507E_SET_CONTEXT_DMA_ISO_HANDLE 31:0
#define NV507E_SET_POINT_IN (0x000000E0)
#define NV507E_SET_POINT_IN_X 14:0
#define NV507E_SET_POINT_IN_Y 30:16
#define NV507E_SET_SIZE_IN (0x000000E4)
#define NV507E_SET_SIZE_IN_WIDTH 14:0
#define NV507E_SET_SIZE_IN_HEIGHT 30:16
#define NV507E_SET_SIZE_OUT (0x000000E8)
#define NV507E_SET_SIZE_OUT_WIDTH 14:0
#define NV507E_SET_COMPOSITION_CONTROL (0x00000100)
#define NV507E_SET_COMPOSITION_CONTROL_MODE 3:0
#define NV507E_SET_COMPOSITION_CONTROL_MODE_SOURCE_COLOR_VALUE_KEYING (0x00000000)
#define NV507E_SET_COMPOSITION_CONTROL_MODE_DESTINATION_COLOR_VALUE_KEYING (0x00000001)
#define NV507E_SET_COMPOSITION_CONTROL_MODE_OPAQUE_SUSPEND_BASE (0x00000002)
#define NV507E_SURFACE_SET_OFFSET (0x00000800)
#define NV507E_SURFACE_SET_OFFSET_ORIGIN 31:0
#define NV507E_SURFACE_SET_SIZE (0x00000808)
#define NV507E_SURFACE_SET_SIZE_WIDTH 14:0
#define NV507E_SURFACE_SET_SIZE_HEIGHT 30:16
#define NV507E_SURFACE_SET_STORAGE (0x0000080C)
#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0
#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000)
#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001)
#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002)
#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003)
#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004)
#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005)
#define NV507E_SURFACE_SET_STORAGE_PITCH 17:8
#define NV507E_SURFACE_SET_STORAGE_MEMORY_LAYOUT 20:20
#define NV507E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000)
#define NV507E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001)
#define NV507E_SURFACE_SET_PARAMS (0x00000810)
#define NV507E_SURFACE_SET_PARAMS_FORMAT 15:8
#define NV507E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8 (0x00000028)
#define NV507E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8 (0x00000029)
#define NV507E_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF)
#define NV507E_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9)
#define NV507E_SURFACE_SET_PARAMS_COLOR_SPACE 1:0
#define NV507E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB (0x00000000)
#define NV507E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601 (0x00000001)
#define NV507E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_709 (0x00000002)
#define NV507E_SURFACE_SET_PARAMS_KIND 22:16
#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_PITCH (0x00000000)
#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_8BX2 (0x00000070)
#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_8BX2_BANKSWIZ (0x00000072)
#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_16BX1 (0x00000074)
#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_16BX1_BANKSWIZ (0x00000076)
#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C32_MS4 (0x00000078)
#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C32_MS8 (0x00000079)
#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C32_MS4_BANKSWIZ (0x0000007A)
#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C32_MS8_BANKSWIZ (0x0000007B)
#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C64_MS4 (0x0000007C)
#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C64_MS8 (0x0000007D)
#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C128_MS4 (0x0000007E)
#define NV507E_SURFACE_SET_PARAMS_KIND_FROM_PTE (0x0000007F)
#define NV507E_SURFACE_SET_PARAMS_PART_STRIDE 24:24
#define NV507E_SURFACE_SET_PARAMS_PART_STRIDE_PARTSTRIDE_256 (0x00000000)
#define NV507E_SURFACE_SET_PARAMS_PART_STRIDE_PARTSTRIDE_1024 (0x00000001)
#endif // _cl507e_h

86
drivers/gpu/drm/nouveau/include/nvhw/class/cl827c.h Normal file
View File

@ -0,0 +1,86 @@
/*
* Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl827c_h_
#define _cl827c_h_
// class methods
#define NV827C_SET_PRESENT_CONTROL (0x00000084)
#define NV827C_SET_PRESENT_CONTROL_BEGIN_MODE 9:8
#define NV827C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000)
#define NV827C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001)
#define NV827C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE (0x00000002)
#define NV827C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4
#define NV827C_SET_PRESENT_CONTROL_BEGIN_LINE 30:16
#define NV827C_SET_PRESENT_CONTROL_ON_LINE_MARGIN 15:10
#define NV827C_SET_CONTEXT_DMAS_ISO(b) (0x000000C0 + (b)*0x00000004)
#define NV827C_SET_CONTEXT_DMAS_ISO_HANDLE 31:0
#define NV827C_SET_PROCESSING (0x00000110)
#define NV827C_SET_PROCESSING_USE_GAIN_OFS 0:0
#define NV827C_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000)
#define NV827C_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001)
#define NV827C_SET_CONVERSION (0x00000114)
#define NV827C_SET_CONVERSION_GAIN 15:0
#define NV827C_SET_CONVERSION_OFS 31:16
#define NV827C_SURFACE_SET_OFFSET(a,b) (0x00000800 + (a)*0x00000020 + (b)*0x00000004)
#define NV827C_SURFACE_SET_OFFSET_ORIGIN 31:0
#define NV827C_SURFACE_SET_SIZE(a) (0x00000808 + (a)*0x00000020)
#define NV827C_SURFACE_SET_SIZE_WIDTH 14:0
#define NV827C_SURFACE_SET_SIZE_HEIGHT 30:16
#define NV827C_SURFACE_SET_STORAGE(a) (0x0000080C + (a)*0x00000020)
#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0
#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000)
#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001)
#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002)
#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003)
#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004)
#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005)
#define NV827C_SURFACE_SET_STORAGE_PITCH 17:8
#define NV827C_SURFACE_SET_STORAGE_MEMORY_LAYOUT 20:20
#define NV827C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000)
#define NV827C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001)
#define NV827C_SURFACE_SET_PARAMS(a) (0x00000810 + (a)*0x00000020)
#define NV827C_SURFACE_SET_PARAMS_FORMAT 15:8
#define NV827C_SURFACE_SET_PARAMS_FORMAT_I8 (0x0000001E)
#define NV827C_SURFACE_SET_PARAMS_FORMAT_VOID16 (0x0000001F)
#define NV827C_SURFACE_SET_PARAMS_FORMAT_VOID32 (0x0000002E)
#define NV827C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA)
#define NV827C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF)
#define NV827C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1)
#define NV827C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5)
#define NV827C_SURFACE_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8)
#define NV827C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9)
#define NV827C_SURFACE_SET_PARAMS_SUPER_SAMPLE 1:0
#define NV827C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000)
#define NV827C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002)
#define NV827C_SURFACE_SET_PARAMS_GAMMA 2:2
#define NV827C_SURFACE_SET_PARAMS_GAMMA_LINEAR (0x00000000)
#define NV827C_SURFACE_SET_PARAMS_GAMMA_SRGB (0x00000001)
#define NV827C_SURFACE_SET_PARAMS_LAYOUT 5:4
#define NV827C_SURFACE_SET_PARAMS_LAYOUT_FRM (0x00000000)
#define NV827C_SURFACE_SET_PARAMS_LAYOUT_FLD1 (0x00000001)
#define NV827C_SURFACE_SET_PARAMS_LAYOUT_FLD2 (0x00000002)
#define NV827C_SURFACE_SET_PARAMS_RESERVED0 22:16
#define NV827C_SURFACE_SET_PARAMS_RESERVED1 24:24
#endif // _cl827c_h

73
drivers/gpu/drm/nouveau/include/nvhw/class/cl907e.h Normal file
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@ -0,0 +1,73 @@
/*
* Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl907e_h_
#define _cl907e_h_
// class methods
#define NV907E_SET_PRESENT_CONTROL (0x00000084)
#define NV907E_SET_PRESENT_CONTROL_BEGIN_MODE 1:0
#define NV907E_SET_PRESENT_CONTROL_BEGIN_MODE_ASAP (0x00000000)
#define NV907E_SET_PRESENT_CONTROL_BEGIN_MODE_TIMESTAMP (0x00000003)
#define NV907E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4
#define NV907E_SET_CONTEXT_DMA_ISO (0x000000C0)
#define NV907E_SET_CONTEXT_DMA_ISO_HANDLE 31:0
#define NV907E_SET_COMPOSITION_CONTROL (0x00000100)
#define NV907E_SET_COMPOSITION_CONTROL_MODE 3:0
#define NV907E_SET_COMPOSITION_CONTROL_MODE_SOURCE_COLOR_VALUE_KEYING (0x00000000)
#define NV907E_SET_COMPOSITION_CONTROL_MODE_DESTINATION_COLOR_VALUE_KEYING (0x00000001)
#define NV907E_SET_COMPOSITION_CONTROL_MODE_OPAQUE (0x00000002)
#define NV907E_SURFACE_SET_OFFSET (0x00000400)
#define NV907E_SURFACE_SET_OFFSET_ORIGIN 31:0
#define NV907E_SURFACE_SET_SIZE (0x00000408)
#define NV907E_SURFACE_SET_SIZE_WIDTH 15:0
#define NV907E_SURFACE_SET_SIZE_HEIGHT 31:16
#define NV907E_SURFACE_SET_STORAGE (0x0000040C)
#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0
#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000)
#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001)
#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002)
#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003)
#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004)
#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005)
#define NV907E_SURFACE_SET_STORAGE_PITCH 20:8
#define NV907E_SURFACE_SET_STORAGE_MEMORY_LAYOUT 24:24
#define NV907E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000)
#define NV907E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001)
#define NV907E_SURFACE_SET_PARAMS (0x00000410)
#define NV907E_SURFACE_SET_PARAMS_FORMAT 15:8
#define NV907E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8 (0x00000028)
#define NV907E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8 (0x00000029)
#define NV907E_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1)
#define NV907E_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022)
#define NV907E_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF)
#define NV907E_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9)
#define NV907E_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA)
#define NV907E_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6)
#define NV907E_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023)
#define NV907E_SURFACE_SET_PARAMS_COLOR_SPACE 1:0
#define NV907E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB (0x00000000)
#define NV907E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601 (0x00000001)
#define NV907E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_709 (0x00000002)
#endif // _cl907e_h