drm/amd/powerplay: add Vega10 powerplay support (v5)
Adds power management support for vega10. v2: squash in fan control and led config fixes from Rex v3: squash in dead code removal and socvid fixes from Rex v4: squash in dpm force level fix from Rex v5: squash in latest headless, gpu load fixes from Rex Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Eric Huang
Alex Deucher
parent
d018772748
commit
f83a999164
|
|
@ -71,6 +71,7 @@ static int amdgpu_pp_early_init(void *handle)
|
||||||
case CHIP_TOPAZ:
|
case CHIP_TOPAZ:
|
||||||
case CHIP_CARRIZO:
|
case CHIP_CARRIZO:
|
||||||
case CHIP_STONEY:
|
case CHIP_STONEY:
|
||||||
|
case CHIP_VEGA10:
|
||||||
adev->pp_enabled = true;
|
adev->pp_enabled = true;
|
||||||
if (amdgpu_create_pp_handle(adev))
|
if (amdgpu_create_pp_handle(adev))
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
|
||||||
|
|
@ -7,7 +7,9 @@ HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
|
||||||
cz_clockpowergating.o pppcielanes.o\
|
cz_clockpowergating.o pppcielanes.o\
|
||||||
process_pptables_v1_0.o ppatomctrl.o ppatomfwctrl.o \
|
process_pptables_v1_0.o ppatomctrl.o ppatomfwctrl.o \
|
||||||
smu7_hwmgr.o smu7_powertune.o smu7_thermal.o \
|
smu7_hwmgr.o smu7_powertune.o smu7_thermal.o \
|
||||||
smu7_clockpowergating.o
|
smu7_clockpowergating.o \
|
||||||
|
vega10_processpptables.o vega10_hwmgr.o vega10_powertune.o \
|
||||||
|
vega10_thermal.o
|
||||||
|
|
||||||
|
|
||||||
AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
|
AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
|
||||||
|
|
|
||||||
|
|
@ -106,6 +106,15 @@ int hwmgr_early_init(struct pp_instance *handle)
|
||||||
}
|
}
|
||||||
smu7_init_function_pointers(hwmgr);
|
smu7_init_function_pointers(hwmgr);
|
||||||
break;
|
break;
|
||||||
|
case AMDGPU_FAMILY_AI:
|
||||||
|
switch (hwmgr->chip_id) {
|
||||||
|
case CHIP_VEGA10:
|
||||||
|
vega10_hwmgr_init(hwmgr);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
break;
|
||||||
default:
|
default:
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,434 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2016 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
|
* copy of this software and associated documentation files (the "Software"),
|
||||||
|
* to deal in the Software without restriction, including without limitation
|
||||||
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||||
|
* and/or sell copies of the Software, and to permit persons to whom the
|
||||||
|
* Software is furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
|
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||||
|
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||||
|
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||||
|
* OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _VEGA10_HWMGR_H_
|
||||||
|
#define _VEGA10_HWMGR_H_
|
||||||
|
|
||||||
|
#include "hwmgr.h"
|
||||||
|
#include "smu9_driver_if.h"
|
||||||
|
#include "ppatomctrl.h"
|
||||||
|
#include "ppatomfwctrl.h"
|
||||||
|
#include "vega10_ppsmc.h"
|
||||||
|
#include "vega10_powertune.h"
|
||||||
|
|
||||||
|
extern const uint32_t PhwVega10_Magic;
|
||||||
|
#define VEGA10_MAX_HARDWARE_POWERLEVELS 2
|
||||||
|
|
||||||
|
#define WaterMarksExist 1
|
||||||
|
#define WaterMarksLoaded 2
|
||||||
|
|
||||||
|
enum {
|
||||||
|
GNLD_DPM_PREFETCHER = 0,
|
||||||
|
GNLD_DPM_GFXCLK,
|
||||||
|
GNLD_DPM_UCLK,
|
||||||
|
GNLD_DPM_SOCCLK,
|
||||||
|
GNLD_DPM_UVD,
|
||||||
|
GNLD_DPM_VCE,
|
||||||
|
GNLD_ULV,
|
||||||
|
GNLD_DPM_MP0CLK,
|
||||||
|
GNLD_DPM_LINK,
|
||||||
|
GNLD_DPM_DCEFCLK,
|
||||||
|
GNLD_AVFS,
|
||||||
|
GNLD_DS_GFXCLK,
|
||||||
|
GNLD_DS_SOCCLK,
|
||||||
|
GNLD_DS_LCLK,
|
||||||
|
GNLD_PPT,
|
||||||
|
GNLD_TDC,
|
||||||
|
GNLD_THERMAL,
|
||||||
|
GNLD_GFX_PER_CU_CG,
|
||||||
|
GNLD_RM,
|
||||||
|
GNLD_DS_DCEFCLK,
|
||||||
|
GNLD_ACDC,
|
||||||
|
GNLD_VR0HOT,
|
||||||
|
GNLD_VR1HOT,
|
||||||
|
GNLD_FW_CTF,
|
||||||
|
GNLD_LED_DISPLAY,
|
||||||
|
GNLD_FAN_CONTROL,
|
||||||
|
GNLD_VOLTAGE_CONTROLLER,
|
||||||
|
GNLD_FEATURES_MAX
|
||||||
|
};
|
||||||
|
|
||||||
|
#define GNLD_DPM_MAX (GNLD_DPM_DCEFCLK + 1)
|
||||||
|
|
||||||
|
#define SMC_DPM_FEATURES 0x30F
|
||||||
|
|
||||||
|
struct smu_features {
|
||||||
|
bool supported;
|
||||||
|
bool enabled;
|
||||||
|
uint32_t smu_feature_id;
|
||||||
|
uint32_t smu_feature_bitmap;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct vega10_performance_level {
|
||||||
|
uint32_t soc_clock;
|
||||||
|
uint32_t gfx_clock;
|
||||||
|
uint32_t mem_clock;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct vega10_bacos {
|
||||||
|
uint32_t baco_flags;
|
||||||
|
/* struct vega10_performance_level performance_level; */
|
||||||
|
};
|
||||||
|
|
||||||
|
struct vega10_uvd_clocks {
|
||||||
|
uint32_t vclk;
|
||||||
|
uint32_t dclk;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct vega10_vce_clocks {
|
||||||
|
uint32_t evclk;
|
||||||
|
uint32_t ecclk;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct vega10_power_state {
|
||||||
|
uint32_t magic;
|
||||||
|
struct vega10_uvd_clocks uvd_clks;
|
||||||
|
struct vega10_vce_clocks vce_clks;
|
||||||
|
uint16_t performance_level_count;
|
||||||
|
bool dc_compatible;
|
||||||
|
uint32_t sclk_threshold;
|
||||||
|
struct vega10_performance_level performance_levels[VEGA10_MAX_HARDWARE_POWERLEVELS];
|
||||||
|
};
|
||||||
|
|
||||||
|
struct vega10_dpm_level {
|
||||||
|
bool enabled;
|
||||||
|
uint32_t value;
|
||||||
|
uint32_t param1;
|
||||||
|
};
|
||||||
|
|
||||||
|
#define VEGA10_MAX_DEEPSLEEP_DIVIDER_ID 5
|
||||||
|
#define MAX_REGULAR_DPM_NUMBER 8
|
||||||
|
#define MAX_PCIE_CONF 2
|
||||||
|
#define VEGA10_MINIMUM_ENGINE_CLOCK 2500
|
||||||
|
|
||||||
|
struct vega10_dpm_state {
|
||||||
|
uint32_t soft_min_level;
|
||||||
|
uint32_t soft_max_level;
|
||||||
|
uint32_t hard_min_level;
|
||||||
|
uint32_t hard_max_level;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct vega10_single_dpm_table {
|
||||||
|
uint32_t count;
|
||||||
|
struct vega10_dpm_state dpm_state;
|
||||||
|
struct vega10_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
|
||||||
|
};
|
||||||
|
|
||||||
|
struct vega10_pcie_table {
|
||||||
|
uint16_t count;
|
||||||
|
uint8_t pcie_gen[MAX_PCIE_CONF];
|
||||||
|
uint8_t pcie_lane[MAX_PCIE_CONF];
|
||||||
|
uint32_t lclk[MAX_PCIE_CONF];
|
||||||
|
};
|
||||||
|
|
||||||
|
struct vega10_dpm_table {
|
||||||
|
struct vega10_single_dpm_table soc_table;
|
||||||
|
struct vega10_single_dpm_table gfx_table;
|
||||||
|
struct vega10_single_dpm_table mem_table;
|
||||||
|
struct vega10_single_dpm_table eclk_table;
|
||||||
|
struct vega10_single_dpm_table vclk_table;
|
||||||
|
struct vega10_single_dpm_table dclk_table;
|
||||||
|
struct vega10_single_dpm_table dcef_table;
|
||||||
|
struct vega10_single_dpm_table pixel_table;
|
||||||
|
struct vega10_single_dpm_table display_table;
|
||||||
|
struct vega10_single_dpm_table phy_table;
|
||||||
|
struct vega10_pcie_table pcie_table;
|
||||||
|
};
|
||||||
|
|
||||||
|
#define VEGA10_MAX_LEAKAGE_COUNT 8
|
||||||
|
struct vega10_leakage_voltage {
|
||||||
|
uint16_t count;
|
||||||
|
uint16_t leakage_id[VEGA10_MAX_LEAKAGE_COUNT];
|
||||||
|
uint16_t actual_voltage[VEGA10_MAX_LEAKAGE_COUNT];
|
||||||
|
};
|
||||||
|
|
||||||
|
struct vega10_display_timing {
|
||||||
|
uint32_t min_clock_in_sr;
|
||||||
|
uint32_t num_existing_displays;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct vega10_dpmlevel_enable_mask {
|
||||||
|
uint32_t uvd_dpm_enable_mask;
|
||||||
|
uint32_t vce_dpm_enable_mask;
|
||||||
|
uint32_t acp_dpm_enable_mask;
|
||||||
|
uint32_t samu_dpm_enable_mask;
|
||||||
|
uint32_t sclk_dpm_enable_mask;
|
||||||
|
uint32_t mclk_dpm_enable_mask;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct vega10_vbios_boot_state {
|
||||||
|
uint16_t vddc;
|
||||||
|
uint16_t vddci;
|
||||||
|
uint32_t gfx_clock;
|
||||||
|
uint32_t mem_clock;
|
||||||
|
uint32_t soc_clock;
|
||||||
|
};
|
||||||
|
|
||||||
|
#define DPMTABLE_OD_UPDATE_SCLK 0x00000001
|
||||||
|
#define DPMTABLE_OD_UPDATE_MCLK 0x00000002
|
||||||
|
#define DPMTABLE_UPDATE_SCLK 0x00000004
|
||||||
|
#define DPMTABLE_UPDATE_MCLK 0x00000008
|
||||||
|
#define DPMTABLE_OD_UPDATE_VDDC 0x00000010
|
||||||
|
|
||||||
|
struct vega10_smc_state_table {
|
||||||
|
uint32_t soc_boot_level;
|
||||||
|
uint32_t gfx_boot_level;
|
||||||
|
uint32_t dcef_boot_level;
|
||||||
|
uint32_t mem_boot_level;
|
||||||
|
uint32_t uvd_boot_level;
|
||||||
|
uint32_t vce_boot_level;
|
||||||
|
uint32_t gfx_max_level;
|
||||||
|
uint32_t mem_max_level;
|
||||||
|
uint8_t vr_hot_gpio;
|
||||||
|
uint8_t ac_dc_gpio;
|
||||||
|
uint8_t therm_out_gpio;
|
||||||
|
uint8_t therm_out_polarity;
|
||||||
|
uint8_t therm_out_mode;
|
||||||
|
PPTable_t pp_table;
|
||||||
|
Watermarks_t water_marks_table;
|
||||||
|
AvfsTable_t avfs_table;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct vega10_mclk_latency_entries {
|
||||||
|
uint32_t frequency;
|
||||||
|
uint32_t latency;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct vega10_mclk_latency_table {
|
||||||
|
uint32_t count;
|
||||||
|
struct vega10_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER];
|
||||||
|
};
|
||||||
|
|
||||||
|
struct vega10_registry_data {
|
||||||
|
uint8_t ac_dc_switch_gpio_support;
|
||||||
|
uint8_t avfs_support;
|
||||||
|
uint8_t cac_support;
|
||||||
|
uint8_t clock_stretcher_support;
|
||||||
|
uint8_t db_ramping_support;
|
||||||
|
uint8_t didt_support;
|
||||||
|
uint8_t dynamic_state_patching_support;
|
||||||
|
uint8_t enable_pkg_pwr_tracking_feature;
|
||||||
|
uint8_t enable_tdc_limit_feature;
|
||||||
|
uint32_t fast_watermark_threshold;
|
||||||
|
uint8_t force_dpm_high;
|
||||||
|
uint8_t fuzzy_fan_control_support;
|
||||||
|
uint8_t long_idle_baco_support;
|
||||||
|
uint8_t mclk_dpm_key_disabled;
|
||||||
|
uint8_t od_state_in_dc_support;
|
||||||
|
uint8_t pcieLaneOverride;
|
||||||
|
uint8_t pcieSpeedOverride;
|
||||||
|
uint32_t pcieClockOverride;
|
||||||
|
uint8_t pcie_dpm_key_disabled;
|
||||||
|
uint8_t dcefclk_dpm_key_disabled;
|
||||||
|
uint8_t power_containment_support;
|
||||||
|
uint8_t ppt_support;
|
||||||
|
uint8_t prefetcher_dpm_key_disabled;
|
||||||
|
uint8_t quick_transition_support;
|
||||||
|
uint8_t regulator_hot_gpio_support;
|
||||||
|
uint8_t sclk_deep_sleep_support;
|
||||||
|
uint8_t sclk_dpm_key_disabled;
|
||||||
|
uint8_t sclk_from_vbios;
|
||||||
|
uint8_t sclk_throttle_low_notification;
|
||||||
|
uint8_t show_baco_dbg_info;
|
||||||
|
uint8_t skip_baco_hardware;
|
||||||
|
uint8_t socclk_dpm_key_disabled;
|
||||||
|
uint8_t spll_shutdown_support;
|
||||||
|
uint8_t sq_ramping_support;
|
||||||
|
uint32_t stable_pstate_sclk_dpm_percentage;
|
||||||
|
uint8_t tcp_ramping_support;
|
||||||
|
uint8_t tdc_support;
|
||||||
|
uint8_t td_ramping_support;
|
||||||
|
uint8_t thermal_out_gpio_support;
|
||||||
|
uint8_t thermal_support;
|
||||||
|
uint8_t fw_ctf_enabled;
|
||||||
|
uint8_t fan_control_support;
|
||||||
|
uint8_t ulps_support;
|
||||||
|
uint8_t ulv_support;
|
||||||
|
uint32_t vddc_vddci_delta;
|
||||||
|
uint8_t odn_feature_enable;
|
||||||
|
uint8_t disable_water_mark;
|
||||||
|
uint8_t zrpm_stop_temp;
|
||||||
|
uint8_t zrpm_start_temp;
|
||||||
|
uint8_t led_dpm_enabled;
|
||||||
|
uint8_t vr0hot_enabled;
|
||||||
|
uint8_t vr1hot_enabled;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct vega10_odn_clock_voltage_dependency_table {
|
||||||
|
uint32_t count;
|
||||||
|
struct phm_ppt_v1_clock_voltage_dependency_record
|
||||||
|
entries[MAX_REGULAR_DPM_NUMBER];
|
||||||
|
};
|
||||||
|
|
||||||
|
struct vega10_odn_dpm_table {
|
||||||
|
struct phm_odn_clock_levels odn_core_clock_dpm_levels;
|
||||||
|
struct phm_odn_clock_levels odn_memory_clock_dpm_levels;
|
||||||
|
struct vega10_odn_clock_voltage_dependency_table vdd_dependency_on_sclk;
|
||||||
|
struct vega10_odn_clock_voltage_dependency_table vdd_dependency_on_mclk;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct vega10_odn_fan_table {
|
||||||
|
uint32_t target_fan_speed;
|
||||||
|
uint32_t target_temperature;
|
||||||
|
uint32_t min_performance_clock;
|
||||||
|
uint32_t min_fan_limit;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct vega10_hwmgr {
|
||||||
|
struct vega10_dpm_table dpm_table;
|
||||||
|
struct vega10_dpm_table golden_dpm_table;
|
||||||
|
struct vega10_registry_data registry_data;
|
||||||
|
struct vega10_vbios_boot_state vbios_boot_state;
|
||||||
|
struct vega10_mclk_latency_table mclk_latency_table;
|
||||||
|
|
||||||
|
struct vega10_leakage_voltage vddc_leakage;
|
||||||
|
|
||||||
|
uint32_t vddc_control;
|
||||||
|
struct pp_atomfwctrl_voltage_table vddc_voltage_table;
|
||||||
|
uint32_t mvdd_control;
|
||||||
|
struct pp_atomfwctrl_voltage_table mvdd_voltage_table;
|
||||||
|
uint32_t vddci_control;
|
||||||
|
struct pp_atomfwctrl_voltage_table vddci_voltage_table;
|
||||||
|
|
||||||
|
uint32_t active_auto_throttle_sources;
|
||||||
|
uint32_t water_marks_bitmap;
|
||||||
|
struct vega10_bacos bacos;
|
||||||
|
|
||||||
|
struct vega10_odn_dpm_table odn_dpm_table;
|
||||||
|
struct vega10_odn_fan_table odn_fan_table;
|
||||||
|
|
||||||
|
/* ---- General data ---- */
|
||||||
|
uint8_t need_update_dpm_table;
|
||||||
|
|
||||||
|
bool cac_enabled;
|
||||||
|
bool battery_state;
|
||||||
|
bool is_tlu_enabled;
|
||||||
|
|
||||||
|
uint32_t low_sclk_interrupt_threshold;
|
||||||
|
|
||||||
|
uint32_t total_active_cus;
|
||||||
|
|
||||||
|
struct vega10_display_timing display_timing;
|
||||||
|
|
||||||
|
/* ---- Vega10 Dyn Register Settings ---- */
|
||||||
|
|
||||||
|
uint32_t debug_settings;
|
||||||
|
uint32_t lowest_uclk_reserved_for_ulv;
|
||||||
|
uint32_t gfxclk_average_alpha;
|
||||||
|
uint32_t socclk_average_alpha;
|
||||||
|
uint32_t uclk_average_alpha;
|
||||||
|
uint32_t gfx_activity_average_alpha;
|
||||||
|
uint32_t display_voltage_mode;
|
||||||
|
uint32_t dcef_clk_quad_eqn_a;
|
||||||
|
uint32_t dcef_clk_quad_eqn_b;
|
||||||
|
uint32_t dcef_clk_quad_eqn_c;
|
||||||
|
uint32_t disp_clk_quad_eqn_a;
|
||||||
|
uint32_t disp_clk_quad_eqn_b;
|
||||||
|
uint32_t disp_clk_quad_eqn_c;
|
||||||
|
uint32_t pixel_clk_quad_eqn_a;
|
||||||
|
uint32_t pixel_clk_quad_eqn_b;
|
||||||
|
uint32_t pixel_clk_quad_eqn_c;
|
||||||
|
uint32_t phy_clk_quad_eqn_a;
|
||||||
|
uint32_t phy_clk_quad_eqn_b;
|
||||||
|
uint32_t phy_clk_quad_eqn_c;
|
||||||
|
|
||||||
|
/* ---- Thermal Temperature Setting ---- */
|
||||||
|
struct vega10_dpmlevel_enable_mask dpm_level_enable_mask;
|
||||||
|
|
||||||
|
/* ---- Power Gating States ---- */
|
||||||
|
bool uvd_power_gated;
|
||||||
|
bool vce_power_gated;
|
||||||
|
bool samu_power_gated;
|
||||||
|
bool need_long_memory_training;
|
||||||
|
|
||||||
|
/* Internal settings to apply the application power optimization parameters */
|
||||||
|
bool apply_optimized_settings;
|
||||||
|
uint32_t disable_dpm_mask;
|
||||||
|
|
||||||
|
/* ---- Overdrive next setting ---- */
|
||||||
|
uint32_t apply_overdrive_next_settings_mask;
|
||||||
|
|
||||||
|
/* ---- Workload Mask ---- */
|
||||||
|
uint32_t workload_mask;
|
||||||
|
|
||||||
|
/* ---- SMU9 ---- */
|
||||||
|
struct smu_features smu_features[GNLD_FEATURES_MAX];
|
||||||
|
struct vega10_smc_state_table smc_state_table;
|
||||||
|
|
||||||
|
uint32_t config_telemetry;
|
||||||
|
};
|
||||||
|
|
||||||
|
#define VEGA10_DPM2_NEAR_TDP_DEC 10
|
||||||
|
#define VEGA10_DPM2_ABOVE_SAFE_INC 5
|
||||||
|
#define VEGA10_DPM2_BELOW_SAFE_INC 20
|
||||||
|
|
||||||
|
#define VEGA10_DPM2_LTA_WINDOW_SIZE 7
|
||||||
|
|
||||||
|
#define VEGA10_DPM2_LTS_TRUNCATE 0
|
||||||
|
|
||||||
|
#define VEGA10_DPM2_TDP_SAFE_LIMIT_PERCENT 80
|
||||||
|
|
||||||
|
#define VEGA10_DPM2_MAXPS_PERCENT_M 90
|
||||||
|
#define VEGA10_DPM2_MAXPS_PERCENT_H 90
|
||||||
|
|
||||||
|
#define VEGA10_DPM2_PWREFFICIENCYRATIO_MARGIN 50
|
||||||
|
|
||||||
|
#define VEGA10_DPM2_SQ_RAMP_MAX_POWER 0x3FFF
|
||||||
|
#define VEGA10_DPM2_SQ_RAMP_MIN_POWER 0x12
|
||||||
|
#define VEGA10_DPM2_SQ_RAMP_MAX_POWER_DELTA 0x15
|
||||||
|
#define VEGA10_DPM2_SQ_RAMP_SHORT_TERM_INTERVAL_SIZE 0x1E
|
||||||
|
#define VEGA10_DPM2_SQ_RAMP_LONG_TERM_INTERVAL_RATIO 0xF
|
||||||
|
|
||||||
|
#define VEGA10_VOLTAGE_CONTROL_NONE 0x0
|
||||||
|
#define VEGA10_VOLTAGE_CONTROL_BY_GPIO 0x1
|
||||||
|
#define VEGA10_VOLTAGE_CONTROL_BY_SVID2 0x2
|
||||||
|
#define VEGA10_VOLTAGE_CONTROL_MERGED 0x3
|
||||||
|
/* To convert to Q8.8 format for firmware */
|
||||||
|
#define VEGA10_Q88_FORMAT_CONVERSION_UNIT 256
|
||||||
|
|
||||||
|
#define VEGA10_UNUSED_GPIO_PIN 0x7F
|
||||||
|
|
||||||
|
#define VEGA10_THERM_OUT_MODE_DISABLE 0x0
|
||||||
|
#define VEGA10_THERM_OUT_MODE_THERM_ONLY 0x1
|
||||||
|
#define VEGA10_THERM_OUT_MODE_THERM_VRHOT 0x2
|
||||||
|
|
||||||
|
#define PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT 0xffffffff
|
||||||
|
#define PPREGKEY_VEGA10QUADRATICEQUATION_DFLT 0xffffffff
|
||||||
|
|
||||||
|
#define PPVEGA10_VEGA10GFXCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */
|
||||||
|
#define PPVEGA10_VEGA10SOCCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */
|
||||||
|
#define PPVEGA10_VEGA10UCLKCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */
|
||||||
|
#define PPVEGA10_VEGA10GFXACTIVITYAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */
|
||||||
|
|
||||||
|
extern int tonga_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
|
||||||
|
extern int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr);
|
||||||
|
extern int tonga_get_mc_microcode_version (struct pp_hwmgr *hwmgr);
|
||||||
|
extern int tonga_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr);
|
||||||
|
extern int tonga_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display);
|
||||||
|
int vega10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input);
|
||||||
|
int vega10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate);
|
||||||
|
int vega10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate);
|
||||||
|
int vega10_update_acp_dpm(struct pp_hwmgr *hwmgr, bool bgate);
|
||||||
|
int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
|
||||||
|
|
||||||
|
#endif /* _VEGA10_HWMGR_H_ */
|
||||||
|
|
@ -0,0 +1,44 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2016 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
|
* copy of this software and associated documentation files (the "Software"),
|
||||||
|
* to deal in the Software without restriction, including without limitation
|
||||||
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||||
|
* and/or sell copies of the Software, and to permit persons to whom the
|
||||||
|
* Software is furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
|
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||||
|
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||||
|
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||||
|
* OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef VEGA10_INC_H
|
||||||
|
#define VEGA10_INC_H
|
||||||
|
|
||||||
|
#include "asic_reg/vega10/THM/thm_9_0_default.h"
|
||||||
|
#include "asic_reg/vega10/THM/thm_9_0_offset.h"
|
||||||
|
#include "asic_reg/vega10/THM/thm_9_0_sh_mask.h"
|
||||||
|
|
||||||
|
#include "asic_reg/vega10/MP/mp_9_0_default.h"
|
||||||
|
#include "asic_reg/vega10/MP/mp_9_0_offset.h"
|
||||||
|
#include "asic_reg/vega10/MP/mp_9_0_sh_mask.h"
|
||||||
|
|
||||||
|
#include "asic_reg/vega10/GC/gc_9_0_default.h"
|
||||||
|
#include "asic_reg/vega10/GC/gc_9_0_offset.h"
|
||||||
|
#include "asic_reg/vega10/GC/gc_9_0_sh_mask.h"
|
||||||
|
|
||||||
|
#include "asic_reg/vega10/NBIO/nbio_6_1_default.h"
|
||||||
|
#include "asic_reg/vega10/NBIO/nbio_6_1_offset.h"
|
||||||
|
#include "asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,137 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2016 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
|
* copy of this software and associated documentation files (the "Software"),
|
||||||
|
* to deal in the Software without restriction, including without limitation
|
||||||
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||||
|
* and/or sell copies of the Software, and to permit persons to whom the
|
||||||
|
* Software is furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
|
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||||
|
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||||
|
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||||
|
* OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "hwmgr.h"
|
||||||
|
#include "vega10_hwmgr.h"
|
||||||
|
#include "vega10_powertune.h"
|
||||||
|
#include "vega10_smumgr.h"
|
||||||
|
#include "vega10_ppsmc.h"
|
||||||
|
#include "pp_debug.h"
|
||||||
|
|
||||||
|
void vega10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
|
||||||
|
{
|
||||||
|
struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
|
||||||
|
struct phm_ppt_v2_information *table_info =
|
||||||
|
(struct phm_ppt_v2_information *)(hwmgr->pptable);
|
||||||
|
struct phm_tdp_table *tdp_table = table_info->tdp_table;
|
||||||
|
PPTable_t *table = &(data->smc_state_table.pp_table);
|
||||||
|
|
||||||
|
table->SocketPowerLimit = cpu_to_le16(
|
||||||
|
tdp_table->usMaximumPowerDeliveryLimit);
|
||||||
|
table->TdcLimit = cpu_to_le16(tdp_table->usTDC);
|
||||||
|
table->EdcLimit = cpu_to_le16(tdp_table->usEDCLimit);
|
||||||
|
table->TedgeLimit = cpu_to_le16(tdp_table->usTemperatureLimitTedge);
|
||||||
|
table->ThotspotLimit = cpu_to_le16(tdp_table->usTemperatureLimitHotspot);
|
||||||
|
table->ThbmLimit = cpu_to_le16(tdp_table->usTemperatureLimitHBM);
|
||||||
|
table->Tvr_socLimit = cpu_to_le16(tdp_table->usTemperatureLimitVrVddc);
|
||||||
|
table->Tvr_memLimit = cpu_to_le16(tdp_table->usTemperatureLimitVrMvdd);
|
||||||
|
table->Tliquid1Limit = cpu_to_le16(tdp_table->usTemperatureLimitLiquid1);
|
||||||
|
table->Tliquid2Limit = cpu_to_le16(tdp_table->usTemperatureLimitLiquid2);
|
||||||
|
table->TplxLimit = cpu_to_le16(tdp_table->usTemperatureLimitPlx);
|
||||||
|
table->LoadLineResistance = cpu_to_le16(
|
||||||
|
hwmgr->platform_descriptor.LoadLineSlope);
|
||||||
|
table->FitLimit = 0; /* Not used for Vega10 */
|
||||||
|
|
||||||
|
table->Liquid1_I2C_address = tdp_table->ucLiquid1_I2C_address;
|
||||||
|
table->Liquid2_I2C_address = tdp_table->ucLiquid2_I2C_address;
|
||||||
|
table->Vr_I2C_address = tdp_table->ucVr_I2C_address;
|
||||||
|
table->Plx_I2C_address = tdp_table->ucPlx_I2C_address;
|
||||||
|
|
||||||
|
table->Liquid_I2C_LineSCL = tdp_table->ucLiquid_I2C_Line;
|
||||||
|
table->Liquid_I2C_LineSDA = tdp_table->ucLiquid_I2C_LineSDA;
|
||||||
|
|
||||||
|
table->Vr_I2C_LineSCL = tdp_table->ucVr_I2C_Line;
|
||||||
|
table->Vr_I2C_LineSDA = tdp_table->ucVr_I2C_LineSDA;
|
||||||
|
|
||||||
|
table->Plx_I2C_LineSCL = tdp_table->ucPlx_I2C_Line;
|
||||||
|
table->Plx_I2C_LineSDA = tdp_table->ucPlx_I2C_LineSDA;
|
||||||
|
}
|
||||||
|
|
||||||
|
int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
|
||||||
|
{
|
||||||
|
struct vega10_hwmgr *data =
|
||||||
|
(struct vega10_hwmgr *)(hwmgr->backend);
|
||||||
|
|
||||||
|
if (data->registry_data.enable_pkg_pwr_tracking_feature)
|
||||||
|
return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
|
||||||
|
PPSMC_MSG_SetPptLimit, n);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int vega10_enable_power_containment(struct pp_hwmgr *hwmgr)
|
||||||
|
{
|
||||||
|
struct vega10_hwmgr *data =
|
||||||
|
(struct vega10_hwmgr *)(hwmgr->backend);
|
||||||
|
struct phm_ppt_v2_information *table_info =
|
||||||
|
(struct phm_ppt_v2_information *)(hwmgr->pptable);
|
||||||
|
struct phm_tdp_table *tdp_table = table_info->tdp_table;
|
||||||
|
uint32_t default_pwr_limit =
|
||||||
|
(uint32_t)(tdp_table->usMaximumPowerDeliveryLimit);
|
||||||
|
int result = 0;
|
||||||
|
|
||||||
|
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
|
||||||
|
PHM_PlatformCaps_PowerContainment)) {
|
||||||
|
if (data->smu_features[GNLD_PPT].supported)
|
||||||
|
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
|
||||||
|
true, data->smu_features[GNLD_PPT].smu_feature_bitmap),
|
||||||
|
"Attempt to enable PPT feature Failed!",
|
||||||
|
data->smu_features[GNLD_PPT].supported = false);
|
||||||
|
|
||||||
|
if (data->smu_features[GNLD_TDC].supported)
|
||||||
|
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
|
||||||
|
true, data->smu_features[GNLD_TDC].smu_feature_bitmap),
|
||||||
|
"Attempt to enable PPT feature Failed!",
|
||||||
|
data->smu_features[GNLD_TDC].supported = false);
|
||||||
|
|
||||||
|
result = vega10_set_power_limit(hwmgr, default_pwr_limit);
|
||||||
|
PP_ASSERT_WITH_CODE(!result,
|
||||||
|
"Failed to set Default Power Limit in SMC!",
|
||||||
|
return result);
|
||||||
|
}
|
||||||
|
|
||||||
|
return result;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int vega10_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr,
|
||||||
|
uint32_t adjust_percent)
|
||||||
|
{
|
||||||
|
return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
|
||||||
|
PPSMC_MSG_OverDriveSetPercentage, adjust_percent);
|
||||||
|
}
|
||||||
|
|
||||||
|
int vega10_power_control_set_level(struct pp_hwmgr *hwmgr)
|
||||||
|
{
|
||||||
|
int adjust_percent, result = 0;
|
||||||
|
|
||||||
|
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
|
||||||
|
PHM_PlatformCaps_PowerContainment)) {
|
||||||
|
adjust_percent =
|
||||||
|
hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
|
||||||
|
hwmgr->platform_descriptor.TDPAdjustment :
|
||||||
|
(-1 * hwmgr->platform_descriptor.TDPAdjustment);
|
||||||
|
result = vega10_set_overdrive_target_percentage(hwmgr,
|
||||||
|
(uint32_t)adjust_percent);
|
||||||
|
}
|
||||||
|
return result;
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,65 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2016 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
|
* copy of this software and associated documentation files (the "Software"),
|
||||||
|
* to deal in the Software without restriction, including without limitation
|
||||||
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||||
|
* and/or sell copies of the Software, and to permit persons to whom the
|
||||||
|
* Software is furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
|
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||||
|
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||||
|
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||||
|
* OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#ifndef _VEGA10_POWERTUNE_H_
|
||||||
|
#define _VEGA10_POWERTUNE_H_
|
||||||
|
|
||||||
|
enum vega10_pt_config_reg_type {
|
||||||
|
VEGA10_CONFIGREG_MMR = 0,
|
||||||
|
VEGA10_CONFIGREG_SMC_IND,
|
||||||
|
VEGA10_CONFIGREG_DIDT_IND,
|
||||||
|
VEGA10_CONFIGREG_CACHE,
|
||||||
|
VEGA10_CONFIGREG_MAX
|
||||||
|
};
|
||||||
|
|
||||||
|
/* PowerContainment Features */
|
||||||
|
#define POWERCONTAINMENT_FEATURE_DTE 0x00000001
|
||||||
|
#define POWERCONTAINMENT_FEATURE_TDCLimit 0x00000002
|
||||||
|
#define POWERCONTAINMENT_FEATURE_PkgPwrLimit 0x00000004
|
||||||
|
|
||||||
|
struct vega10_pt_config_reg {
|
||||||
|
uint32_t offset;
|
||||||
|
uint32_t mask;
|
||||||
|
uint32_t shift;
|
||||||
|
uint32_t value;
|
||||||
|
enum vega10_pt_config_reg_type type;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct vega10_pt_defaults {
|
||||||
|
uint8_t SviLoadLineEn;
|
||||||
|
uint8_t SviLoadLineVddC;
|
||||||
|
uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
|
||||||
|
uint8_t TDC_MAWt;
|
||||||
|
uint8_t TdcWaterfallCtl;
|
||||||
|
uint8_t DTEAmbientTempBase;
|
||||||
|
};
|
||||||
|
|
||||||
|
void vega10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr);
|
||||||
|
int vega10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr);
|
||||||
|
int vega10_populate_pm_fuses(struct pp_hwmgr *hwmgr);
|
||||||
|
int vega10_enable_smc_cac(struct pp_hwmgr *hwmgr);
|
||||||
|
int vega10_enable_power_containment(struct pp_hwmgr *hwmgr);
|
||||||
|
int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);
|
||||||
|
int vega10_power_control_set_level(struct pp_hwmgr *hwmgr);
|
||||||
|
|
||||||
|
#endif /* _VEGA10_POWERTUNE_H_ */
|
||||||
|
|
||||||
|
|
@ -0,0 +1,331 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2016 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
|
* copy of this software and associated documentation files (the "Software"),
|
||||||
|
* to deal in the Software without restriction, including without limitation
|
||||||
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||||
|
* and/or sell copies of the Software, and to permit persons to whom the
|
||||||
|
* Software is furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
|
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||||
|
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||||
|
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||||
|
* OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#ifndef _VEGA10_PPTABLE_H_
|
||||||
|
#define _VEGA10_PPTABLE_H_
|
||||||
|
|
||||||
|
#pragma pack(push, 1)
|
||||||
|
|
||||||
|
#define ATOM_VEGA10_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK 0x0f
|
||||||
|
#define ATOM_VEGA10_PP_FANPARAMETERS_NOFAN 0x80
|
||||||
|
|
||||||
|
#define ATOM_VEGA10_PP_THERMALCONTROLLER_NONE 0
|
||||||
|
#define ATOM_VEGA10_PP_THERMALCONTROLLER_LM96163 17
|
||||||
|
#define ATOM_VEGA10_PP_THERMALCONTROLLER_VEGA10 24
|
||||||
|
|
||||||
|
#define ATOM_VEGA10_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL 0x89
|
||||||
|
#define ATOM_VEGA10_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL 0x8D
|
||||||
|
|
||||||
|
#define ATOM_VEGA10_PP_PLATFORM_CAP_POWERPLAY 0x1
|
||||||
|
#define ATOM_VEGA10_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 0x2
|
||||||
|
#define ATOM_VEGA10_PP_PLATFORM_CAP_HARDWAREDC 0x4
|
||||||
|
#define ATOM_VEGA10_PP_PLATFORM_CAP_BACO 0x8
|
||||||
|
#define ATOM_VEGA10_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL 0x10
|
||||||
|
|
||||||
|
|
||||||
|
/* ATOM_PPLIB_NONCLOCK_INFO::usClassification */
|
||||||
|
#define ATOM_PPLIB_CLASSIFICATION_UI_MASK 0x0007
|
||||||
|
#define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT 0
|
||||||
|
#define ATOM_PPLIB_CLASSIFICATION_UI_NONE 0
|
||||||
|
#define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1
|
||||||
|
#define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3
|
||||||
|
#define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5
|
||||||
|
/* 2, 4, 6, 7 are reserved */
|
||||||
|
|
||||||
|
#define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008
|
||||||
|
#define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010
|
||||||
|
#define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020
|
||||||
|
#define ATOM_PPLIB_CLASSIFICATION_REST 0x0040
|
||||||
|
#define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080
|
||||||
|
#define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000
|
||||||
|
|
||||||
|
/* ATOM_PPLIB_NONCLOCK_INFO::usClassification2 */
|
||||||
|
#define ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2 0x0001
|
||||||
|
|
||||||
|
#define ATOM_Vega10_DISALLOW_ON_DC 0x00004000
|
||||||
|
#define ATOM_Vega10_ENABLE_VARIBRIGHT 0x00008000
|
||||||
|
|
||||||
|
#define ATOM_Vega10_TABLE_REVISION_VEGA10 8
|
||||||
|
|
||||||
|
#define ATOM_Vega10_VoltageMode_AVFS_Interpolate 0
|
||||||
|
#define ATOM_Vega10_VoltageMode_AVFS_WorstCase 1
|
||||||
|
#define ATOM_Vega10_VoltageMode_Static 2
|
||||||
|
|
||||||
|
typedef struct _ATOM_Vega10_POWERPLAYTABLE {
|
||||||
|
struct atom_common_table_header sHeader;
|
||||||
|
UCHAR ucTableRevision;
|
||||||
|
USHORT usTableSize; /* the size of header structure */
|
||||||
|
ULONG ulGoldenPPID; /* PPGen use only */
|
||||||
|
ULONG ulGoldenRevision; /* PPGen use only */
|
||||||
|
USHORT usFormatID; /* PPGen use only */
|
||||||
|
ULONG ulPlatformCaps; /* See ATOM_Vega10_CAPS_* */
|
||||||
|
ULONG ulMaxODEngineClock; /* For Overdrive. */
|
||||||
|
ULONG ulMaxODMemoryClock; /* For Overdrive. */
|
||||||
|
USHORT usPowerControlLimit;
|
||||||
|
USHORT usUlvVoltageOffset; /* in mv units */
|
||||||
|
USHORT usUlvSmnclkDid;
|
||||||
|
USHORT usUlvMp1clkDid;
|
||||||
|
USHORT usUlvGfxclkBypass;
|
||||||
|
USHORT usGfxclkSlewRate;
|
||||||
|
UCHAR ucGfxVoltageMode;
|
||||||
|
UCHAR ucSocVoltageMode;
|
||||||
|
UCHAR ucUclkVoltageMode;
|
||||||
|
UCHAR ucUvdVoltageMode;
|
||||||
|
UCHAR ucVceVoltageMode;
|
||||||
|
UCHAR ucMp0VoltageMode;
|
||||||
|
UCHAR ucDcefVoltageMode;
|
||||||
|
USHORT usStateArrayOffset; /* points to ATOM_Vega10_State_Array */
|
||||||
|
USHORT usFanTableOffset; /* points to ATOM_Vega10_Fan_Table */
|
||||||
|
USHORT usThermalControllerOffset; /* points to ATOM_Vega10_Thermal_Controller */
|
||||||
|
USHORT usSocclkDependencyTableOffset; /* points to ATOM_Vega10_SOCCLK_Dependency_Table */
|
||||||
|
USHORT usMclkDependencyTableOffset; /* points to ATOM_Vega10_MCLK_Dependency_Table */
|
||||||
|
USHORT usGfxclkDependencyTableOffset; /* points to ATOM_Vega10_GFXCLK_Dependency_Table */
|
||||||
|
USHORT usDcefclkDependencyTableOffset; /* points to ATOM_Vega10_DCEFCLK_Dependency_Table */
|
||||||
|
USHORT usVddcLookupTableOffset; /* points to ATOM_Vega10_Voltage_Lookup_Table */
|
||||||
|
USHORT usVddmemLookupTableOffset; /* points to ATOM_Vega10_Voltage_Lookup_Table */
|
||||||
|
USHORT usMMDependencyTableOffset; /* points to ATOM_Vega10_MM_Dependency_Table */
|
||||||
|
USHORT usVCEStateTableOffset; /* points to ATOM_Vega10_VCE_State_Table */
|
||||||
|
USHORT usReserve; /* No PPM Support for Vega10 */
|
||||||
|
USHORT usPowerTuneTableOffset; /* points to ATOM_Vega10_PowerTune_Table */
|
||||||
|
USHORT usHardLimitTableOffset; /* points to ATOM_Vega10_Hard_Limit_Table */
|
||||||
|
USHORT usVddciLookupTableOffset; /* points to ATOM_Vega10_Voltage_Lookup_Table */
|
||||||
|
USHORT usPCIETableOffset; /* points to ATOM_Vega10_PCIE_Table */
|
||||||
|
USHORT usPixclkDependencyTableOffset; /* points to ATOM_Vega10_PIXCLK_Dependency_Table */
|
||||||
|
USHORT usDispClkDependencyTableOffset; /* points to ATOM_Vega10_DISPCLK_Dependency_Table */
|
||||||
|
USHORT usPhyClkDependencyTableOffset; /* points to ATOM_Vega10_PHYCLK_Dependency_Table */
|
||||||
|
} ATOM_Vega10_POWERPLAYTABLE;
|
||||||
|
|
||||||
|
typedef struct _ATOM_Vega10_State {
|
||||||
|
UCHAR ucSocClockIndexHigh;
|
||||||
|
UCHAR ucSocClockIndexLow;
|
||||||
|
UCHAR ucGfxClockIndexHigh;
|
||||||
|
UCHAR ucGfxClockIndexLow;
|
||||||
|
UCHAR ucMemClockIndexHigh;
|
||||||
|
UCHAR ucMemClockIndexLow;
|
||||||
|
USHORT usClassification;
|
||||||
|
ULONG ulCapsAndSettings;
|
||||||
|
USHORT usClassification2;
|
||||||
|
} ATOM_Vega10_State;
|
||||||
|
|
||||||
|
typedef struct _ATOM_Vega10_State_Array {
|
||||||
|
UCHAR ucRevId;
|
||||||
|
UCHAR ucNumEntries; /* Number of entries. */
|
||||||
|
ATOM_Vega10_State states[1]; /* Dynamically allocate entries. */
|
||||||
|
} ATOM_Vega10_State_Array;
|
||||||
|
|
||||||
|
typedef struct _ATOM_Vega10_CLK_Dependency_Record {
|
||||||
|
ULONG ulClk; /* Frequency of Clock */
|
||||||
|
UCHAR ucVddInd; /* Base voltage */
|
||||||
|
} ATOM_Vega10_CLK_Dependency_Record;
|
||||||
|
|
||||||
|
typedef struct _ATOM_Vega10_GFXCLK_Dependency_Record {
|
||||||
|
ULONG ulClk; /* Clock Frequency */
|
||||||
|
UCHAR ucVddInd; /* SOC_VDD index */
|
||||||
|
USHORT usCKSVOffsetandDisable; /* Bits 0~30: Voltage offset for CKS, Bit 31: Disable/enable for the GFXCLK level. */
|
||||||
|
USHORT usAVFSOffset; /* AVFS Voltage offset */
|
||||||
|
} ATOM_Vega10_GFXCLK_Dependency_Record;
|
||||||
|
|
||||||
|
typedef struct _ATOM_Vega10_MCLK_Dependency_Record {
|
||||||
|
ULONG ulMemClk; /* Clock Frequency */
|
||||||
|
UCHAR ucVddInd; /* SOC_VDD index */
|
||||||
|
UCHAR ucVddMemInd; /* MEM_VDD - only non zero for MCLK record */
|
||||||
|
UCHAR ucVddciInd; /* VDDCI = only non zero for MCLK record */
|
||||||
|
} ATOM_Vega10_MCLK_Dependency_Record;
|
||||||
|
|
||||||
|
typedef struct _ATOM_Vega10_GFXCLK_Dependency_Table {
|
||||||
|
UCHAR ucRevId;
|
||||||
|
UCHAR ucNumEntries; /* Number of entries. */
|
||||||
|
ATOM_Vega10_GFXCLK_Dependency_Record entries[1]; /* Dynamically allocate entries. */
|
||||||
|
} ATOM_Vega10_GFXCLK_Dependency_Table;
|
||||||
|
|
||||||
|
typedef struct _ATOM_Vega10_MCLK_Dependency_Table {
|
||||||
|
UCHAR ucRevId;
|
||||||
|
UCHAR ucNumEntries; /* Number of entries. */
|
||||||
|
ATOM_Vega10_MCLK_Dependency_Record entries[1]; /* Dynamically allocate entries. */
|
||||||
|
} ATOM_Vega10_MCLK_Dependency_Table;
|
||||||
|
|
||||||
|
typedef struct _ATOM_Vega10_SOCCLK_Dependency_Table {
|
||||||
|
UCHAR ucRevId;
|
||||||
|
UCHAR ucNumEntries; /* Number of entries. */
|
||||||
|
ATOM_Vega10_CLK_Dependency_Record entries[1]; /* Dynamically allocate entries. */
|
||||||
|
} ATOM_Vega10_SOCCLK_Dependency_Table;
|
||||||
|
|
||||||
|
typedef struct _ATOM_Vega10_DCEFCLK_Dependency_Table {
|
||||||
|
UCHAR ucRevId;
|
||||||
|
UCHAR ucNumEntries; /* Number of entries. */
|
||||||
|
ATOM_Vega10_CLK_Dependency_Record entries[1]; /* Dynamically allocate entries. */
|
||||||
|
} ATOM_Vega10_DCEFCLK_Dependency_Table;
|
||||||
|
|
||||||
|
typedef struct _ATOM_Vega10_PIXCLK_Dependency_Table {
|
||||||
|
UCHAR ucRevId;
|
||||||
|
UCHAR ucNumEntries; /* Number of entries. */
|
||||||
|
ATOM_Vega10_CLK_Dependency_Record entries[1]; /* Dynamically allocate entries. */
|
||||||
|
} ATOM_Vega10_PIXCLK_Dependency_Table;
|
||||||
|
|
||||||
|
typedef struct _ATOM_Vega10_DISPCLK_Dependency_Table {
|
||||||
|
UCHAR ucRevId;
|
||||||
|
UCHAR ucNumEntries; /* Number of entries.*/
|
||||||
|
ATOM_Vega10_CLK_Dependency_Record entries[1]; /* Dynamically allocate entries. */
|
||||||
|
} ATOM_Vega10_DISPCLK_Dependency_Table;
|
||||||
|
|
||||||
|
typedef struct _ATOM_Vega10_PHYCLK_Dependency_Table {
|
||||||
|
UCHAR ucRevId;
|
||||||
|
UCHAR ucNumEntries; /* Number of entries. */
|
||||||
|
ATOM_Vega10_CLK_Dependency_Record entries[1]; /* Dynamically allocate entries. */
|
||||||
|
} ATOM_Vega10_PHYCLK_Dependency_Table;
|
||||||
|
|
||||||
|
typedef struct _ATOM_Vega10_MM_Dependency_Record {
|
||||||
|
UCHAR ucVddcInd; /* SOC_VDD voltage */
|
||||||
|
ULONG ulDClk; /* UVD D-clock */
|
||||||
|
ULONG ulVClk; /* UVD V-clock */
|
||||||
|
ULONG ulEClk; /* VCE clock */
|
||||||
|
ULONG ulPSPClk; /* PSP clock */
|
||||||
|
} ATOM_Vega10_MM_Dependency_Record;
|
||||||
|
|
||||||
|
typedef struct _ATOM_Vega10_MM_Dependency_Table {
|
||||||
|
UCHAR ucRevId;
|
||||||
|
UCHAR ucNumEntries; /* Number of entries */
|
||||||
|
ATOM_Vega10_MM_Dependency_Record entries[1]; /* Dynamically allocate entries */
|
||||||
|
} ATOM_Vega10_MM_Dependency_Table;
|
||||||
|
|
||||||
|
typedef struct _ATOM_Vega10_PCIE_Record {
|
||||||
|
ULONG ulLCLK; /* LClock */
|
||||||
|
UCHAR ucPCIEGenSpeed; /* PCIE Speed */
|
||||||
|
UCHAR ucPCIELaneWidth; /* PCIE Lane Width */
|
||||||
|
} ATOM_Vega10_PCIE_Record;
|
||||||
|
|
||||||
|
typedef struct _ATOM_Vega10_PCIE_Table {
|
||||||
|
UCHAR ucRevId;
|
||||||
|
UCHAR ucNumEntries; /* Number of entries */
|
||||||
|
ATOM_Vega10_PCIE_Record entries[1]; /* Dynamically allocate entries. */
|
||||||
|
} ATOM_Vega10_PCIE_Table;
|
||||||
|
|
||||||
|
typedef struct _ATOM_Vega10_Voltage_Lookup_Record {
|
||||||
|
USHORT usVdd; /* Base voltage */
|
||||||
|
} ATOM_Vega10_Voltage_Lookup_Record;
|
||||||
|
|
||||||
|
typedef struct _ATOM_Vega10_Voltage_Lookup_Table {
|
||||||
|
UCHAR ucRevId;
|
||||||
|
UCHAR ucNumEntries; /* Number of entries */
|
||||||
|
ATOM_Vega10_Voltage_Lookup_Record entries[1]; /* Dynamically allocate entries */
|
||||||
|
} ATOM_Vega10_Voltage_Lookup_Table;
|
||||||
|
|
||||||
|
typedef struct _ATOM_Vega10_Fan_Table {
|
||||||
|
UCHAR ucRevId; /* Change this if the table format changes or version changes so that the other fields are not the same. */
|
||||||
|
USHORT usFanOutputSensitivity; /* Sensitivity of fan reaction to temepature changes. */
|
||||||
|
USHORT usFanRPMMax; /* The default value in RPM. */
|
||||||
|
USHORT usThrottlingRPM;
|
||||||
|
USHORT usFanAcousticLimit; /* Minimum Fan Controller Frequency Acoustic Limit. */
|
||||||
|
USHORT usTargetTemperature; /* The default ideal temperature in Celcius. */
|
||||||
|
USHORT usMinimumPWMLimit; /* The minimum PWM that the advanced fan controller can set. */
|
||||||
|
USHORT usTargetGfxClk; /* The ideal Fan Controller GFXCLK Frequency Acoustic Limit. */
|
||||||
|
USHORT usFanGainEdge;
|
||||||
|
USHORT usFanGainHotspot;
|
||||||
|
USHORT usFanGainLiquid;
|
||||||
|
USHORT usFanGainVrVddc;
|
||||||
|
USHORT usFanGainVrMvdd;
|
||||||
|
USHORT usFanGainPlx;
|
||||||
|
USHORT usFanGainHbm;
|
||||||
|
UCHAR ucEnableZeroRPM;
|
||||||
|
USHORT usFanStopTemperature;
|
||||||
|
USHORT usFanStartTemperature;
|
||||||
|
} ATOM_Vega10_Fan_Table;
|
||||||
|
|
||||||
|
typedef struct _ATOM_Vega10_Thermal_Controller {
|
||||||
|
UCHAR ucRevId;
|
||||||
|
UCHAR ucType; /* one of ATOM_VEGA10_PP_THERMALCONTROLLER_*/
|
||||||
|
UCHAR ucI2cLine; /* as interpreted by DAL I2C */
|
||||||
|
UCHAR ucI2cAddress;
|
||||||
|
UCHAR ucFanParameters; /* Fan Control Parameters. */
|
||||||
|
UCHAR ucFanMinRPM; /* Fan Minimum RPM (hundreds) -- for display purposes only.*/
|
||||||
|
UCHAR ucFanMaxRPM; /* Fan Maximum RPM (hundreds) -- for display purposes only.*/
|
||||||
|
UCHAR ucFlags; /* to be defined */
|
||||||
|
} ATOM_Vega10_Thermal_Controller;
|
||||||
|
|
||||||
|
typedef struct _ATOM_Vega10_VCE_State_Record
|
||||||
|
{
|
||||||
|
UCHAR ucVCEClockIndex; /*index into usVCEDependencyTableOffset of 'ATOM_Vega10_MM_Dependency_Table' type */
|
||||||
|
UCHAR ucFlag; /* 2 bits indicates memory p-states */
|
||||||
|
UCHAR ucSCLKIndex; /* index into ATOM_Vega10_SCLK_Dependency_Table */
|
||||||
|
UCHAR ucMCLKIndex; /* index into ATOM_Vega10_MCLK_Dependency_Table */
|
||||||
|
} ATOM_Vega10_VCE_State_Record;
|
||||||
|
|
||||||
|
typedef struct _ATOM_Vega10_VCE_State_Table
|
||||||
|
{
|
||||||
|
UCHAR ucRevId;
|
||||||
|
UCHAR ucNumEntries;
|
||||||
|
ATOM_Vega10_VCE_State_Record entries[1];
|
||||||
|
} ATOM_Vega10_VCE_State_Table;
|
||||||
|
|
||||||
|
typedef struct _ATOM_Vega10_PowerTune_Table {
|
||||||
|
UCHAR ucRevId;
|
||||||
|
USHORT usSocketPowerLimit;
|
||||||
|
USHORT usBatteryPowerLimit;
|
||||||
|
USHORT usSmallPowerLimit;
|
||||||
|
USHORT usTdcLimit;
|
||||||
|
USHORT usEdcLimit;
|
||||||
|
USHORT usSoftwareShutdownTemp;
|
||||||
|
USHORT usTemperatureLimitHotSpot;
|
||||||
|
USHORT usTemperatureLimitLiquid1;
|
||||||
|
USHORT usTemperatureLimitLiquid2;
|
||||||
|
USHORT usTemperatureLimitHBM;
|
||||||
|
USHORT usTemperatureLimitVrSoc;
|
||||||
|
USHORT usTemperatureLimitVrMem;
|
||||||
|
USHORT usTemperatureLimitPlx;
|
||||||
|
USHORT usLoadLineResistance;
|
||||||
|
UCHAR ucLiquid1_I2C_address;
|
||||||
|
UCHAR ucLiquid2_I2C_address;
|
||||||
|
UCHAR ucVr_I2C_address;
|
||||||
|
UCHAR ucPlx_I2C_address;
|
||||||
|
UCHAR ucLiquid_I2C_LineSCL;
|
||||||
|
UCHAR ucLiquid_I2C_LineSDA;
|
||||||
|
UCHAR ucVr_I2C_LineSCL;
|
||||||
|
UCHAR ucVr_I2C_LineSDA;
|
||||||
|
UCHAR ucPlx_I2C_LineSCL;
|
||||||
|
UCHAR ucPlx_I2C_LineSDA;
|
||||||
|
USHORT usTemperatureLimitTedge;
|
||||||
|
} ATOM_Vega10_PowerTune_Table;
|
||||||
|
|
||||||
|
typedef struct _ATOM_Vega10_Hard_Limit_Record {
|
||||||
|
ULONG ulSOCCLKLimit;
|
||||||
|
ULONG ulGFXCLKLimit;
|
||||||
|
ULONG ulMCLKLimit;
|
||||||
|
USHORT usVddcLimit;
|
||||||
|
USHORT usVddciLimit;
|
||||||
|
USHORT usVddMemLimit;
|
||||||
|
} ATOM_Vega10_Hard_Limit_Record;
|
||||||
|
|
||||||
|
typedef struct _ATOM_Vega10_Hard_Limit_Table
|
||||||
|
{
|
||||||
|
UCHAR ucRevId;
|
||||||
|
UCHAR ucNumEntries;
|
||||||
|
ATOM_Vega10_Hard_Limit_Record entries[1];
|
||||||
|
} ATOM_Vega10_Hard_Limit_Table;
|
||||||
|
|
||||||
|
typedef struct _Vega10_PPTable_Generic_SubTable_Header
|
||||||
|
{
|
||||||
|
UCHAR ucRevId;
|
||||||
|
} Vega10_PPTable_Generic_SubTable_Header;
|
||||||
|
|
||||||
|
#pragma pack(pop)
|
||||||
|
|
||||||
|
#endif
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,34 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2016 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
|
* copy of this software and associated documentation files (the "Software"),
|
||||||
|
* to deal in the Software without restriction, including without limitation
|
||||||
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||||
|
* and/or sell copies of the Software, and to permit persons to whom the
|
||||||
|
* Software is furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
|
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||||
|
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||||
|
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||||
|
* OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef VEGA10_PROCESSPPTABLES_H
|
||||||
|
#define VEGA10_PROCESSPPTABLES_H
|
||||||
|
|
||||||
|
#include "hwmgr.h"
|
||||||
|
|
||||||
|
extern const struct pp_table_func vega10_pptable_funcs;
|
||||||
|
extern int vega10_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr);
|
||||||
|
extern int vega10_get_powerplay_table_entry(struct pp_hwmgr *hwmgr, uint32_t entry_index,
|
||||||
|
struct pp_power_state *power_state, int (*call_back_func)(struct pp_hwmgr *, void *,
|
||||||
|
struct pp_power_state *, void *, uint32_t));
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,761 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2016 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
|
* copy of this software and associated documentation files (the "Software"),
|
||||||
|
* to deal in the Software without restriction, including without limitation
|
||||||
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||||
|
* and/or sell copies of the Software, and to permit persons to whom the
|
||||||
|
* Software is furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
|
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||||
|
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||||
|
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||||
|
* OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "vega10_thermal.h"
|
||||||
|
#include "vega10_hwmgr.h"
|
||||||
|
#include "vega10_smumgr.h"
|
||||||
|
#include "vega10_ppsmc.h"
|
||||||
|
#include "vega10_inc.h"
|
||||||
|
#include "pp_soc15.h"
|
||||||
|
#include "pp_debug.h"
|
||||||
|
|
||||||
|
static int vega10_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
|
||||||
|
{
|
||||||
|
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
|
||||||
|
PPSMC_MSG_GetCurrentRpm),
|
||||||
|
"Attempt to get current RPM from SMC Failed!",
|
||||||
|
return -1);
|
||||||
|
PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr->smumgr,
|
||||||
|
current_rpm),
|
||||||
|
"Attempt to read current RPM from SMC Failed!",
|
||||||
|
return -1);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
|
||||||
|
struct phm_fan_speed_info *fan_speed_info)
|
||||||
|
{
|
||||||
|
|
||||||
|
if (hwmgr->thermal_controller.fanInfo.bNoFan)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
fan_speed_info->supports_percent_read = true;
|
||||||
|
fan_speed_info->supports_percent_write = true;
|
||||||
|
fan_speed_info->min_percent = 0;
|
||||||
|
fan_speed_info->max_percent = 100;
|
||||||
|
|
||||||
|
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
|
||||||
|
PHM_PlatformCaps_FanSpeedInTableIsRPM) &&
|
||||||
|
hwmgr->thermal_controller.fanInfo.
|
||||||
|
ucTachometerPulsesPerRevolution) {
|
||||||
|
fan_speed_info->supports_rpm_read = true;
|
||||||
|
fan_speed_info->supports_rpm_write = true;
|
||||||
|
fan_speed_info->min_rpm =
|
||||||
|
hwmgr->thermal_controller.fanInfo.ulMinRPM;
|
||||||
|
fan_speed_info->max_rpm =
|
||||||
|
hwmgr->thermal_controller.fanInfo.ulMaxRPM;
|
||||||
|
} else {
|
||||||
|
fan_speed_info->min_rpm = 0;
|
||||||
|
fan_speed_info->max_rpm = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int vega10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
|
||||||
|
uint32_t *speed)
|
||||||
|
{
|
||||||
|
uint32_t current_rpm;
|
||||||
|
uint32_t percent = 0;
|
||||||
|
|
||||||
|
if (hwmgr->thermal_controller.fanInfo.bNoFan)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
if (vega10_get_current_rpm(hwmgr, ¤t_rpm))
|
||||||
|
return -1;
|
||||||
|
|
||||||
|
if (hwmgr->thermal_controller.
|
||||||
|
advanceFanControlParameters.usMaxFanRPM != 0)
|
||||||
|
percent = current_rpm * 100 /
|
||||||
|
hwmgr->thermal_controller.
|
||||||
|
advanceFanControlParameters.usMaxFanRPM;
|
||||||
|
|
||||||
|
*speed = percent > 100 ? 100 : percent;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
|
||||||
|
{
|
||||||
|
struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
|
||||||
|
uint32_t tach_period;
|
||||||
|
uint32_t crystal_clock_freq;
|
||||||
|
int result = 0;
|
||||||
|
|
||||||
|
if (hwmgr->thermal_controller.fanInfo.bNoFan)
|
||||||
|
return -1;
|
||||||
|
|
||||||
|
if (data->smu_features[GNLD_FAN_CONTROL].supported)
|
||||||
|
result = vega10_get_current_rpm(hwmgr, speed);
|
||||||
|
else {
|
||||||
|
uint32_t reg = soc15_get_register_offset(THM_HWID, 0,
|
||||||
|
mmCG_TACH_STATUS_BASE_IDX, mmCG_TACH_STATUS);
|
||||||
|
tach_period = (cgs_read_register(hwmgr->device,
|
||||||
|
reg) & CG_TACH_STATUS__TACH_PERIOD_MASK) >>
|
||||||
|
CG_TACH_STATUS__TACH_PERIOD__SHIFT;
|
||||||
|
|
||||||
|
if (tach_period == 0)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
crystal_clock_freq = smu7_get_xclk(hwmgr);
|
||||||
|
|
||||||
|
*speed = 60 * crystal_clock_freq * 10000 / tach_period;
|
||||||
|
}
|
||||||
|
|
||||||
|
return result;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Set Fan Speed Control to static mode,
|
||||||
|
* so that the user can decide what speed to use.
|
||||||
|
* @param hwmgr the address of the powerplay hardware manager.
|
||||||
|
* mode the fan control mode, 0 default, 1 by percent, 5, by RPM
|
||||||
|
* @exception Should always succeed.
|
||||||
|
*/
|
||||||
|
int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
|
||||||
|
{
|
||||||
|
uint32_t reg;
|
||||||
|
|
||||||
|
reg = soc15_get_register_offset(THM_HWID, 0,
|
||||||
|
mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2);
|
||||||
|
|
||||||
|
if (hwmgr->fan_ctrl_is_in_default_mode) {
|
||||||
|
hwmgr->fan_ctrl_default_mode =
|
||||||
|
(cgs_read_register(hwmgr->device, reg) &
|
||||||
|
CG_FDO_CTRL2__FDO_PWM_MODE_MASK) >>
|
||||||
|
CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
|
||||||
|
hwmgr->tmin = (cgs_read_register(hwmgr->device, reg) &
|
||||||
|
CG_FDO_CTRL2__TMIN_MASK) >>
|
||||||
|
CG_FDO_CTRL2__TMIN__SHIFT;
|
||||||
|
hwmgr->fan_ctrl_is_in_default_mode = false;
|
||||||
|
}
|
||||||
|
|
||||||
|
cgs_write_register(hwmgr->device, reg,
|
||||||
|
(cgs_read_register(hwmgr->device, reg) &
|
||||||
|
~CG_FDO_CTRL2__TMIN_MASK) |
|
||||||
|
(0 << CG_FDO_CTRL2__TMIN__SHIFT));
|
||||||
|
cgs_write_register(hwmgr->device, reg,
|
||||||
|
(cgs_read_register(hwmgr->device, reg) &
|
||||||
|
~CG_FDO_CTRL2__FDO_PWM_MODE_MASK) |
|
||||||
|
(mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT));
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Reset Fan Speed Control to default mode.
|
||||||
|
* @param hwmgr the address of the powerplay hardware manager.
|
||||||
|
* @exception Should always succeed.
|
||||||
|
*/
|
||||||
|
int vega10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
|
||||||
|
{
|
||||||
|
uint32_t reg;
|
||||||
|
|
||||||
|
reg = soc15_get_register_offset(THM_HWID, 0,
|
||||||
|
mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2);
|
||||||
|
|
||||||
|
if (!hwmgr->fan_ctrl_is_in_default_mode) {
|
||||||
|
cgs_write_register(hwmgr->device, reg,
|
||||||
|
(cgs_read_register(hwmgr->device, reg) &
|
||||||
|
~CG_FDO_CTRL2__FDO_PWM_MODE_MASK) |
|
||||||
|
(hwmgr->fan_ctrl_default_mode <<
|
||||||
|
CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT));
|
||||||
|
cgs_write_register(hwmgr->device, reg,
|
||||||
|
(cgs_read_register(hwmgr->device, reg) &
|
||||||
|
~CG_FDO_CTRL2__TMIN_MASK) |
|
||||||
|
(hwmgr->tmin << CG_FDO_CTRL2__TMIN__SHIFT));
|
||||||
|
hwmgr->fan_ctrl_is_in_default_mode = true;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @fn vega10_enable_fan_control_feature
|
||||||
|
* @brief Enables the SMC Fan Control Feature.
|
||||||
|
*
|
||||||
|
* @param hwmgr - the address of the powerplay hardware manager.
|
||||||
|
* @return 0 on success. -1 otherwise.
|
||||||
|
*/
|
||||||
|
static int vega10_enable_fan_control_feature(struct pp_hwmgr *hwmgr)
|
||||||
|
{
|
||||||
|
struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
|
||||||
|
|
||||||
|
if (data->smu_features[GNLD_FAN_CONTROL].supported) {
|
||||||
|
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
|
||||||
|
hwmgr->smumgr, true,
|
||||||
|
data->smu_features[GNLD_FAN_CONTROL].
|
||||||
|
smu_feature_bitmap),
|
||||||
|
"Attempt to Enable FAN CONTROL feature Failed!",
|
||||||
|
return -1);
|
||||||
|
data->smu_features[GNLD_FAN_CONTROL].enabled = true;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int vega10_disable_fan_control_feature(struct pp_hwmgr *hwmgr)
|
||||||
|
{
|
||||||
|
struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
|
||||||
|
|
||||||
|
if (data->smu_features[GNLD_FAN_CONTROL].supported) {
|
||||||
|
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
|
||||||
|
hwmgr->smumgr, false,
|
||||||
|
data->smu_features[GNLD_FAN_CONTROL].
|
||||||
|
smu_feature_bitmap),
|
||||||
|
"Attempt to Enable FAN CONTROL feature Failed!",
|
||||||
|
return -1);
|
||||||
|
data->smu_features[GNLD_FAN_CONTROL].enabled = false;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
|
||||||
|
{
|
||||||
|
if (hwmgr->thermal_controller.fanInfo.bNoFan)
|
||||||
|
return -1;
|
||||||
|
|
||||||
|
PP_ASSERT_WITH_CODE(!vega10_enable_fan_control_feature(hwmgr),
|
||||||
|
"Attempt to Enable SMC FAN CONTROL Feature Failed!",
|
||||||
|
return -1);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
int vega10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
|
||||||
|
{
|
||||||
|
struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
|
||||||
|
|
||||||
|
if (hwmgr->thermal_controller.fanInfo.bNoFan)
|
||||||
|
return -1;
|
||||||
|
|
||||||
|
if (data->smu_features[GNLD_FAN_CONTROL].supported) {
|
||||||
|
PP_ASSERT_WITH_CODE(!vega10_disable_fan_control_feature(hwmgr),
|
||||||
|
"Attempt to Disable SMC FAN CONTROL Feature Failed!",
|
||||||
|
return -1);
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Set Fan Speed in percent.
|
||||||
|
* @param hwmgr the address of the powerplay hardware manager.
|
||||||
|
* @param speed is the percentage value (0% - 100%) to be set.
|
||||||
|
* @exception Fails is the 100% setting appears to be 0.
|
||||||
|
*/
|
||||||
|
int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
|
||||||
|
uint32_t speed)
|
||||||
|
{
|
||||||
|
uint32_t duty100;
|
||||||
|
uint32_t duty;
|
||||||
|
uint64_t tmp64;
|
||||||
|
uint32_t reg;
|
||||||
|
|
||||||
|
if (hwmgr->thermal_controller.fanInfo.bNoFan)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
if (speed > 100)
|
||||||
|
speed = 100;
|
||||||
|
|
||||||
|
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
|
||||||
|
PHM_PlatformCaps_MicrocodeFanControl))
|
||||||
|
vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
|
||||||
|
|
||||||
|
reg = soc15_get_register_offset(THM_HWID, 0,
|
||||||
|
mmCG_FDO_CTRL1_BASE_IDX, mmCG_FDO_CTRL1);
|
||||||
|
|
||||||
|
duty100 = (cgs_read_register(hwmgr->device, reg) &
|
||||||
|
CG_FDO_CTRL1__FMAX_DUTY100_MASK) >>
|
||||||
|
CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
|
||||||
|
|
||||||
|
if (duty100 == 0)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
tmp64 = (uint64_t)speed * duty100;
|
||||||
|
do_div(tmp64, 100);
|
||||||
|
duty = (uint32_t)tmp64;
|
||||||
|
|
||||||
|
reg = soc15_get_register_offset(THM_HWID, 0,
|
||||||
|
mmCG_FDO_CTRL0_BASE_IDX, mmCG_FDO_CTRL0);
|
||||||
|
cgs_write_register(hwmgr->device, reg,
|
||||||
|
(cgs_read_register(hwmgr->device, reg) &
|
||||||
|
~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK) |
|
||||||
|
(duty << CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT));
|
||||||
|
|
||||||
|
return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Reset Fan Speed to default.
|
||||||
|
* @param hwmgr the address of the powerplay hardware manager.
|
||||||
|
* @exception Always succeeds.
|
||||||
|
*/
|
||||||
|
int vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
|
||||||
|
{
|
||||||
|
int result;
|
||||||
|
|
||||||
|
if (hwmgr->thermal_controller.fanInfo.bNoFan)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
|
||||||
|
PHM_PlatformCaps_MicrocodeFanControl)) {
|
||||||
|
result = vega10_fan_ctrl_set_static_mode(hwmgr,
|
||||||
|
FDO_PWM_MODE_STATIC);
|
||||||
|
if (!result)
|
||||||
|
result = vega10_fan_ctrl_start_smc_fan_control(hwmgr);
|
||||||
|
} else
|
||||||
|
result = vega10_fan_ctrl_set_default_mode(hwmgr);
|
||||||
|
|
||||||
|
return result;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Set Fan Speed in RPM.
|
||||||
|
* @param hwmgr the address of the powerplay hardware manager.
|
||||||
|
* @param speed is the percentage value (min - max) to be set.
|
||||||
|
* @exception Fails is the speed not lie between min and max.
|
||||||
|
*/
|
||||||
|
int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
|
||||||
|
{
|
||||||
|
uint32_t tach_period;
|
||||||
|
uint32_t crystal_clock_freq;
|
||||||
|
int result = 0;
|
||||||
|
uint32_t reg;
|
||||||
|
|
||||||
|
if (hwmgr->thermal_controller.fanInfo.bNoFan ||
|
||||||
|
(speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||
|
||||||
|
(speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))
|
||||||
|
return -1;
|
||||||
|
|
||||||
|
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
|
||||||
|
PHM_PlatformCaps_MicrocodeFanControl))
|
||||||
|
result = vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
|
||||||
|
|
||||||
|
if (!result) {
|
||||||
|
crystal_clock_freq = smu7_get_xclk(hwmgr);
|
||||||
|
tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
|
||||||
|
reg = soc15_get_register_offset(THM_HWID, 0,
|
||||||
|
mmCG_TACH_STATUS_BASE_IDX, mmCG_TACH_STATUS);
|
||||||
|
cgs_write_register(hwmgr->device, reg,
|
||||||
|
(cgs_read_register(hwmgr->device, reg) &
|
||||||
|
~CG_TACH_STATUS__TACH_PERIOD_MASK) |
|
||||||
|
(tach_period << CG_TACH_STATUS__TACH_PERIOD__SHIFT));
|
||||||
|
}
|
||||||
|
return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC_RPM);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Reads the remote temperature from the SIslands thermal controller.
|
||||||
|
*
|
||||||
|
* @param hwmgr The address of the hardware manager.
|
||||||
|
*/
|
||||||
|
int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
|
||||||
|
{
|
||||||
|
int temp;
|
||||||
|
uint32_t reg;
|
||||||
|
|
||||||
|
reg = soc15_get_register_offset(THM_HWID, 0,
|
||||||
|
mmCG_TACH_STATUS_BASE_IDX, mmCG_MULT_THERMAL_STATUS);
|
||||||
|
|
||||||
|
temp = cgs_read_register(hwmgr->device, reg);
|
||||||
|
|
||||||
|
temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
|
||||||
|
CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
|
||||||
|
|
||||||
|
/* Bit 9 means the reading is lower than the lowest usable value. */
|
||||||
|
if (temp & 0x200)
|
||||||
|
temp = VEGA10_THERMAL_MAXIMUM_TEMP_READING;
|
||||||
|
else
|
||||||
|
temp = temp & 0x1ff;
|
||||||
|
|
||||||
|
temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
|
||||||
|
|
||||||
|
return temp;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Set the requested temperature range for high and low alert signals
|
||||||
|
*
|
||||||
|
* @param hwmgr The address of the hardware manager.
|
||||||
|
* @param range Temperature range to be programmed for
|
||||||
|
* high and low alert signals
|
||||||
|
* @exception PP_Result_BadInput if the input data is not valid.
|
||||||
|
*/
|
||||||
|
static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
|
||||||
|
struct PP_TemperatureRange *range)
|
||||||
|
{
|
||||||
|
uint32_t low = VEGA10_THERMAL_MINIMUM_ALERT_TEMP *
|
||||||
|
PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
|
||||||
|
uint32_t high = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP *
|
||||||
|
PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
|
||||||
|
uint32_t val, reg;
|
||||||
|
|
||||||
|
if (low < range->min)
|
||||||
|
low = range->min;
|
||||||
|
if (high > range->max)
|
||||||
|
high = range->max;
|
||||||
|
|
||||||
|
if (low > high)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
reg = soc15_get_register_offset(THM_HWID, 0,
|
||||||
|
mmTHM_THERMAL_INT_CTRL_BASE_IDX, mmTHM_THERMAL_INT_CTRL);
|
||||||
|
|
||||||
|
val = cgs_read_register(hwmgr->device, reg);
|
||||||
|
val &= ~(THM_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK);
|
||||||
|
val |= (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES) <<
|
||||||
|
THM_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT;
|
||||||
|
val &= ~(THM_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK);
|
||||||
|
val |= (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES) <<
|
||||||
|
THM_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT;
|
||||||
|
cgs_write_register(hwmgr->device, reg, val);
|
||||||
|
|
||||||
|
reg = soc15_get_register_offset(THM_HWID, 0,
|
||||||
|
mmTHM_TCON_HTC_BASE_IDX, mmTHM_TCON_HTC);
|
||||||
|
|
||||||
|
val = cgs_read_register(hwmgr->device, reg);
|
||||||
|
val &= ~(THM_TCON_HTC__HTC_TMP_LMT_MASK);
|
||||||
|
val |= (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES) <<
|
||||||
|
THM_TCON_HTC__HTC_TMP_LMT__SHIFT;
|
||||||
|
cgs_write_register(hwmgr->device, reg, val);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Programs thermal controller one-time setting registers
|
||||||
|
*
|
||||||
|
* @param hwmgr The address of the hardware manager.
|
||||||
|
*/
|
||||||
|
static int vega10_thermal_initialize(struct pp_hwmgr *hwmgr)
|
||||||
|
{
|
||||||
|
uint32_t reg;
|
||||||
|
|
||||||
|
if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {
|
||||||
|
reg = soc15_get_register_offset(THM_HWID, 0,
|
||||||
|
mmCG_TACH_CTRL_BASE_IDX, mmCG_TACH_CTRL);
|
||||||
|
cgs_write_register(hwmgr->device, reg,
|
||||||
|
(cgs_read_register(hwmgr->device, reg) &
|
||||||
|
~CG_TACH_CTRL__EDGE_PER_REV_MASK) |
|
||||||
|
((hwmgr->thermal_controller.fanInfo.
|
||||||
|
ucTachometerPulsesPerRevolution - 1) <<
|
||||||
|
CG_TACH_CTRL__EDGE_PER_REV__SHIFT));
|
||||||
|
}
|
||||||
|
|
||||||
|
reg = soc15_get_register_offset(THM_HWID, 0,
|
||||||
|
mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2);
|
||||||
|
cgs_write_register(hwmgr->device, reg,
|
||||||
|
(cgs_read_register(hwmgr->device, reg) &
|
||||||
|
~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK) |
|
||||||
|
(0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT));
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Enable thermal alerts on the RV770 thermal controller.
|
||||||
|
*
|
||||||
|
* @param hwmgr The address of the hardware manager.
|
||||||
|
*/
|
||||||
|
static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr)
|
||||||
|
{
|
||||||
|
struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
|
||||||
|
|
||||||
|
if (data->smu_features[GNLD_FW_CTF].supported) {
|
||||||
|
if (data->smu_features[GNLD_FW_CTF].enabled)
|
||||||
|
printk("[Thermal_EnableAlert] FW CTF Already Enabled!\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
|
||||||
|
true,
|
||||||
|
data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
|
||||||
|
"Attempt to Enable FW CTF feature Failed!",
|
||||||
|
return -1);
|
||||||
|
data->smu_features[GNLD_FW_CTF].enabled = true;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Disable thermal alerts on the RV770 thermal controller.
|
||||||
|
* @param hwmgr The address of the hardware manager.
|
||||||
|
*/
|
||||||
|
static int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr)
|
||||||
|
{
|
||||||
|
struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
|
||||||
|
|
||||||
|
if (data->smu_features[GNLD_FW_CTF].supported) {
|
||||||
|
if (!data->smu_features[GNLD_FW_CTF].enabled)
|
||||||
|
printk("[Thermal_EnableAlert] FW CTF Already disabled!\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
|
||||||
|
false,
|
||||||
|
data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
|
||||||
|
"Attempt to disable FW CTF feature Failed!",
|
||||||
|
return -1);
|
||||||
|
data->smu_features[GNLD_FW_CTF].enabled = false;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Uninitialize the thermal controller.
|
||||||
|
* Currently just disables alerts.
|
||||||
|
* @param hwmgr The address of the hardware manager.
|
||||||
|
*/
|
||||||
|
int vega10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
|
||||||
|
{
|
||||||
|
int result = vega10_thermal_disable_alert(hwmgr);
|
||||||
|
|
||||||
|
if (!hwmgr->thermal_controller.fanInfo.bNoFan)
|
||||||
|
vega10_fan_ctrl_set_default_mode(hwmgr);
|
||||||
|
|
||||||
|
return result;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Set up the fan table to control the fan using the SMC.
|
||||||
|
* @param hwmgr the address of the powerplay hardware manager.
|
||||||
|
* @param pInput the pointer to input data
|
||||||
|
* @param pOutput the pointer to output data
|
||||||
|
* @param pStorage the pointer to temporary storage
|
||||||
|
* @param Result the last failure code
|
||||||
|
* @return result from set temperature range routine
|
||||||
|
*/
|
||||||
|
int tf_vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
|
||||||
|
void *input, void *output, void *storage, int result)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
|
||||||
|
PPTable_t *table = &(data->smc_state_table.pp_table);
|
||||||
|
|
||||||
|
if (!data->smu_features[GNLD_FAN_CONTROL].supported)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
table->FanMaximumRpm = (uint16_t)hwmgr->thermal_controller.
|
||||||
|
advanceFanControlParameters.usMaxFanRPM;
|
||||||
|
table->FanThrottlingRpm = hwmgr->thermal_controller.
|
||||||
|
advanceFanControlParameters.usFanRPMMaxLimit;
|
||||||
|
table->FanAcousticLimitRpm = (uint16_t)(hwmgr->thermal_controller.
|
||||||
|
advanceFanControlParameters.ulMinFanSCLKAcousticLimit);
|
||||||
|
table->FanTargetTemperature = hwmgr->thermal_controller.
|
||||||
|
advanceFanControlParameters.usTMax;
|
||||||
|
table->FanPwmMin = hwmgr->thermal_controller.
|
||||||
|
advanceFanControlParameters.usPWMMin * 255 / 100;
|
||||||
|
table->FanTargetGfxclk = (uint16_t)(hwmgr->thermal_controller.
|
||||||
|
advanceFanControlParameters.ulTargetGfxClk);
|
||||||
|
table->FanGainEdge = hwmgr->thermal_controller.
|
||||||
|
advanceFanControlParameters.usFanGainEdge;
|
||||||
|
table->FanGainHotspot = hwmgr->thermal_controller.
|
||||||
|
advanceFanControlParameters.usFanGainHotspot;
|
||||||
|
table->FanGainLiquid = hwmgr->thermal_controller.
|
||||||
|
advanceFanControlParameters.usFanGainLiquid;
|
||||||
|
table->FanGainVrVddc = hwmgr->thermal_controller.
|
||||||
|
advanceFanControlParameters.usFanGainVrVddc;
|
||||||
|
table->FanGainVrMvdd = hwmgr->thermal_controller.
|
||||||
|
advanceFanControlParameters.usFanGainVrMvdd;
|
||||||
|
table->FanGainPlx = hwmgr->thermal_controller.
|
||||||
|
advanceFanControlParameters.usFanGainPlx;
|
||||||
|
table->FanGainHbm = hwmgr->thermal_controller.
|
||||||
|
advanceFanControlParameters.usFanGainHbm;
|
||||||
|
table->FanZeroRpmEnable = hwmgr->thermal_controller.
|
||||||
|
advanceFanControlParameters.ucEnableZeroRPM;
|
||||||
|
table->FanStopTemp = hwmgr->thermal_controller.
|
||||||
|
advanceFanControlParameters.usZeroRPMStopTemperature;
|
||||||
|
table->FanStartTemp = hwmgr->thermal_controller.
|
||||||
|
advanceFanControlParameters.usZeroRPMStartTemperature;
|
||||||
|
|
||||||
|
ret = vega10_copy_table_to_smc(hwmgr->smumgr,
|
||||||
|
(uint8_t *)(&(data->smc_state_table.pp_table)), PPTABLE);
|
||||||
|
if (ret)
|
||||||
|
pr_info("Failed to update Fan Control Table in PPTable!");
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Start the fan control on the SMC.
|
||||||
|
* @param hwmgr the address of the powerplay hardware manager.
|
||||||
|
* @param pInput the pointer to input data
|
||||||
|
* @param pOutput the pointer to output data
|
||||||
|
* @param pStorage the pointer to temporary storage
|
||||||
|
* @param Result the last failure code
|
||||||
|
* @return result from set temperature range routine
|
||||||
|
*/
|
||||||
|
int tf_vega10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr,
|
||||||
|
void *input, void *output, void *storage, int result)
|
||||||
|
{
|
||||||
|
/* If the fantable setup has failed we could have disabled
|
||||||
|
* PHM_PlatformCaps_MicrocodeFanControl even after
|
||||||
|
* this function was included in the table.
|
||||||
|
* Make sure that we still think controlling the fan is OK.
|
||||||
|
*/
|
||||||
|
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
|
||||||
|
PHM_PlatformCaps_MicrocodeFanControl)) {
|
||||||
|
vega10_fan_ctrl_start_smc_fan_control(hwmgr);
|
||||||
|
vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Set temperature range for high and low alerts
|
||||||
|
* @param hwmgr the address of the powerplay hardware manager.
|
||||||
|
* @param pInput the pointer to input data
|
||||||
|
* @param pOutput the pointer to output data
|
||||||
|
* @param pStorage the pointer to temporary storage
|
||||||
|
* @param Result the last failure code
|
||||||
|
* @return result from set temperature range routine
|
||||||
|
*/
|
||||||
|
int tf_vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
|
||||||
|
void *input, void *output, void *storage, int result)
|
||||||
|
{
|
||||||
|
struct PP_TemperatureRange *range = (struct PP_TemperatureRange *)input;
|
||||||
|
|
||||||
|
if (range == NULL)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
return vega10_thermal_set_temperature_range(hwmgr, range);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Programs one-time setting registers
|
||||||
|
* @param hwmgr the address of the powerplay hardware manager.
|
||||||
|
* @param pInput the pointer to input data
|
||||||
|
* @param pOutput the pointer to output data
|
||||||
|
* @param pStorage the pointer to temporary storage
|
||||||
|
* @param Result the last failure code
|
||||||
|
* @return result from initialize thermal controller routine
|
||||||
|
*/
|
||||||
|
int tf_vega10_thermal_initialize(struct pp_hwmgr *hwmgr,
|
||||||
|
void *input, void *output, void *storage, int result)
|
||||||
|
{
|
||||||
|
return vega10_thermal_initialize(hwmgr);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Enable high and low alerts
|
||||||
|
* @param hwmgr the address of the powerplay hardware manager.
|
||||||
|
* @param pInput the pointer to input data
|
||||||
|
* @param pOutput the pointer to output data
|
||||||
|
* @param pStorage the pointer to temporary storage
|
||||||
|
* @param Result the last failure code
|
||||||
|
* @return result from enable alert routine
|
||||||
|
*/
|
||||||
|
int tf_vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr,
|
||||||
|
void *input, void *output, void *storage, int result)
|
||||||
|
{
|
||||||
|
return vega10_thermal_enable_alert(hwmgr);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Disable high and low alerts
|
||||||
|
* @param hwmgr the address of the powerplay hardware manager.
|
||||||
|
* @param pInput the pointer to input data
|
||||||
|
* @param pOutput the pointer to output data
|
||||||
|
* @param pStorage the pointer to temporary storage
|
||||||
|
* @param Result the last failure code
|
||||||
|
* @return result from disable alert routine
|
||||||
|
*/
|
||||||
|
static int tf_vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr,
|
||||||
|
void *input, void *output, void *storage, int result)
|
||||||
|
{
|
||||||
|
return vega10_thermal_disable_alert(hwmgr);
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct phm_master_table_item
|
||||||
|
vega10_thermal_start_thermal_controller_master_list[] = {
|
||||||
|
{NULL, tf_vega10_thermal_initialize},
|
||||||
|
{NULL, tf_vega10_thermal_set_temperature_range},
|
||||||
|
{NULL, tf_vega10_thermal_enable_alert},
|
||||||
|
/* We should restrict performance levels to low before we halt the SMC.
|
||||||
|
* On the other hand we are still in boot state when we do this
|
||||||
|
* so it would be pointless.
|
||||||
|
* If this assumption changes we have to revisit this table.
|
||||||
|
*/
|
||||||
|
{NULL, tf_vega10_thermal_setup_fan_table},
|
||||||
|
{NULL, tf_vega10_thermal_start_smc_fan_control},
|
||||||
|
{NULL, NULL}
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct phm_master_table_header
|
||||||
|
vega10_thermal_start_thermal_controller_master = {
|
||||||
|
0,
|
||||||
|
PHM_MasterTableFlag_None,
|
||||||
|
vega10_thermal_start_thermal_controller_master_list
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct phm_master_table_item
|
||||||
|
vega10_thermal_set_temperature_range_master_list[] = {
|
||||||
|
{NULL, tf_vega10_thermal_disable_alert},
|
||||||
|
{NULL, tf_vega10_thermal_set_temperature_range},
|
||||||
|
{NULL, tf_vega10_thermal_enable_alert},
|
||||||
|
{NULL, NULL}
|
||||||
|
};
|
||||||
|
|
||||||
|
struct phm_master_table_header
|
||||||
|
vega10_thermal_set_temperature_range_master = {
|
||||||
|
0,
|
||||||
|
PHM_MasterTableFlag_None,
|
||||||
|
vega10_thermal_set_temperature_range_master_list
|
||||||
|
};
|
||||||
|
|
||||||
|
int vega10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr)
|
||||||
|
{
|
||||||
|
if (!hwmgr->thermal_controller.fanInfo.bNoFan) {
|
||||||
|
vega10_fan_ctrl_set_default_mode(hwmgr);
|
||||||
|
vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Initializes the thermal controller related functions
|
||||||
|
* in the Hardware Manager structure.
|
||||||
|
* @param hwmgr The address of the hardware manager.
|
||||||
|
* @exception Any error code from the low-level communication.
|
||||||
|
*/
|
||||||
|
int pp_vega10_thermal_initialize(struct pp_hwmgr *hwmgr)
|
||||||
|
{
|
||||||
|
int result;
|
||||||
|
|
||||||
|
result = phm_construct_table(hwmgr,
|
||||||
|
&vega10_thermal_set_temperature_range_master,
|
||||||
|
&(hwmgr->set_temperature_range));
|
||||||
|
|
||||||
|
if (!result) {
|
||||||
|
result = phm_construct_table(hwmgr,
|
||||||
|
&vega10_thermal_start_thermal_controller_master,
|
||||||
|
&(hwmgr->start_thermal_controller));
|
||||||
|
if (result)
|
||||||
|
phm_destroy_table(hwmgr,
|
||||||
|
&(hwmgr->set_temperature_range));
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!result)
|
||||||
|
hwmgr->fan_ctrl_is_in_default_mode = true;
|
||||||
|
return result;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,83 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2015 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
|
* copy of this software and associated documentation files (the "Software"),
|
||||||
|
* to deal in the Software without restriction, including without limitation
|
||||||
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||||
|
* and/or sell copies of the Software, and to permit persons to whom the
|
||||||
|
* Software is furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
|
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||||
|
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||||
|
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||||
|
* OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef VEGA10_THERMAL_H
|
||||||
|
#define VEGA10_THERMAL_H
|
||||||
|
|
||||||
|
#include "hwmgr.h"
|
||||||
|
|
||||||
|
struct vega10_temperature {
|
||||||
|
uint16_t edge_temp;
|
||||||
|
uint16_t hot_spot_temp;
|
||||||
|
uint16_t hbm_temp;
|
||||||
|
uint16_t vr_soc_temp;
|
||||||
|
uint16_t vr_mem_temp;
|
||||||
|
uint16_t liquid1_temp;
|
||||||
|
uint16_t liquid2_temp;
|
||||||
|
uint16_t plx_temp;
|
||||||
|
};
|
||||||
|
|
||||||
|
#define VEGA10_THERMAL_HIGH_ALERT_MASK 0x1
|
||||||
|
#define VEGA10_THERMAL_LOW_ALERT_MASK 0x2
|
||||||
|
|
||||||
|
#define VEGA10_THERMAL_MINIMUM_TEMP_READING -256
|
||||||
|
#define VEGA10_THERMAL_MAXIMUM_TEMP_READING 255
|
||||||
|
|
||||||
|
#define VEGA10_THERMAL_MINIMUM_ALERT_TEMP 0
|
||||||
|
#define VEGA10_THERMAL_MAXIMUM_ALERT_TEMP 255
|
||||||
|
|
||||||
|
#define FDO_PWM_MODE_STATIC 1
|
||||||
|
#define FDO_PWM_MODE_STATIC_RPM 5
|
||||||
|
|
||||||
|
|
||||||
|
extern int tf_vega10_thermal_initialize(struct pp_hwmgr *hwmgr,
|
||||||
|
void *input, void *output, void *storage, int result);
|
||||||
|
extern int tf_vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
|
||||||
|
void *input, void *output, void *storage, int result);
|
||||||
|
extern int tf_vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr,
|
||||||
|
void *input, void *output, void *storage, int result);
|
||||||
|
|
||||||
|
extern int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr);
|
||||||
|
extern int vega10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr);
|
||||||
|
extern int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
|
||||||
|
struct phm_fan_speed_info *fan_speed_info);
|
||||||
|
extern int vega10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
|
||||||
|
uint32_t *speed);
|
||||||
|
extern int vega10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr);
|
||||||
|
extern int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr,
|
||||||
|
uint32_t mode);
|
||||||
|
extern int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
|
||||||
|
uint32_t speed);
|
||||||
|
extern int vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr);
|
||||||
|
extern int pp_vega10_thermal_initialize(struct pp_hwmgr *hwmgr);
|
||||||
|
extern int vega10_thermal_ctrl_uninitialize_thermal_controller(
|
||||||
|
struct pp_hwmgr *hwmgr);
|
||||||
|
extern int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr,
|
||||||
|
uint32_t speed);
|
||||||
|
extern int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr,
|
||||||
|
uint32_t *speed);
|
||||||
|
extern int vega10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr);
|
||||||
|
extern uint32_t smu7_get_xclk(struct pp_hwmgr *hwmgr);
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
@ -85,6 +85,7 @@ enum PP_FEATURE_MASK {
|
||||||
PP_CLOCK_STRETCH_MASK = 0x400,
|
PP_CLOCK_STRETCH_MASK = 0x400,
|
||||||
PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
|
PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
|
||||||
PP_SOCCLK_DPM_MASK = 0x1000,
|
PP_SOCCLK_DPM_MASK = 0x1000,
|
||||||
|
PP_DCEFCLK_DPM_MASK = 0x2000,
|
||||||
};
|
};
|
||||||
|
|
||||||
enum PHM_BackEnd_Magic {
|
enum PHM_BackEnd_Magic {
|
||||||
|
|
@ -820,6 +821,8 @@ extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t ma
|
||||||
extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr);
|
extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr);
|
||||||
|
|
||||||
extern int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
|
extern int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
|
||||||
|
extern int vega10_hwmgr_init(struct pp_hwmgr *hwmgr);
|
||||||
|
|
||||||
extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
|
extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
|
||||||
uint32_t sclk, uint16_t id, uint16_t *voltage);
|
uint32_t sclk, uint16_t id, uint16_t *voltage);
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,48 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2016 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
|
* copy of this software and associated documentation files (the "Software"),
|
||||||
|
* to deal in the Software without restriction, including without limitation
|
||||||
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||||
|
* and/or sell copies of the Software, and to permit persons to whom the
|
||||||
|
* Software is furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
|
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||||
|
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||||
|
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||||
|
* OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#ifndef PP_SOC15_H
|
||||||
|
#define PP_SOC15_H
|
||||||
|
|
||||||
|
#include "vega10/soc15ip.h"
|
||||||
|
|
||||||
|
inline static uint32_t soc15_get_register_offset(
|
||||||
|
uint32_t hw_id,
|
||||||
|
uint32_t inst,
|
||||||
|
uint32_t segment,
|
||||||
|
uint32_t offset)
|
||||||
|
{
|
||||||
|
uint32_t reg = 0;
|
||||||
|
|
||||||
|
if (hw_id == THM_HWID)
|
||||||
|
reg = THM_BASE.instance[inst].segment[segment] + offset;
|
||||||
|
else if (hw_id == NBIF_HWID)
|
||||||
|
reg = NBIF_BASE.instance[inst].segment[segment] + offset;
|
||||||
|
else if (hw_id == MP1_HWID)
|
||||||
|
reg = MP1_BASE.instance[inst].segment[segment] + offset;
|
||||||
|
else if (hw_id == DF_HWID)
|
||||||
|
reg = DF_BASE.instance[inst].segment[segment] + offset;
|
||||||
|
|
||||||
|
return reg;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -38,6 +38,7 @@ extern const struct pp_smumgr_func iceland_smu_funcs;
|
||||||
extern const struct pp_smumgr_func tonga_smu_funcs;
|
extern const struct pp_smumgr_func tonga_smu_funcs;
|
||||||
extern const struct pp_smumgr_func fiji_smu_funcs;
|
extern const struct pp_smumgr_func fiji_smu_funcs;
|
||||||
extern const struct pp_smumgr_func polaris10_smu_funcs;
|
extern const struct pp_smumgr_func polaris10_smu_funcs;
|
||||||
|
extern const struct pp_smumgr_func vega10_smu_funcs;
|
||||||
|
|
||||||
enum AVFS_BTC_STATUS {
|
enum AVFS_BTC_STATUS {
|
||||||
AVFS_BTC_BOOT = 0,
|
AVFS_BTC_BOOT = 0,
|
||||||
|
|
@ -177,6 +178,8 @@ extern int smu_allocate_memory(void *device, uint32_t size,
|
||||||
void **kptr, void *handle);
|
void **kptr, void *handle);
|
||||||
|
|
||||||
extern int smu_free_memory(void *device, void *handle);
|
extern int smu_free_memory(void *device, void *handle);
|
||||||
|
extern int vega10_smum_init(struct pp_smumgr *smumgr);
|
||||||
|
|
||||||
extern int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr);
|
extern int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr);
|
||||||
|
|
||||||
extern int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type);
|
extern int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type);
|
||||||
|
|
|
||||||
|
|
@ -4,7 +4,7 @@
|
||||||
|
|
||||||
SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o fiji_smc.o \
|
SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o fiji_smc.o \
|
||||||
polaris10_smumgr.o iceland_smumgr.o polaris10_smc.o tonga_smc.o \
|
polaris10_smumgr.o iceland_smumgr.o polaris10_smc.o tonga_smc.o \
|
||||||
smu7_smumgr.o iceland_smc.o
|
smu7_smumgr.o iceland_smc.o vega10_smumgr.o
|
||||||
|
|
||||||
AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR))
|
AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR))
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -86,6 +86,15 @@ int smum_early_init(struct pp_instance *handle)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
|
case AMDGPU_FAMILY_AI:
|
||||||
|
switch (smumgr->chip_id) {
|
||||||
|
case CHIP_VEGA10:
|
||||||
|
smumgr->smumgr_funcs = &vega10_smu_funcs;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
break;
|
||||||
default:
|
default:
|
||||||
kfree(smumgr);
|
kfree(smumgr);
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,564 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2016 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
|
* copy of this software and associated documentation files (the "Software"),
|
||||||
|
* to deal in the Software without restriction, including without limitation
|
||||||
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||||
|
* and/or sell copies of the Software, and to permit persons to whom the
|
||||||
|
* Software is furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
|
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||||
|
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||||
|
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||||
|
* OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "smumgr.h"
|
||||||
|
#include "vega10_inc.h"
|
||||||
|
#include "pp_soc15.h"
|
||||||
|
#include "vega10_smumgr.h"
|
||||||
|
#include "vega10_ppsmc.h"
|
||||||
|
#include "smu9_driver_if.h"
|
||||||
|
|
||||||
|
#include "ppatomctrl.h"
|
||||||
|
#include "pp_debug.h"
|
||||||
|
#include "smu_ucode_xfer_vi.h"
|
||||||
|
#include "smu7_smumgr.h"
|
||||||
|
|
||||||
|
#define AVFS_EN_MSB 1568
|
||||||
|
#define AVFS_EN_LSB 1568
|
||||||
|
|
||||||
|
#define VOLTAGE_SCALE 4
|
||||||
|
|
||||||
|
/* Microcode file is stored in this buffer */
|
||||||
|
#define BUFFER_SIZE 80000
|
||||||
|
#define MAX_STRING_SIZE 15
|
||||||
|
#define BUFFER_SIZETWO 131072 /* 128 *1024 */
|
||||||
|
|
||||||
|
/* MP Apertures */
|
||||||
|
#define MP0_Public 0x03800000
|
||||||
|
#define MP0_SRAM 0x03900000
|
||||||
|
#define MP1_Public 0x03b00000
|
||||||
|
#define MP1_SRAM 0x03c00004
|
||||||
|
|
||||||
|
#define smnMP1_FIRMWARE_FLAGS 0x3010028
|
||||||
|
#define smnMP0_FW_INTF 0x3010104
|
||||||
|
#define smnMP1_PUB_CTRL 0x3010b14
|
||||||
|
|
||||||
|
static bool vega10_is_smc_ram_running(struct pp_smumgr *smumgr)
|
||||||
|
{
|
||||||
|
uint32_t mp1_fw_flags, reg;
|
||||||
|
|
||||||
|
reg = soc15_get_register_offset(NBIF_HWID, 0,
|
||||||
|
mmPCIE_INDEX2_BASE_IDX, mmPCIE_INDEX2);
|
||||||
|
|
||||||
|
cgs_write_register(smumgr->device, reg,
|
||||||
|
(MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff)));
|
||||||
|
|
||||||
|
reg = soc15_get_register_offset(NBIF_HWID, 0,
|
||||||
|
mmPCIE_DATA2_BASE_IDX, mmPCIE_DATA2);
|
||||||
|
|
||||||
|
mp1_fw_flags = cgs_read_register(smumgr->device, reg);
|
||||||
|
|
||||||
|
if (mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)
|
||||||
|
return true;
|
||||||
|
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Check if SMC has responded to previous message.
|
||||||
|
*
|
||||||
|
* @param smumgr the address of the powerplay hardware manager.
|
||||||
|
* @return TRUE SMC has responded, FALSE otherwise.
|
||||||
|
*/
|
||||||
|
static uint32_t vega10_wait_for_response(struct pp_smumgr *smumgr)
|
||||||
|
{
|
||||||
|
uint32_t reg;
|
||||||
|
|
||||||
|
if (!vega10_is_smc_ram_running(smumgr))
|
||||||
|
return -1;
|
||||||
|
|
||||||
|
reg = soc15_get_register_offset(MP1_HWID, 0,
|
||||||
|
mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
|
||||||
|
|
||||||
|
smum_wait_for_register_unequal(smumgr, reg,
|
||||||
|
0, MP1_C2PMSG_90__CONTENT_MASK);
|
||||||
|
|
||||||
|
return cgs_read_register(smumgr->device, reg);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Send a message to the SMC, and do not wait for its response.
|
||||||
|
*
|
||||||
|
* @param smumgr the address of the powerplay hardware manager.
|
||||||
|
* @param msg the message to send.
|
||||||
|
* @return Always return 0.
|
||||||
|
*/
|
||||||
|
int vega10_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr,
|
||||||
|
uint16_t msg)
|
||||||
|
{
|
||||||
|
uint32_t reg;
|
||||||
|
|
||||||
|
if (!vega10_is_smc_ram_running(smumgr))
|
||||||
|
return -1;
|
||||||
|
|
||||||
|
reg = soc15_get_register_offset(MP1_HWID, 0,
|
||||||
|
mmMP1_SMN_C2PMSG_66_BASE_IDX, mmMP1_SMN_C2PMSG_66);
|
||||||
|
cgs_write_register(smumgr->device, reg, msg);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Send a message to the SMC, and wait for its response.
|
||||||
|
*
|
||||||
|
* @param smumgr the address of the powerplay hardware manager.
|
||||||
|
* @param msg the message to send.
|
||||||
|
* @return The response that came from the SMC.
|
||||||
|
*/
|
||||||
|
int vega10_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
|
||||||
|
{
|
||||||
|
uint32_t reg;
|
||||||
|
|
||||||
|
if (!vega10_is_smc_ram_running(smumgr))
|
||||||
|
return -1;
|
||||||
|
|
||||||
|
vega10_wait_for_response(smumgr);
|
||||||
|
|
||||||
|
reg = soc15_get_register_offset(MP1_HWID, 0,
|
||||||
|
mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
|
||||||
|
cgs_write_register(smumgr->device, reg, 0);
|
||||||
|
|
||||||
|
vega10_send_msg_to_smc_without_waiting(smumgr, msg);
|
||||||
|
|
||||||
|
PP_ASSERT_WITH_CODE(vega10_wait_for_response(smumgr) == 1,
|
||||||
|
"Failed to send Message.",
|
||||||
|
return -1);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Send a message to the SMC with parameter
|
||||||
|
* @param smumgr: the address of the powerplay hardware manager.
|
||||||
|
* @param msg: the message to send.
|
||||||
|
* @param parameter: the parameter to send
|
||||||
|
* @return The response that came from the SMC.
|
||||||
|
*/
|
||||||
|
int vega10_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
|
||||||
|
uint16_t msg, uint32_t parameter)
|
||||||
|
{
|
||||||
|
uint32_t reg;
|
||||||
|
|
||||||
|
if (!vega10_is_smc_ram_running(smumgr))
|
||||||
|
return -1;
|
||||||
|
|
||||||
|
vega10_wait_for_response(smumgr);
|
||||||
|
|
||||||
|
reg = soc15_get_register_offset(MP1_HWID, 0,
|
||||||
|
mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
|
||||||
|
cgs_write_register(smumgr->device, reg, 0);
|
||||||
|
|
||||||
|
reg = soc15_get_register_offset(MP1_HWID, 0,
|
||||||
|
mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
|
||||||
|
cgs_write_register(smumgr->device, reg, parameter);
|
||||||
|
|
||||||
|
vega10_send_msg_to_smc_without_waiting(smumgr, msg);
|
||||||
|
|
||||||
|
PP_ASSERT_WITH_CODE(vega10_wait_for_response(smumgr) == 1,
|
||||||
|
"Failed to send Message.",
|
||||||
|
return -1);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Send a message to the SMC with parameter, do not wait for response
|
||||||
|
*
|
||||||
|
* @param smumgr: the address of the powerplay hardware manager.
|
||||||
|
* @param msg: the message to send.
|
||||||
|
* @param parameter: the parameter to send
|
||||||
|
* @return The response that came from the SMC.
|
||||||
|
*/
|
||||||
|
int vega10_send_msg_to_smc_with_parameter_without_waiting(
|
||||||
|
struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
|
||||||
|
{
|
||||||
|
uint32_t reg;
|
||||||
|
|
||||||
|
reg = soc15_get_register_offset(MP1_HWID, 0,
|
||||||
|
mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
|
||||||
|
cgs_write_register(smumgr->device, reg, parameter);
|
||||||
|
|
||||||
|
return vega10_send_msg_to_smc_without_waiting(smumgr, msg);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Retrieve an argument from SMC.
|
||||||
|
*
|
||||||
|
* @param smumgr the address of the powerplay hardware manager.
|
||||||
|
* @param arg pointer to store the argument from SMC.
|
||||||
|
* @return Always return 0.
|
||||||
|
*/
|
||||||
|
int vega10_read_arg_from_smc(struct pp_smumgr *smumgr, uint32_t *arg)
|
||||||
|
{
|
||||||
|
uint32_t reg;
|
||||||
|
|
||||||
|
reg = soc15_get_register_offset(MP1_HWID, 0,
|
||||||
|
mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
|
||||||
|
|
||||||
|
*arg = cgs_read_register(smumgr->device, reg);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Copy table from SMC into driver FB
|
||||||
|
* @param smumgr the address of the SMC manager
|
||||||
|
* @param table_id the driver's table ID to copy from
|
||||||
|
*/
|
||||||
|
int vega10_copy_table_from_smc(struct pp_smumgr *smumgr,
|
||||||
|
uint8_t *table, int16_t table_id)
|
||||||
|
{
|
||||||
|
struct vega10_smumgr *priv =
|
||||||
|
(struct vega10_smumgr *)(smumgr->backend);
|
||||||
|
|
||||||
|
PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
|
||||||
|
"Invalid SMU Table ID!", return -1;);
|
||||||
|
PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
|
||||||
|
"Invalid SMU Table version!", return -1;);
|
||||||
|
PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
|
||||||
|
"Invalid SMU Table Length!", return -1;);
|
||||||
|
PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr,
|
||||||
|
PPSMC_MSG_SetDriverDramAddrHigh,
|
||||||
|
priv->smu_tables.entry[table_id].table_addr_high) == 0,
|
||||||
|
"[CopyTableFromSMC] Attempt to Set Dram Addr High Failed!", return -1;);
|
||||||
|
PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr,
|
||||||
|
PPSMC_MSG_SetDriverDramAddrLow,
|
||||||
|
priv->smu_tables.entry[table_id].table_addr_low) == 0,
|
||||||
|
"[CopyTableFromSMC] Attempt to Set Dram Addr Low Failed!",
|
||||||
|
return -1;);
|
||||||
|
PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr,
|
||||||
|
PPSMC_MSG_TransferTableSmu2Dram,
|
||||||
|
priv->smu_tables.entry[table_id].table_id) == 0,
|
||||||
|
"[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!",
|
||||||
|
return -1;);
|
||||||
|
|
||||||
|
memcpy(table, priv->smu_tables.entry[table_id].table,
|
||||||
|
priv->smu_tables.entry[table_id].size);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Copy table from Driver FB into SMC
|
||||||
|
* @param smumgr the address of the SMC manager
|
||||||
|
* @param table_id the table to copy from
|
||||||
|
*/
|
||||||
|
int vega10_copy_table_to_smc(struct pp_smumgr *smumgr,
|
||||||
|
uint8_t *table, int16_t table_id)
|
||||||
|
{
|
||||||
|
struct vega10_smumgr *priv =
|
||||||
|
(struct vega10_smumgr *)(smumgr->backend);
|
||||||
|
|
||||||
|
PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
|
||||||
|
"Invalid SMU Table ID!", return -1;);
|
||||||
|
PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
|
||||||
|
"Invalid SMU Table version!", return -1;);
|
||||||
|
PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
|
||||||
|
"Invalid SMU Table Length!", return -1;);
|
||||||
|
|
||||||
|
memcpy(priv->smu_tables.entry[table_id].table, table,
|
||||||
|
priv->smu_tables.entry[table_id].size);
|
||||||
|
|
||||||
|
PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr,
|
||||||
|
PPSMC_MSG_SetDriverDramAddrHigh,
|
||||||
|
priv->smu_tables.entry[table_id].table_addr_high) == 0,
|
||||||
|
"[CopyTableToSMC] Attempt to Set Dram Addr High Failed!",
|
||||||
|
return -1;);
|
||||||
|
PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr,
|
||||||
|
PPSMC_MSG_SetDriverDramAddrLow,
|
||||||
|
priv->smu_tables.entry[table_id].table_addr_low) == 0,
|
||||||
|
"[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!",
|
||||||
|
return -1;);
|
||||||
|
PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr,
|
||||||
|
PPSMC_MSG_TransferTableDram2Smu,
|
||||||
|
priv->smu_tables.entry[table_id].table_id) == 0,
|
||||||
|
"[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!",
|
||||||
|
return -1;);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int vega10_perform_btc(struct pp_smumgr *smumgr)
|
||||||
|
{
|
||||||
|
PP_ASSERT_WITH_CODE(!vega10_send_msg_to_smc_with_parameter(
|
||||||
|
smumgr, PPSMC_MSG_RunBtc, 0),
|
||||||
|
"Attempt to run DC BTC Failed!",
|
||||||
|
return -1);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int vega10_save_vft_table(struct pp_smumgr *smumgr, uint8_t *avfs_table)
|
||||||
|
{
|
||||||
|
PP_ASSERT_WITH_CODE(avfs_table,
|
||||||
|
"No access to SMC AVFS Table",
|
||||||
|
return -1);
|
||||||
|
|
||||||
|
return vega10_copy_table_from_smc(smumgr, avfs_table, AVFSTABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
int vega10_restore_vft_table(struct pp_smumgr *smumgr, uint8_t *avfs_table)
|
||||||
|
{
|
||||||
|
PP_ASSERT_WITH_CODE(avfs_table,
|
||||||
|
"No access to SMC AVFS Table",
|
||||||
|
return -1);
|
||||||
|
|
||||||
|
return vega10_copy_table_to_smc(smumgr, avfs_table, AVFSTABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
int vega10_enable_smc_features(struct pp_smumgr *smumgr,
|
||||||
|
bool enable, uint32_t feature_mask)
|
||||||
|
{
|
||||||
|
int msg = enable ? PPSMC_MSG_EnableSmuFeatures :
|
||||||
|
PPSMC_MSG_DisableSmuFeatures;
|
||||||
|
|
||||||
|
return vega10_send_msg_to_smc_with_parameter(smumgr,
|
||||||
|
msg, feature_mask);
|
||||||
|
}
|
||||||
|
|
||||||
|
int vega10_get_smc_features(struct pp_smumgr *smumgr,
|
||||||
|
uint32_t *features_enabled)
|
||||||
|
{
|
||||||
|
if (!vega10_send_msg_to_smc(smumgr,
|
||||||
|
PPSMC_MSG_GetEnabledSmuFeatures)) {
|
||||||
|
if (!vega10_read_arg_from_smc(smumgr, features_enabled))
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
int vega10_set_tools_address(struct pp_smumgr *smumgr)
|
||||||
|
{
|
||||||
|
struct vega10_smumgr *priv =
|
||||||
|
(struct vega10_smumgr *)(smumgr->backend);
|
||||||
|
|
||||||
|
if (priv->smu_tables.entry[TOOLSTABLE].table_addr_high ||
|
||||||
|
priv->smu_tables.entry[TOOLSTABLE].table_addr_low) {
|
||||||
|
if (!vega10_send_msg_to_smc_with_parameter(smumgr,
|
||||||
|
PPSMC_MSG_SetToolsDramAddrHigh,
|
||||||
|
priv->smu_tables.entry[TOOLSTABLE].table_addr_high))
|
||||||
|
vega10_send_msg_to_smc_with_parameter(smumgr,
|
||||||
|
PPSMC_MSG_SetToolsDramAddrLow,
|
||||||
|
priv->smu_tables.entry[TOOLSTABLE].table_addr_low);
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int vega10_verify_smc_interface(struct pp_smumgr *smumgr)
|
||||||
|
{
|
||||||
|
uint32_t smc_driver_if_version;
|
||||||
|
|
||||||
|
PP_ASSERT_WITH_CODE(!vega10_send_msg_to_smc(smumgr,
|
||||||
|
PPSMC_MSG_GetDriverIfVersion),
|
||||||
|
"Attempt to get SMC IF Version Number Failed!",
|
||||||
|
return -1);
|
||||||
|
PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(smumgr,
|
||||||
|
&smc_driver_if_version),
|
||||||
|
"Attempt to read SMC IF Version Number Failed!",
|
||||||
|
return -1);
|
||||||
|
|
||||||
|
if (smc_driver_if_version != SMU9_DRIVER_IF_VERSION)
|
||||||
|
return -1;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Write a 32bit value to the SMC SRAM space.
|
||||||
|
* ALL PARAMETERS ARE IN HOST BYTE ORDER.
|
||||||
|
* @param smumgr the address of the powerplay hardware manager.
|
||||||
|
* @param smc_addr the address in the SMC RAM to access.
|
||||||
|
* @param value to write to the SMC SRAM.
|
||||||
|
*/
|
||||||
|
static int vega10_smu_init(struct pp_smumgr *smumgr)
|
||||||
|
{
|
||||||
|
struct vega10_smumgr *priv;
|
||||||
|
uint64_t mc_addr;
|
||||||
|
void *kaddr = NULL;
|
||||||
|
unsigned long handle, tools_size;
|
||||||
|
int ret;
|
||||||
|
struct cgs_firmware_info info = {0};
|
||||||
|
|
||||||
|
ret = cgs_get_firmware_info(smumgr->device,
|
||||||
|
smu7_convert_fw_type_to_cgs(UCODE_ID_SMU),
|
||||||
|
&info);
|
||||||
|
if (ret || !info.kptr)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
priv = kzalloc(sizeof(struct vega10_smumgr), GFP_KERNEL);
|
||||||
|
|
||||||
|
if (!priv)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
smumgr->backend = priv;
|
||||||
|
|
||||||
|
/* allocate space for pptable */
|
||||||
|
smu_allocate_memory(smumgr->device,
|
||||||
|
sizeof(PPTable_t),
|
||||||
|
CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
|
||||||
|
PAGE_SIZE,
|
||||||
|
&mc_addr,
|
||||||
|
&kaddr,
|
||||||
|
&handle);
|
||||||
|
|
||||||
|
PP_ASSERT_WITH_CODE(kaddr,
|
||||||
|
"[vega10_smu_init] Out of memory for pptable.",
|
||||||
|
kfree(smumgr->backend);
|
||||||
|
cgs_free_gpu_mem(smumgr->device,
|
||||||
|
(cgs_handle_t)handle);
|
||||||
|
return -1);
|
||||||
|
|
||||||
|
priv->smu_tables.entry[PPTABLE].version = 0x01;
|
||||||
|
priv->smu_tables.entry[PPTABLE].size = sizeof(PPTable_t);
|
||||||
|
priv->smu_tables.entry[PPTABLE].table_id = TABLE_PPTABLE;
|
||||||
|
priv->smu_tables.entry[PPTABLE].table_addr_high =
|
||||||
|
smu_upper_32_bits(mc_addr);
|
||||||
|
priv->smu_tables.entry[PPTABLE].table_addr_low =
|
||||||
|
smu_lower_32_bits(mc_addr);
|
||||||
|
priv->smu_tables.entry[PPTABLE].table = kaddr;
|
||||||
|
priv->smu_tables.entry[PPTABLE].handle = handle;
|
||||||
|
|
||||||
|
/* allocate space for watermarks table */
|
||||||
|
smu_allocate_memory(smumgr->device,
|
||||||
|
sizeof(Watermarks_t),
|
||||||
|
CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
|
||||||
|
PAGE_SIZE,
|
||||||
|
&mc_addr,
|
||||||
|
&kaddr,
|
||||||
|
&handle);
|
||||||
|
|
||||||
|
PP_ASSERT_WITH_CODE(kaddr,
|
||||||
|
"[vega10_smu_init] Out of memory for wmtable.",
|
||||||
|
kfree(smumgr->backend);
|
||||||
|
cgs_free_gpu_mem(smumgr->device,
|
||||||
|
(cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle);
|
||||||
|
cgs_free_gpu_mem(smumgr->device,
|
||||||
|
(cgs_handle_t)handle);
|
||||||
|
return -1);
|
||||||
|
|
||||||
|
priv->smu_tables.entry[WMTABLE].version = 0x01;
|
||||||
|
priv->smu_tables.entry[WMTABLE].size = sizeof(Watermarks_t);
|
||||||
|
priv->smu_tables.entry[WMTABLE].table_id = TABLE_WATERMARKS;
|
||||||
|
priv->smu_tables.entry[WMTABLE].table_addr_high =
|
||||||
|
smu_upper_32_bits(mc_addr);
|
||||||
|
priv->smu_tables.entry[WMTABLE].table_addr_low =
|
||||||
|
smu_lower_32_bits(mc_addr);
|
||||||
|
priv->smu_tables.entry[WMTABLE].table = kaddr;
|
||||||
|
priv->smu_tables.entry[WMTABLE].handle = handle;
|
||||||
|
|
||||||
|
/* allocate space for AVFS table */
|
||||||
|
smu_allocate_memory(smumgr->device,
|
||||||
|
sizeof(AvfsTable_t),
|
||||||
|
CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
|
||||||
|
PAGE_SIZE,
|
||||||
|
&mc_addr,
|
||||||
|
&kaddr,
|
||||||
|
&handle);
|
||||||
|
|
||||||
|
PP_ASSERT_WITH_CODE(kaddr,
|
||||||
|
"[vega10_smu_init] Out of memory for avfs table.",
|
||||||
|
kfree(smumgr->backend);
|
||||||
|
cgs_free_gpu_mem(smumgr->device,
|
||||||
|
(cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle);
|
||||||
|
cgs_free_gpu_mem(smumgr->device,
|
||||||
|
(cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle);
|
||||||
|
cgs_free_gpu_mem(smumgr->device,
|
||||||
|
(cgs_handle_t)handle);
|
||||||
|
return -1);
|
||||||
|
|
||||||
|
priv->smu_tables.entry[AVFSTABLE].version = 0x01;
|
||||||
|
priv->smu_tables.entry[AVFSTABLE].size = sizeof(AvfsTable_t);
|
||||||
|
priv->smu_tables.entry[AVFSTABLE].table_id = TABLE_AVFS;
|
||||||
|
priv->smu_tables.entry[AVFSTABLE].table_addr_high =
|
||||||
|
smu_upper_32_bits(mc_addr);
|
||||||
|
priv->smu_tables.entry[AVFSTABLE].table_addr_low =
|
||||||
|
smu_lower_32_bits(mc_addr);
|
||||||
|
priv->smu_tables.entry[AVFSTABLE].table = kaddr;
|
||||||
|
priv->smu_tables.entry[AVFSTABLE].handle = handle;
|
||||||
|
|
||||||
|
tools_size = 0;
|
||||||
|
if (tools_size) {
|
||||||
|
smu_allocate_memory(smumgr->device,
|
||||||
|
tools_size,
|
||||||
|
CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
|
||||||
|
PAGE_SIZE,
|
||||||
|
&mc_addr,
|
||||||
|
&kaddr,
|
||||||
|
&handle);
|
||||||
|
|
||||||
|
if (kaddr) {
|
||||||
|
priv->smu_tables.entry[TOOLSTABLE].version = 0x01;
|
||||||
|
priv->smu_tables.entry[TOOLSTABLE].size = tools_size;
|
||||||
|
priv->smu_tables.entry[TOOLSTABLE].table_id = TABLE_PMSTATUSLOG;
|
||||||
|
priv->smu_tables.entry[TOOLSTABLE].table_addr_high =
|
||||||
|
smu_upper_32_bits(mc_addr);
|
||||||
|
priv->smu_tables.entry[TOOLSTABLE].table_addr_low =
|
||||||
|
smu_lower_32_bits(mc_addr);
|
||||||
|
priv->smu_tables.entry[TOOLSTABLE].table = kaddr;
|
||||||
|
priv->smu_tables.entry[TOOLSTABLE].handle = handle;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int vega10_smu_fini(struct pp_smumgr *smumgr)
|
||||||
|
{
|
||||||
|
struct vega10_smumgr *priv =
|
||||||
|
(struct vega10_smumgr *)(smumgr->backend);
|
||||||
|
|
||||||
|
if (priv) {
|
||||||
|
cgs_free_gpu_mem(smumgr->device,
|
||||||
|
(cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle);
|
||||||
|
cgs_free_gpu_mem(smumgr->device,
|
||||||
|
(cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle);
|
||||||
|
cgs_free_gpu_mem(smumgr->device,
|
||||||
|
(cgs_handle_t)priv->smu_tables.entry[AVFSTABLE].handle);
|
||||||
|
if (priv->smu_tables.entry[TOOLSTABLE].table)
|
||||||
|
cgs_free_gpu_mem(smumgr->device,
|
||||||
|
(cgs_handle_t)priv->smu_tables.entry[TOOLSTABLE].handle);
|
||||||
|
kfree(smumgr->backend);
|
||||||
|
smumgr->backend = NULL;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int vega10_start_smu(struct pp_smumgr *smumgr)
|
||||||
|
{
|
||||||
|
PP_ASSERT_WITH_CODE(!vega10_verify_smc_interface(smumgr),
|
||||||
|
"Failed to verify SMC interface!",
|
||||||
|
return -1);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
const struct pp_smumgr_func vega10_smu_funcs = {
|
||||||
|
.smu_init = &vega10_smu_init,
|
||||||
|
.smu_fini = &vega10_smu_fini,
|
||||||
|
.start_smu = &vega10_start_smu,
|
||||||
|
.request_smu_load_specific_fw = NULL,
|
||||||
|
.send_msg_to_smc = &vega10_send_msg_to_smc,
|
||||||
|
.send_msg_to_smc_with_parameter = &vega10_send_msg_to_smc_with_parameter,
|
||||||
|
.download_pptable_settings = NULL,
|
||||||
|
.upload_pptable_settings = NULL,
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,70 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2016 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
|
* copy of this software and associated documentation files (the "Software"),
|
||||||
|
* to deal in the Software without restriction, including without limitation
|
||||||
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||||
|
* and/or sell copies of the Software, and to permit persons to whom the
|
||||||
|
* Software is furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
|
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||||
|
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||||
|
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||||
|
* OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#ifndef _VEGA10_SMUMANAGER_H_
|
||||||
|
#define _VEGA10_SMUMANAGER_H_
|
||||||
|
|
||||||
|
#include "vega10_hwmgr.h"
|
||||||
|
|
||||||
|
enum smu_table_id {
|
||||||
|
PPTABLE = 0,
|
||||||
|
WMTABLE,
|
||||||
|
AVFSTABLE,
|
||||||
|
TOOLSTABLE,
|
||||||
|
MAX_SMU_TABLE,
|
||||||
|
};
|
||||||
|
|
||||||
|
struct smu_table_entry {
|
||||||
|
uint32_t version;
|
||||||
|
uint32_t size;
|
||||||
|
uint32_t table_id;
|
||||||
|
uint32_t table_addr_high;
|
||||||
|
uint32_t table_addr_low;
|
||||||
|
uint8_t *table;
|
||||||
|
unsigned long handle;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct smu_table_array {
|
||||||
|
struct smu_table_entry entry[MAX_SMU_TABLE];
|
||||||
|
};
|
||||||
|
|
||||||
|
struct vega10_smumgr {
|
||||||
|
struct smu_table_array smu_tables;
|
||||||
|
};
|
||||||
|
|
||||||
|
int vega10_read_arg_from_smc(struct pp_smumgr *smumgr, uint32_t *arg);
|
||||||
|
int vega10_copy_table_from_smc(struct pp_smumgr *smumgr,
|
||||||
|
uint8_t *table, int16_t table_id);
|
||||||
|
int vega10_copy_table_to_smc(struct pp_smumgr *smumgr,
|
||||||
|
uint8_t *table, int16_t table_id);
|
||||||
|
int vega10_enable_smc_features(struct pp_smumgr *smumgr,
|
||||||
|
bool enable, uint32_t feature_mask);
|
||||||
|
int vega10_get_smc_features(struct pp_smumgr *smumgr,
|
||||||
|
uint32_t *features_enabled);
|
||||||
|
int vega10_save_vft_table(struct pp_smumgr *smumgr, uint8_t *avfs_table);
|
||||||
|
int vega10_restore_vft_table(struct pp_smumgr *smumgr, uint8_t *avfs_table);
|
||||||
|
int vega10_perform_btc(struct pp_smumgr *smumgr);
|
||||||
|
|
||||||
|
int vega10_set_tools_address(struct pp_smumgr *smumgr);
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
Loading…
Reference in New Issue