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A lot of fixes related to the dt-binding yaml conversion, 

power-domain additions for rk322x and rk3036 and the missing
 mmc aliases move to board files on rk3066/rk3188.
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Merge tag 'v5.14-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt

A lot of fixes related to the dt-binding yaml conversion,
power-domain additions for rk322x and rk3036 and the missing
mmc aliases move to board files on rk3066/rk3188.

* tag 'v5.14-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: rockchip: add power controller for RK322x
  ARM: dts: rockchip: add power controller for RK3036
  ARM: dts: rockchip: add labels to the timer nodes on rk3066a
  ARM: dts: rockchip: fix supply properties in io-domains nodes
  ARM: dts: rockchip: remove #phy-cells from usbphy node rk3066/rk3188
  ARM: dts: rockchip: rename nodename for phy-rockchip-inno-usb2
  ARM: dts: rockchip: move mmc aliases to board dts on rk3066/rk3188
  ARM: dts: rockchip: move and restyle grf nodes rk3066/rk3188
  ARM: dts: rockchip: rename vcc_stdby node name for rk3066a-rayeager.dts
  ARM: dts: rockchip: Remove more clock-names from PWM nodes
  ARM: dts: rockchip: add #power-domain-cells to power domain nodes
  ARM: dts: rockchip: Fix power-controller node names for rk3288
  ARM: dts: rockchip: Fix power-controller node names for rk3188
  ARM: dts: rockchip: Fix power-controller node names for rk3066a
  ARM: dts: rockchip: Remove useless interrupt-names on IOMMU node on rk3036
  ARM: dts: rockchip: Fix IOMMU nodes properties on rk322x
  ARM: dts: rockchip: Fix the timer clocks order
  ARM: dts: rockchip: fix pinctrl sleep nodename for rk3036-kylin and rk3288
  ARM: dts: rockchip: Fix thermal sensor cells o rk322x

Link: https://lore.kernel.org/r/2084346.irdbgypaU6@phil
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2021-06-23 18:58:56 -07:00
parent 43b3219861 623ba75a5d
commit f82c6e6dd1
17 changed files with 295 additions and 93 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/rk3036-kylin.dts
View File

@ -390,7 +390,7 @@
};
};
sleep {
suspend {
global_pwroff: global-pwroff {
rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>;
};

51
arch/arm/boot/dts/rk3036.dtsi
View File

@ -6,6 +6,7 @@
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3036-cru.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/power/rk3036-power.h>
/ {
#address-cells = <1>;
@ -111,6 +112,7 @@
assigned-clock-rates = <100000000>;
clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
clock-names = "bus", "core";
power-domains = <&power RK3036_PD_GPU>;
resets = <&cru SRST_GPU>;
status = "disabled";
};
@ -124,6 +126,7 @@
resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
reset-names = "axi", "ahb", "dclk";
iommus = <&vop_mmu>;
power-domains = <&power RK3036_PD_VIO>;
status = "disabled";
vop_out: port {
@ -140,13 +143,28 @@
compatible = "rockchip,iommu";
reg = <0x10118300 0x100>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vop_mmu";
clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>;
clock-names = "aclk", "iface";
power-domains = <&power RK3036_PD_VIO>;
#iommu-cells = <0>;
status = "disabled";
};
qos_gpu: qos@1012d000 {
compatible = "rockchip,rk3036-qos", "syscon";
reg = <0x1012d000 0x20>;
};
qos_vpu: qos@1012e000 {
compatible = "rockchip,rk3036-qos", "syscon";
reg = <0x1012e000 0x20>;
};
qos_vio: qos@1012f000 {
compatible = "rockchip,rk3036-qos", "syscon";
reg = <0x1012f000 0x20>;
};
gic: interrupt-controller@10139000 {
compatible = "arm,gic-400";
interrupt-controller;
@ -302,6 +320,37 @@
compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
reg = <0x20008000 0x1000>;
power: power-controller {
compatible = "rockchip,rk3036-power-controller";
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
power-domain@RK3036_PD_VIO {
reg = <RK3036_PD_VIO>;
clocks = <&cru ACLK_LCDC>,
<&cru HCLK_LCDC>,
<&cru SCLK_LCDC>;
pm_qos = <&qos_vio>;
#power-domain-cells = <0>;
};
power-domain@RK3036_PD_VPU {
reg = <RK3036_PD_VPU>;
clocks = <&cru ACLK_VCODEC>,
<&cru HCLK_VCODEC>;
pm_qos = <&qos_vpu>;
#power-domain-cells = <0>;
};
power-domain@RK3036_PD_GPU {
reg = <RK3036_PD_GPU>;
clocks = <&cru SCLK_GPU>;
pm_qos = <&qos_gpu>;
#power-domain-cells = <0>;
};
};
reboot-mode {
compatible = "syscon-reboot-mode";
offset = <0x1d8>;

5
arch/arm/boot/dts/rk3066a-bqcurie2.dts
View File

@ -12,6 +12,11 @@
model = "bq Curie 2";
compatible = "mundoreader,bq-curie2", "rockchip,rk3066a";
aliases {
mmc0 = &mmc0;
mmc1 = &mmc1;
};
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x40000000>;

4
arch/arm/boot/dts/rk3066a-marsboard.dts
View File

@ -10,6 +10,10 @@
model = "MarsBoard RK3066";
compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a";
aliases {
mmc0 = &mmc0;
};
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x40000000>;

5
arch/arm/boot/dts/rk3066a-mk808.dts
View File

@ -10,6 +10,11 @@
model = "Rikomagic MK808";
compatible = "rikomagic,mk808", "rockchip,rk3066a";
aliases {
mmc0 = &mmc0;
mmc1 = &mmc1;
};
chosen {
stdout-path = "serial2:115200n8";
};

8
arch/arm/boot/dts/rk3066a-rayeager.dts
View File

@ -11,6 +11,12 @@
model = "Rayeager PX2";
compatible = "chipspark,rayeager-px2", "rockchip,rk3066a";
aliases {
mmc0 = &mmc0;
mmc1 = &mmc1;
mmc2 = &emmc;
};
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x40000000>;
@ -58,7 +64,7 @@
};
/* input for 5V_STDBY is VSYS or DC5V, selectable by jumper J4 */
vcc_stdby: 5v-stdby-regulator {
vcc_stdby: stdby-regulator {
compatible = "regulator-fixed";
regulator-name = "5v_stdby";
regulator-min-microvolt = <5000000>;

67
arch/arm/boot/dts/rk3066a.dtsi
View File

@ -217,7 +217,7 @@
<150000000>, <75000000>;
};
timer@2000e000 {
timer2: timer@2000e000 {
compatible = "snps,dw-apb-timer-osc";
reg = <0x2000e000 0x100>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
@ -238,7 +238,7 @@
};
};
timer@20038000 {
timer0: timer@20038000 {
compatible = "snps,dw-apb-timer-osc";
reg = <0x20038000 0x100>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
@ -246,7 +246,7 @@
clock-names = "timer", "pclk";
};
timer@2003a000 {
timer1: timer@2003a000 {
compatible = "snps,dw-apb-timer-osc";
reg = <0x2003a000 0x100>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
@ -266,30 +266,6 @@
status = "disabled";
};
usbphy: phy {
compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy";
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
usbphy0: usb-phy@17c {
#phy-cells = <0>;
reg = <0x17c>;
clocks = <&cru SCLK_OTGPHY0>;
clock-names = "phyclk";
#clock-cells = <0>;
};
usbphy1: usb-phy@188 {
#phy-cells = <0>;
reg = <0x188>;
clocks = <&cru SCLK_OTGPHY1>;
clock-names = "phyclk";
#clock-cells = <0>;
};
};
pinctrl: pinctrl {
compatible = "rockchip,rk3066a-pinctrl";
rockchip,grf = <&grf>;
@ -702,6 +678,34 @@
power-domains = <&power RK3066_PD_GPU>;
};
&grf {
compatible = "rockchip,rk3066-grf", "syscon", "simple-mfd";
usbphy: usbphy {
compatible = "rockchip,rk3066a-usb-phy",
"rockchip,rk3288-usb-phy";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
usbphy0: usb-phy@17c {
reg = <0x17c>;
clocks = <&cru SCLK_OTGPHY0>;
clock-names = "phyclk";
#clock-cells = <0>;
#phy-cells = <0>;
};
usbphy1: usb-phy@188 {
reg = <0x188>;
clocks = <&cru SCLK_OTGPHY1>;
clock-names = "phyclk";
#clock-cells = <0>;
#phy-cells = <0>;
};
};
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_xfer>;
@ -755,7 +759,7 @@
#address-cells = <1>;
#size-cells = <0>;
pd_vio@RK3066_PD_VIO {
power-domain@RK3066_PD_VIO {
reg = <RK3066_PD_VIO>;
clocks = <&cru ACLK_LCDC0>,
<&cru ACLK_LCDC1>,
@ -780,21 +784,24 @@
<&qos_cif1>,
<&qos_ipp>,
<&qos_rga>;
#power-domain-cells = <0>;
};
pd_video@RK3066_PD_VIDEO {
power-domain@RK3066_PD_VIDEO {
reg = <RK3066_PD_VIDEO>;
clocks = <&cru ACLK_VDPU>,
<&cru ACLK_VEPU>,
<&cru HCLK_VDPU>,
<&cru HCLK_VEPU>;
pm_qos = <&qos_vpu>;
#power-domain-cells = <0>;
};
pd_gpu@RK3066_PD_GPU {
power-domain@RK3066_PD_GPU {
reg = <RK3066_PD_GPU>;
clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu>;
#power-domain-cells = <0>;
};
};
};

6
arch/arm/boot/dts/rk3188-bqedison2qc.dts
View File

@ -13,6 +13,12 @@
model = "BQ Edison2 Quad-Core";
compatible = "mundoreader,bq-edison2qc", "rockchip,rk3188";
aliases {
mmc0 = &mmc0;
mmc1 = &mmc1;
mmc2 = &emmc;
};
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x80000000>;

5
arch/arm/boot/dts/rk3188-px3-evb.dts
View File

@ -11,6 +11,11 @@
model = "Rockchip PX3-EVB";
compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188";
aliases {
mmc0 = &mmc0;
mmc1 = &emmc;
};
chosen {
stdout-path = "serial2:115200n8";
};

4
arch/arm/boot/dts/rk3188-radxarock.dts
View File

@ -11,6 +11,10 @@
model = "Radxa Rock";
compatible = "radxa,rock", "rockchip,rk3188";
aliases {
mmc0 = &mmc0;
};
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x80000000>;

69
arch/arm/boot/dts/rk3188.dtsi
View File

@ -150,16 +150,16 @@
compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
reg = <0x2000e000 0x20>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_TIMER3>, <&cru PCLK_TIMER3>;
clock-names = "timer", "pclk";
clocks = <&cru PCLK_TIMER3>, <&cru SCLK_TIMER3>;
clock-names = "pclk", "timer";
};
timer6: timer@200380a0 {
compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
reg = <0x200380a0 0x20>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_TIMER6>, <&cru PCLK_TIMER0>;
clock-names = "timer", "pclk";
clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER6>;
clock-names = "pclk", "timer";
};
i2s0: i2s@1011a000 {
@ -214,30 +214,6 @@
};
};
usbphy: phy {
compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
usbphy0: usb-phy@10c {
#phy-cells = <0>;
reg = <0x10c>;
clocks = <&cru SCLK_OTGPHY0>;
clock-names = "phyclk";
#clock-cells = <0>;
};
usbphy1: usb-phy@11c {
#phy-cells = <0>;
reg = <0x11c>;
clocks = <&cru SCLK_OTGPHY1>;
clock-names = "phyclk";
#clock-cells = <0>;
};
};
pinctrl: pinctrl {
compatible = "rockchip,rk3188-pinctrl";
rockchip,grf = <&grf>;
@ -662,6 +638,34 @@
power-domains = <&power RK3188_PD_GPU>;
};
&grf{
compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd";
usbphy: usbphy {
compatible = "rockchip,rk3188-usb-phy",
"rockchip,rk3288-usb-phy";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
usbphy0: usb-phy@10c {
reg = <0x10c>;
clocks = <&cru SCLK_OTGPHY0>;
clock-names = "phyclk";
#clock-cells = <0>;
#phy-cells = <0>;
};
usbphy1: usb-phy@11c {
reg = <0x11c>;
clocks = <&cru SCLK_OTGPHY1>;
clock-names = "phyclk";
#clock-cells = <0>;
#phy-cells = <0>;
};
};
};
&i2c0 {
compatible = "rockchip,rk3188-i2c";
pinctrl-names = "default";
@ -699,7 +703,7 @@
#address-cells = <1>;
#size-cells = <0>;
pd_vio@RK3188_PD_VIO {
power-domain@RK3188_PD_VIO {
reg = <RK3188_PD_VIO>;
clocks = <&cru ACLK_LCDC0>,
<&cru ACLK_LCDC1>,
@ -719,21 +723,24 @@
<&qos_cif0>,
<&qos_ipp>,
<&qos_rga>;
#power-domain-cells = <0>;
};
pd_video@RK3188_PD_VIDEO {
power-domain@RK3188_PD_VIDEO {
reg = <RK3188_PD_VIDEO>;
clocks = <&cru ACLK_VDPU>,
<&cru ACLK_VEPU>,
<&cru HCLK_VDPU>,
<&cru HCLK_VEPU>;
pm_qos = <&qos_vpu>;
#power-domain-cells = <0>;
};
pd_gpu@RK3188_PD_GPU {
power-domain@RK3188_PD_GPU {
reg = <RK3188_PD_GPU>;
clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu>;
#power-domain-cells = <0>;
};
};
};

131
arch/arm/boot/dts/rk322x.dtsi
View File

@ -6,6 +6,7 @@
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3228-cru.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/power/rk3228-power.h>
/ {
#address-cells = <1>;
@ -190,7 +191,65 @@
status = "disabled";
};
u2phy0: usb2-phy@760 {
power: power-controller {
compatible = "rockchip,rk3228-power-controller";
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
power-domain@RK3228_PD_VIO {
reg = <RK3228_PD_VIO>;
clocks = <&cru ACLK_HDCP>,
<&cru SCLK_HDCP>,
<&cru ACLK_IEP>,
<&cru HCLK_IEP>,
<&cru ACLK_RGA>,
<&cru HCLK_RGA>,
<&cru SCLK_RGA>;
pm_qos = <&qos_hdcp>,
<&qos_iep>,
<&qos_rga_r>,
<&qos_rga_w>;
#power-domain-cells = <0>;
};
power-domain@RK3228_PD_VOP {
reg = <RK3228_PD_VOP>;
clocks =<&cru ACLK_VOP>,
<&cru DCLK_VOP>,
<&cru HCLK_VOP>;
pm_qos = <&qos_vop>;
#power-domain-cells = <0>;
};
power-domain@RK3228_PD_VPU {
reg = <RK3228_PD_VPU>;
clocks = <&cru ACLK_VPU>,
<&cru HCLK_VPU>;
pm_qos = <&qos_vpu>;
#power-domain-cells = <0>;
};
power-domain@RK3228_PD_RKVDEC {
reg = <RK3228_PD_RKVDEC>;
clocks = <&cru ACLK_RKVDEC>,
<&cru HCLK_RKVDEC>,
<&cru SCLK_VDEC_CABAC>,
<&cru SCLK_VDEC_CORE>;
pm_qos = <&qos_rkvdec_r>,
<&qos_rkvdec_w>;
#power-domain-cells = <0>;
};
power-domain@RK3228_PD_GPU {
reg = <RK3228_PD_GPU>;
clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu>;
#power-domain-cells = <0>;
};
};
u2phy0: usb2phy@760 {
compatible = "rockchip,rk3228-usb2phy";
reg = <0x0760 0x0c>;
clocks = <&cru SCLK_OTGPHY0>;
@ -217,7 +276,7 @@
};
};
u2phy1: usb2-phy@800 {
u2phy1: usb2phy@800 {
compatible = "rockchip,rk3228-usb2phy";
reg = <0x0800 0x0c>;
clocks = <&cru SCLK_OTGPHY1>;
@ -379,7 +438,6 @@
reg = <0x110b0000 0x10>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
status = "disabled";
@ -390,7 +448,6 @@
reg = <0x110b0010 0x10>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "default";
pinctrl-0 = <&pwm1_pin>;
status = "disabled";
@ -401,7 +458,6 @@
reg = <0x110b0020 0x10>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "default";
pinctrl-0 = <&pwm2_pin>;
status = "disabled";
@ -412,7 +468,6 @@
reg = <0x110b0030 0x10>;
#pwm-cells = <2>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "default";
pinctrl-0 = <&pwm3_pin>;
status = "disabled";
@ -517,7 +572,7 @@
pinctrl-0 = <&otp_pin>;
pinctrl-1 = <&otp_out>;
pinctrl-2 = <&otp_pin>;
#thermal-sensor-cells = <0>;
#thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <95000>;
status = "disabled";
};
@ -550,6 +605,7 @@
"ppmmu1";
clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
clock-names = "bus", "core";
power-domains = <&power RK3228_PD_GPU>;
resets = <&cru SRST_GPU_A>;
status = "disabled";
};
@ -558,10 +614,10 @@
compatible = "rockchip,iommu";
reg = <0x20020800 0x100>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vpu_mmu";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk", "iface";
iommu-cells = <0>;
power-domains = <&power RK3228_PD_VPU>;
#iommu-cells = <0>;
status = "disabled";
};
@ -569,10 +625,10 @@
compatible = "rockchip,iommu";
reg = <0x20030480 0x40>, <0x200304c0 0x40>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vdec_mmu";
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
clock-names = "aclk", "iface";
iommu-cells = <0>;
power-domains = <&power RK3228_PD_RKVDEC>;
#iommu-cells = <0>;
status = "disabled";
};
@ -585,6 +641,7 @@
resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
reset-names = "axi", "ahb", "dclk";
iommus = <&vop_mmu>;
power-domains = <&power RK3228_PD_VOP>;
status = "disabled";
vop_out: port {
@ -602,9 +659,9 @@
compatible = "rockchip,iommu";
reg = <0x20053f00 0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vop_mmu";
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
clock-names = "aclk", "iface";
power-domains = <&power RK3228_PD_VOP>;
#iommu-cells = <0>;
status = "disabled";
};
@ -615,6 +672,7 @@
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
clock-names = "aclk", "hclk", "sclk";
power-domains = <&power RK3228_PD_VIO>;
resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>;
reset-names = "core", "axi", "ahb";
};
@ -623,10 +681,10 @@
compatible = "rockchip,iommu";
reg = <0x20070800 0x100>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "iep_mmu";
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk", "iface";
iommu-cells = <0>;
power-domains = <&power RK3228_PD_VIO>;
#iommu-cells = <0>;
status = "disabled";
};
@ -800,6 +858,51 @@
status = "disabled";
};
qos_iep: qos@31030080 {
compatible = "rockchip,rk3228-qos", "syscon";
reg = <0x31030080 0x20>;
};
qos_rga_w: qos@31030100 {
compatible = "rockchip,rk3228-qos", "syscon";
reg = <0x31030100 0x20>;
};
qos_hdcp: qos@31030180 {
compatible = "rockchip,rk3228-qos", "syscon";
reg = <0x31030180 0x20>;
};
qos_rga_r: qos@31030200 {
compatible = "rockchip,rk3228-qos", "syscon";
reg = <0x31030200 0x20>;
};
qos_vpu: qos@31040000 {
compatible = "rockchip,rk3228-qos", "syscon";
reg = <0x31040000 0x20>;
};
qos_gpu: qos@31050000 {
compatible = "rockchip,rk3228-qos", "syscon";
reg = <0x31050000 0x20>;
};
qos_vop: qos@31060000 {
compatible = "rockchip,rk3228-qos", "syscon";
reg = <0x31060000 0x20>;
};
qos_rkvdec_r: qos@31070000 {
compatible = "rockchip,rk3228-qos", "syscon";
reg = <0x31070000 0x20>;
};
qos_rkvdec_w: qos@31070080 {
compatible = "rockchip,rk3228-qos", "syscon";
reg = <0x31070080 0x20>;
};
gic: interrupt-controller@32010000 {
compatible = "arm,gic-400";
interrupt-controller;

2
arch/arm/boot/dts/rk3288-rock2-som.dtsi
View File

@ -218,7 +218,7 @@
flash0-supply = <&vcc_flash>;
flash1-supply = <&vccio_pmu>;
gpio30-supply = <&vccio_pmu>;
gpio1830 = <&vcc_io>;
gpio1830-supply = <&vcc_io>;
lcdc-supply = <&vcc_io>;
sdcard-supply = <&vccio_sd>;
wifi-supply = <&vcc_18>;

4
arch/arm/boot/dts/rk3288-vyasa.dts
View File

@ -379,10 +379,10 @@
audio-supply = <&vcc_18>;
bb-supply = <&vcc_io>;
dvp-supply = <&vcc_io>;
flash0-suuply = <&vcc_18>;
flash0-supply = <&vcc_18>;
flash1-supply = <&vcc_lan>;
gpio30-supply = <&vcc_io>;
gpio1830 = <&vcc_io>;
gpio1830-supply = <&vcc_io>;
lcdc-supply = <&vcc_io>;
sdcard-supply = <&vccio_sd>;
wifi-supply = <&vcc_18>;

18
arch/arm/boot/dts/rk3288.dtsi
View File

@ -196,8 +196,8 @@
compatible = "rockchip,rk3288-timer";
reg = <0x0 0xff810000 0x0 0x20>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&xin24m>, <&cru PCLK_TIMER>;
clock-names = "timer", "pclk";
clocks = <&cru PCLK_TIMER>, <&xin24m>;
clock-names = "pclk", "timer";
};
display-subsystem {
@ -765,7 +765,7 @@
* *_HDMI HDMI
* *_MIPI_* MIPI
*/
pd_vio@RK3288_PD_VIO {
power-domain@RK3288_PD_VIO {
reg = <RK3288_PD_VIO>;
clocks = <&cru ACLK_IEP>,
<&cru ACLK_ISP>,
@ -801,19 +801,21 @@
<&qos_vio2_rga_r>,
<&qos_vio2_rga_w>,
<&qos_vio1_isp_r>;
#power-domain-cells = <0>;
};
/*
* Note: The following 3 are HEVC(H.265) clocks,
* and on the ACLK_HEVC_NIU (NOC).
*/
pd_hevc@RK3288_PD_HEVC {
power-domain@RK3288_PD_HEVC {
reg = <RK3288_PD_HEVC>;
clocks = <&cru ACLK_HEVC>,
<&cru SCLK_HEVC_CABAC>,
<&cru SCLK_HEVC_CORE>;
pm_qos = <&qos_hevc_r>,
<&qos_hevc_w>;
#power-domain-cells = <0>;
};
/*
@ -821,22 +823,24 @@
* (video endecoder & decoder) clocks that on the
* ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
*/
pd_video@RK3288_PD_VIDEO {
power-domain@RK3288_PD_VIDEO {
reg = <RK3288_PD_VIDEO>;
clocks = <&cru ACLK_VCODEC>,
<&cru HCLK_VCODEC>;
pm_qos = <&qos_video>;
#power-domain-cells = <0>;
};
/*
* Note: ACLK_GPU is the GPU clock,
* and on the ACLK_GPU_NIU (NOC).
*/
pd_gpu@RK3288_PD_GPU {
power-domain@RK3288_PD_GPU {
reg = <RK3288_PD_GPU>;
clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu_r>,
<&qos_gpu_w>;
#power-domain-cells = <0>;
};
};
@ -1582,7 +1586,7 @@
drive-strength = <12>;
};
sleep {
suspend {
global_pwroff: global-pwroff {
rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>;
};

5
arch/arm/boot/dts/rk3xxx.dtsi
View File

@ -21,9 +21,6 @@
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
mshc0 = &emmc;
mshc1 = &mmc0;
mshc2 = &mmc1;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
@ -256,7 +253,7 @@
};
grf: grf@20008000 {
compatible = "syscon";
compatible = "syscon", "simple-mfd";
reg = <0x20008000 0x200>;
};

2
arch/arm/boot/dts/rv1108.dtsi
View File

@ -265,7 +265,7 @@
#address-cells = <1>;
#size-cells = <1>;
u2phy: usb2-phy@100 {
u2phy: usb2phy@100 {
compatible = "rockchip,rv1108-usb2phy";
reg = <0x100 0x0c>;
clocks = <&cru SCLK_USBPHY>;