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staging: r8192ee: Remove staging driver 

A new version of this driver has been merged into the regular wireless tree.
The staging version is hereby removed.

Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Larry Finger 2014-09-30 09:48:19 -05:00 committed by Greg Kroah-Hartman
parent 76272ab3f3
commit f823182bc2
66 changed files with 0 additions and 50331 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/staging/Kconfig
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@ -44,8 +44,6 @@ source "drivers/staging/rtl8712/Kconfig"
source "drivers/staging/rtl8188eu/Kconfig"
source "drivers/staging/rtl8192ee/Kconfig"
source "drivers/staging/rtl8723au/Kconfig"
source "drivers/staging/rts5208/Kconfig"

1
drivers/staging/Makefile
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@ -14,7 +14,6 @@ obj-$(CONFIG_RTL8192U) += rtl8192u/
obj-$(CONFIG_RTL8192E) += rtl8192e/
obj-$(CONFIG_R8712U) += rtl8712/
obj-$(CONFIG_R8188EU) += rtl8188eu/
obj-$(CONFIG_R8192EE) += rtl8192ee/
obj-$(CONFIG_R8723AU) += rtl8723au/
obj-$(CONFIG_RTS5208) += rts5208/
obj-$(CONFIG_LINE6_USB) += line6/

14
drivers/staging/rtl8192ee/Kconfig
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@ -1,14 +0,0 @@
config R8192EE
tristate "Realtek RTL8192EE Wireless Network Adapter"
depends on PCI && WLAN && MAC80211
depends on m
select WIRELESS_EXT
select WEXT_PRIV
select EEPROM_93CX6
select CRYPTO
select FW_LOADER
---help---
This is the driver for Realtek RTL8192EE 802.11 PCIe
wireless network adapters.
If you choose to build it as a module, it will be called r8192ee

40
drivers/staging/rtl8192ee/Makefile
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@ -1,40 +0,0 @@
PCI_MAIN_OBJS := base.o \
cam.o \
core.o \
debug.o \
efuse.o \
pci.o \
ps.o \
rc.o \
regd.o \
stats.o
PCI_8192EE_HAL_OBJS:= \
rtl8192ee/dm.o \
rtl8192ee/fw.o \
rtl8192ee/hw.o \
rtl8192ee/led.o \
rtl8192ee/phy.o \
rtl8192ee/pwrseq.o \
rtl8192ee/pwrseqcmd.o \
rtl8192ee/rf.o \
rtl8192ee/sw.o \
rtl8192ee/table.o \
rtl8192ee/trx.o
BT_COEXIST_OBJS:= btcoexist/halbtc8192e2ant.o\
btcoexist/halbtc8723b1ant.o\
btcoexist/halbtc8723b2ant.o\
btcoexist/halbtc8821a1ant.o\
btcoexist/halbtc8821a2ant.o\
btcoexist/halbtcoutsrc.o\
btcoexist/rtl_btc.o
r8192ee-objs += $(PCI_MAIN_OBJS) $(PCI_8192EE_HAL_OBJS) $(BT_COEXIST_OBJS)
obj-$(CONFIG_R8192EE) += r8192ee.o
ccflags-y += -D__CHECK_ENDIAN__

12
drivers/staging/rtl8192ee/TODO
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@ -1,12 +0,0 @@
TODO:
- convert any remaining unusual variable types
- find codes that can use %pM and %Nph formatting
- checkpatch.pl fixes - most of the remaining ones are lines too long. Many
of them will require refactoring
- merge Realtek's bugfixes and new features into the driver
- Convert the versions of rtlwifi and btcoexist in drivers/net/wireless/rtlwifi/...
to work with the RTL8192EE
- move this driver to drivers/net/wireless/rtlwifi
Please send any patches to Greg Kroah-Hartman <gregkh@linux.com>,
and Larry Finger <Larry.Finger@lwfinger.net>.

1849
drivers/staging/rtl8192ee/base.c
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File diff suppressed because it is too large Load Diff

163
drivers/staging/rtl8192ee/base.h
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@ -1,163 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL_BASE_H__
#define __RTL_BASE_H__
#include "compat.h"
enum ap_peer {
PEER_UNKNOWN = 0,
PEER_RTL = 1,
PEER_RTL_92SE = 2,
PEER_BROAD = 3,
PEER_RAL = 4,
PEER_ATH = 5,
PEER_CISCO = 6,
PEER_MARV = 7,
PEER_AIRGO = 9,
PEER_MAX = 10,
};
#define RTL_DUMMY_OFFSET 0
#define RTL_DUMMY_UNIT 8
#define RTL_TX_DUMMY_SIZE (RTL_DUMMY_OFFSET * RTL_DUMMY_UNIT)
#define RTL_TX_DESC_SIZE 32
#define RTL_TX_HEADER_SIZE (RTL_TX_DESC_SIZE + RTL_TX_DUMMY_SIZE)
#define HT_AMSDU_SIZE_4K 3839
#define HT_AMSDU_SIZE_8K 7935
#define MAX_BIT_RATE_40MHZ_MCS15 300 /* Mbps */
#define MAX_BIT_RATE_40MHZ_MCS7 150 /* Mbps */
#define MAX_BIT_RATE_SHORT_GI_2NSS_80MHZ_MCS9 867 /* Mbps */
#define MAX_BIT_RATE_SHORT_GI_2NSS_80MHZ_MCS7 650 /* Mbps */
#define MAX_BIT_RATE_LONG_GI_2NSS_80MHZ_MCS9 780 /* Mbps */
#define MAX_BIT_RATE_LONG_GI_2NSS_80MHZ_MCS7 585 /* Mbps */
#define MAX_BIT_RATE_SHORT_GI_1NSS_80MHZ_MCS9 434 /* Mbps */
#define MAX_BIT_RATE_SHORT_GI_1NSS_80MHZ_MCS7 325 /* Mbps */
#define MAX_BIT_RATE_LONG_GI_1NSS_80MHZ_MCS9 390 /* Mbps */
#define MAX_BIT_RATE_LONG_GI_1NSS_80MHZ_MCS7 293 /* Mbps */
#define RTL_RATE_COUNT_LEGACY 12
#define RTL_CHANNEL_COUNT 14
#define FRAME_OFFSET_FRAME_CONTROL 0
#define FRAME_OFFSET_DURATION 2
#define FRAME_OFFSET_ADDRESS1 4
#define FRAME_OFFSET_ADDRESS2 10
#define FRAME_OFFSET_ADDRESS3 16
#define FRAME_OFFSET_SEQUENCE 22
#define FRAME_OFFSET_ADDRESS4 24
#define SET_80211_HDR_FRAME_CONTROL(_hdr, _val) \
WRITEEF2BYTE(_hdr, _val)
#define SET_80211_HDR_TYPE_AND_SUBTYPE(_hdr, _val) \
WRITEEF1BYTE(_hdr, _val)
#define SET_80211_HDR_PWR_MGNT(_hdr, _val) \
SET_BITS_TO_LE_2BYTE(_hdr, 12, 1, _val)
#define SET_80211_HDR_TO_DS(_hdr, _val) \
SET_BITS_TO_LE_2BYTE(_hdr, 8, 1, _val)
#define SET_80211_PS_POLL_AID(_hdr, _val) \
(*(u16 *)((u8 *)(_hdr) + 2) = _val)
#define SET_80211_PS_POLL_BSSID(_hdr, _val) \
memcpy(((u8 *)(_hdr)) + 4, (u8 *)(_val), ETH_ALEN)
#define SET_80211_PS_POLL_TA(_hdr, _val) \
memcpy(((u8 *)(_hdr)) + 10, (u8 *)(_val), ETH_ALEN)
#define SET_80211_HDR_DURATION(_hdr, _val) \
WRITEEF2BYTE((u8 *)(_hdr)+FRAME_OFFSET_DURATION, _val)
#define SET_80211_HDR_ADDRESS1(_hdr, _val) \
CP_MACADDR((u8 *)(_hdr)+FRAME_OFFSET_ADDRESS1, (u8 *)(_val))
#define SET_80211_HDR_ADDRESS2(_hdr, _val) \
CP_MACADDR((u8 *)(_hdr)+FRAME_OFFSET_ADDRESS2, (u8 *)(_val))
#define SET_80211_HDR_ADDRESS3(_hdr, _val) \
CP_MACADDR((u8 *)(_hdr)+FRAME_OFFSET_ADDRESS3, (u8 *)(_val))
#define SET_80211_HDR_FRAGMENT_SEQUENCE(_hdr, _val) \
WRITEEF2BYTE((u8 *)(_hdr)+FRAME_OFFSET_SEQUENCE, _val)
#define SET_BEACON_PROBE_RSP_TIME_STAMP_LOW(__phdr, __val) \
WRITEEF4BYTE(((u8 *)(__phdr)) + 24, __val)
#define SET_BEACON_PROBE_RSP_TIME_STAMP_HIGH(__phdr, __val) \
WRITEEF4BYTE(((u8 *)(__phdr)) + 28, __val)
#define SET_BEACON_PROBE_RSP_BEACON_INTERVAL(__phdr, __val) \
WRITEEF2BYTE(((u8 *)(__phdr)) + 32, __val)
#define GET_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr) \
READEF2BYTE(((u8 *)(__phdr)) + 34)
#define SET_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr, __val) \
WRITEEF2BYTE(((u8 *)(__phdr)) + 34, __val)
#define MASK_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr, __val) \
SET_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr, \
(GET_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr) & (~(__val))))
int rtl92e_init_core(struct ieee80211_hw *hw);
void rtl92e_deinit_core(struct ieee80211_hw *hw);
void rtl92e_init_rx_config(struct ieee80211_hw *hw);
void rtl92e_init_rfkill(struct ieee80211_hw *hw);
void rtl92e_deinit_rfkill(struct ieee80211_hw *hw);
void rtl92e_watch_dog_timer_callback(unsigned long data);
void rtl92e_deinit_deferred_work(struct ieee80211_hw *hw);
bool rtl92e_action_proc(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx);
bool rtl92e_tx_mgmt_proc(struct ieee80211_hw *hw, struct sk_buff *skb);
u8 rtl92e_is_special_data(struct ieee80211_hw *hw, struct sk_buff *skb,
u8 is_tx);
void rtl92e_beacon_statistic(struct ieee80211_hw *hw, struct sk_buff *skb);
void rtl92e_watch_dog_timer_callback(unsigned long data);
int rtl92e_tx_agg_start(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
struct ieee80211_sta *sta, u16 tid, u16 *ssn);
int rtl92e_tx_agg_stop(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
struct ieee80211_sta *sta, u16 tid);
int rtl92e_tx_agg_oper(struct ieee80211_hw *hw,
struct ieee80211_sta *sta, u16 tid);
int rtl92e_rx_agg_start(struct ieee80211_hw *hw,
struct ieee80211_sta *sta, u16 tid);
int rtl92e_rx_agg_stop(struct ieee80211_hw *hw,
struct ieee80211_sta *sta, u16 tid);
void rtl92e_watchdog_wq_callback(void *data);
void rtl92e_fwevt_wq_callback(void *data);
void stg_rtl_get_tcb_desc(struct ieee80211_hw *hw,
struct ieee80211_tx_info *info,
struct ieee80211_sta *sta,
struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc);
int stg_rtl_send_smps_action(struct ieee80211_hw *hw,
struct ieee80211_sta *sta,
enum ieee80211_smps_mode smps);
u8 *rtl92e_find_ie(u8 *data, unsigned int len, u8 ie);
void rtl92e_recognize_peer(struct ieee80211_hw *hw, u8 *data, unsigned int len);
u8 rtl92e_tid_to_ac(struct ieee80211_hw *hw, u8 tid);
void rtl92e_easy_concurrent_retrytimer_callback(unsigned long data);
extern struct rtl_global_var global_var;
int rtl_core_module_init(void);
void rtl_core_module_exit(void);
#endif

50
drivers/staging/rtl8192ee/btcoexist/halbt_precomp.h
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@ -1,50 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*
******************************************************************************/
#ifndef __HALBT_PRECOMP_H__
#define __HALBT_PRECOMP_H__
/*************************************************************
* include files
*************************************************************/
#include "../wifi.h"
#include "../efuse.h"
#include "../base.h"
#include "../regd.h"
#include "../cam.h"
#include "../ps.h"
#include "../pci.h"
#include "halbtcoutsrc.h"
#include "halbtc8192e2ant.h"
#include "halbtc8723b1ant.h"
#include "halbtc8723b2ant.h"
#include "halbtc8821a2ant.h"
#include "halbtc8821a1ant.h"
#define MASKBYTE0 0xff
#define MASKBYTE1 0xff00
#define MASKBYTE2 0xff0000
#define MASKBYTE3 0xff000000
#define MASKHWORD 0xffff0000
#define MASKLWORD 0x0000ffff
#define MASKDWORD 0xffffffff
#define MASK12BITS 0xfff
#define MASKH4BITS 0xf0000000
#define MASKOFDM_D 0xffc00000
#define MASKCCK 0x3f3f3f3f
#endif /* __HALBT_PRECOMP_H__ */

4110
drivers/staging/rtl8192ee/btcoexist/halbtc8192e2ant.c
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File diff suppressed because it is too large Load Diff

161
drivers/staging/rtl8192ee/btcoexist/halbtc8192e2ant.h
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@ -1,161 +0,0 @@
/*****************************************************************
* The following is for 8192E 2Ant BT Co-exist definition
*****************************************************************/
#define BT_AUTO_REPORT_ONLY_8192E_2ANT 0
#define BT_INFO_8192E_2ANT_B_FTP BIT(7)
#define BT_INFO_8192E_2ANT_B_A2DP BIT(6)
#define BT_INFO_8192E_2ANT_B_HID BIT(5)
#define BT_INFO_8192E_2ANT_B_SCO_BUSY BIT(4)
#define BT_INFO_8192E_2ANT_B_ACL_BUSY BIT(3)
#define BT_INFO_8192E_2ANT_B_INQ_PAGE BIT(2)
#define BT_INFO_8192E_2ANT_B_SCO_ESCO BIT(1)
#define BT_INFO_8192E_2ANT_B_CONNECTION BIT(0)
#define BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT 2
enum bt_info_src_8192e_2ant {
BT_INFO_SRC_8192E_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8192E_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8192E_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8192E_2ANT_MAX
};
enum bt_8192e_2ant_bt_status {
BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8192E_2ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8192E_2ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8192E_2ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8192E_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8192E_2ANT_BT_STATUS_MAX
};
enum bt_8192e_2ant_coex_algo {
BT_8192E_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8192E_2ANT_COEX_ALGO_SCO = 0x1,
BT_8192E_2ANT_COEX_ALGO_SCO_PAN = 0x2,
BT_8192E_2ANT_COEX_ALGO_HID = 0x3,
BT_8192E_2ANT_COEX_ALGO_A2DP = 0x4,
BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS = 0x5,
BT_8192E_2ANT_COEX_ALGO_PANEDR = 0x6,
BT_8192E_2ANT_COEX_ALGO_PANHS = 0x7,
BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP = 0x8,
BT_8192E_2ANT_COEX_ALGO_PANEDR_HID = 0x9,
BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0xa,
BT_8192E_2ANT_COEX_ALGO_HID_A2DP = 0xb,
BT_8192E_2ANT_COEX_ALGO_MAX = 0xc
};
struct coex_dm_8192e_2ant {
/* fw mechanism */
u8 pre_dec_bt_pwr;
u8 cur_dec_bt_pwr;
u8 pre_fw_dac_swing_lvl;
u8 cur_fw_dac_swing_lvl;
bool cur_ignore_wlan_act;
bool pre_ignore_wlan_act;
u8 pre_ps_tdma;
u8 cur_ps_tdma;
u8 ps_tdma_para[5];
u8 ps_tdma_du_adj_type;
bool reset_tdma_adjust;
bool auto_tdma_adjust;
bool pre_ps_tdma_on;
bool cur_ps_tdma_on;
bool pre_bt_auto_report;
bool cur_bt_auto_report;
/* sw mechanism */
bool pre_rf_rx_lpf_shrink;
bool cur_rf_rx_lpf_shrink;
u32 bt_rf0x1e_backup;
bool pre_low_penalty_ra;
bool cur_low_penalty_ra;
bool pre_dac_swing_on;
u32 pre_dac_swing_lvl;
bool cur_dac_swing_on;
u32 cur_dac_swing_lvl;
bool pre_adc_back_off;
bool cur_adc_back_off;
bool pre_agc_table_en;
bool cur_agc_table_en;
u32 pre_val0x6c0;
u32 cur_val0x6c0;
u32 pre_val0x6c4;
u32 cur_val0x6c4;
u32 pre_val0x6c8;
u32 cur_val0x6c8;
u8 pre_val0x6cc;
u8 cur_val0x6cc;
bool limited_dig;
u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */
u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */
u16 backup_retrylimit;
u8 backup_ampdu_maxtime;
/* algorithm related */
u8 pre_algorithm;
u8 cur_algorithm;
u8 bt_status;
u8 wifi_chnl_info[3];
u8 pre_sstype;
u8 cur_sstype;
u32 prera_mask;
u32 curra_mask;
u8 curra_masktype;
u8 pre_arfrtype;
u8 cur_arfrtype;
u8 pre_retrylimit_type;
u8 cur_retrylimit_type;
u8 pre_ampdutime_type;
u8 cur_ampdutime_type;
};
struct coex_sta_8192e_2ant {
bool bt_link_exist;
bool sco_exist;
bool a2dp_exist;
bool hid_exist;
bool pan_exist;
bool under_lps;
bool under_ips;
u32 high_priority_tx;
u32 high_priority_rx;
u32 low_priority_tx;
u32 low_priority_rx;
u8 bt_rssi;
u8 pre_bt_rssi_state;
u8 pre_wifi_rssi_state[4];
bool c2h_bt_info_req_sent;
u8 bt_info_c2h[BT_INFO_SRC_8192E_2ANT_MAX][10];
u32 bt_info_c2h_cnt[BT_INFO_SRC_8192E_2ANT_MAX];
bool c2h_bt_inquiry_page;
u8 bt_retry_cnt;
u8 bt_info_ext;
};
/****************************************************************
* The following is interface which will notify coex module.
****************************************************************/
void ex_halbtc8192e2ant_init_hwconfig(struct btc_coexist *btcoexist);
void ex_halbtc8192e2ant_init_coex_dm(struct btc_coexist *btcoexist);
void ex_halbtc8192e2ant_ips_notify(struct btc_coexist *btcoexist, u8 type);
void ex_halbtc8192e2ant_lps_notify(struct btc_coexist *btcoexist, u8 type);
void ex_halbtc8192e2ant_scan_notify(struct btc_coexist *btcoexist, u8 type);
void ex_halbtc8192e2ant_connect_notify(struct btc_coexist *btcoexist, u8 type);
void ex_halbtc8192e2ant_media_status_notify(struct btc_coexist *btcoexist,
u8 type);
void ex_halbtc8192e2ant_special_packet_notify(struct btc_coexist *btcoexist,
u8 type);
void ex_halbtc8192e2ant_bt_info_notify(struct btc_coexist *btcoexist,
u8 *tmpbuf, u8 length);
void ex_halbtc8192e2ant_stack_operation_notify(struct btc_coexist *btcoexist,
u8 type);
void ex_halbtc8192e2ant_halt_notify(struct btc_coexist *btcoexist);
void ex_halbtc8192e2ant_periodical(struct btc_coexist *btcoexist);
void ex_halbtc8192e2ant_display_coex_info(struct btc_coexist *btcoexist);

3146
drivers/staging/rtl8192ee/btcoexist/halbtc8723b1ant.c
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160
drivers/staging/rtl8192ee/btcoexist/halbtc8723b1ant.h
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@ -1,160 +0,0 @@
/**********************************************************************
* The following is for 8723B 1ANT BT Co-exist definition
**********************************************************************/
#define BT_AUTO_REPORT_ONLY_8723B_1ANT 1
#define BT_INFO_8723B_1ANT_B_FTP BIT(7)
#define BT_INFO_8723B_1ANT_B_A2DP BIT(6)
#define BT_INFO_8723B_1ANT_B_HID BIT(5)
#define BT_INFO_8723B_1ANT_B_SCO_BUSY BIT(4)
#define BT_INFO_8723B_1ANT_B_ACL_BUSY BIT(3)
#define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT(2)
#define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT(1)
#define BT_INFO_8723B_1ANT_B_CONNECTION BIT(0)
#define BT_INFO_8723B_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
(((_BT_INFO_EXT_&BIT(0))) ? true : false)
#define BTC_RSSI_COEX_THRESH_TOL_8723B_1ANT 2
enum BT_INFO_SRC_8723B_1ANT {
BT_INFO_SRC_8723B_1ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8723B_1ANT_BT_RSP = 0x1,
BT_INFO_SRC_8723B_1ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8723B_1ANT_MAX
};
enum BT_8723B_1ANT_BT_STATUS {
BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8723B_1ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8723B_1ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8723B_1ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8723B_1ANT_BT_STATUS_MAX
};
enum BT_8723B_1ANT_WIFI_STATUS {
BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1,
BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2,
BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT = 0x3,
BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4,
BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5,
BT_8723B_1ANT_WIFI_STATUS_MAX
};
enum BT_8723B_1ANT_COEX_ALGO {
BT_8723B_1ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8723B_1ANT_COEX_ALGO_SCO = 0x1,
BT_8723B_1ANT_COEX_ALGO_HID = 0x2,
BT_8723B_1ANT_COEX_ALGO_A2DP = 0x3,
BT_8723B_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8723B_1ANT_COEX_ALGO_PANEDR = 0x5,
BT_8723B_1ANT_COEX_ALGO_PANHS = 0x6,
BT_8723B_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8723B_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8723B_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8723B_1ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8723B_1ANT_COEX_ALGO_MAX = 0xb,
};
struct coex_dm_8723b_1ant {
/* fw mechanism */
bool cur_ignore_wlan_act;
bool pre_ignore_wlan_act;
u8 pre_ps_tdma;
u8 cur_ps_tdma;
u8 ps_tdma_para[5];
u8 ps_tdma_du_adj_type;
bool auto_tdma_adjust;
bool pre_ps_tdma_on;
bool cur_ps_tdma_on;
bool pre_bt_auto_report;
bool cur_bt_auto_report;
u8 pre_lps;
u8 cur_lps;
u8 pre_rpwm;
u8 cur_rpwm;
/* sw mechanism */
bool pre_low_penalty_ra;
bool cur_low_penalty_ra;
u32 pre_val0x6c0;
u32 cur_val0x6c0;
u32 pre_val0x6c4;
u32 cur_val0x6c4;
u32 pre_val0x6c8;
u32 cur_val0x6c8;
u8 pre_val0x6cc;
u8 cur_val0x6cc;
bool limited_dig;
u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */
u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */
u16 backup_retry_limit;
u8 backup_ampdu_max_time;
/* algorithm related */
u8 pre_algorithm;
u8 cur_algorithm;
u8 bt_status;
u8 wifi_chnl_info[3];
u32 prera_mask;
u32 curra_mask;
u8 pre_arfr_type;
u8 cur_arfr_type;
u8 pre_retry_limit_type;
u8 cur_retry_limit_type;
u8 pre_ampdu_time_type;
u8 cur_ampdu_time_type;
u8 error_condition;
};
struct coex_sta_8723b_1ant {
bool bt_link_exist;
bool sco_exist;
bool a2dp_exist;
bool hid_exist;
bool pan_exist;
bool under_lps;
bool under_ips;
u32 special_pkt_period_cnt;
u32 high_priority_tx;
u32 high_priority_rx;
u32 low_priority_tx;
u32 low_priority_rx;
u8 bt_rssi;
u8 pre_bt_rssi_state;
u8 pre_wifi_rssi_state[4];
bool c2h_bt_info_req_sent;
u8 bt_info_c2h[BT_INFO_SRC_8723B_1ANT_MAX][10];
u32 bt_info_c2h_cnt[BT_INFO_SRC_8723B_1ANT_MAX];
bool c2h_bt_inquiry_page;
u8 bt_retry_cnt;
u8 bt_info_ext;
};
/*************************************************************************
* The following is interface which will notify coex module.
*************************************************************************/
void ex_halbtc8723b1ant_init_hwconfig(struct btc_coexist *btcoexist);
void ex_halbtc8723b1ant_init_coex_dm(struct btc_coexist *btcoexist);
void ex_halbtc8723b1ant_ips_notify(struct btc_coexist *btcoexist, u8 type);
void ex_halbtc8723b1ant_lps_notify(struct btc_coexist *btcoexist, u8 type);
void ex_halbtc8723b1ant_scan_notify(struct btc_coexist *btcoexist, u8 type);
void ex_halbtc8723b1ant_connect_notify(struct btc_coexist *btcoexist, u8 type);
void ex_halbtc8723b1ant_media_status_notify(struct btc_coexist *btcoexist,
u8 type);
void ex_halbtc8723b1ant_special_packet_notify(struct btc_coexist *btcoexist,
u8 type);
void ex_halbtc8723b1ant_bt_info_notify(struct btc_coexist *btcoexist,
u8 *tmpbuf, u8 length);
void ex_halbtc8723b1ant_halt_notify(struct btc_coexist *btcoexist);
void ex_halbtc8723b1ant_pnp_notify(struct btc_coexist *btcoexist, u8 state);
void ex_halbtc8723b1ant_coex_dm_reset(struct btc_coexist *btcoexist);
void ex_halbtc8723b1ant_periodical(struct btc_coexist *btcoexist);
void ex_halbtc8723b1ant_display_coex_info(struct btc_coexist *btcoexist);

3929
drivers/staging/rtl8192ee/btcoexist/halbtc8723b2ant.c
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drivers/staging/rtl8192ee/btcoexist/halbtc8723b2ant.h
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/************************************************************************
* The following is for 8723B 2Ant BT Co-exist definition
************************************************************************/
#define BT_AUTO_REPORT_ONLY_8723B_2ANT 1
#define BT_INFO_8723B_2ANT_B_FTP BIT(7)
#define BT_INFO_8723B_2ANT_B_A2DP BIT(6)
#define BT_INFO_8723B_2ANT_B_HID BIT(5)
#define BT_INFO_8723B_2ANT_B_SCO_BUSY BIT(4)
#define BT_INFO_8723B_2ANT_B_ACL_BUSY BIT(3)
#define BT_INFO_8723B_2ANT_B_INQ_PAGE BIT(2)
#define BT_INFO_8723B_2ANT_B_SCO_ESCO BIT(1)
#define BT_INFO_8723B_2ANT_B_CONNECTION BIT(0)
#define BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT 2
enum BT_INFO_SRC_8723B_2ANT {
BT_INFO_SRC_8723B_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8723B_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8723B_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8723B_2ANT_MAX
};
enum BT_8723B_2ANT_BT_STATUS {
BT_8723B_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8723B_2ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8723B_2ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8723B_2ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8723B_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8723B_2ANT_BT_STATUS_MAX
};
enum BT_8723B_2ANT_COEX_ALGO {
BT_8723B_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8723B_2ANT_COEX_ALGO_SCO = 0x1,
BT_8723B_2ANT_COEX_ALGO_HID = 0x2,
BT_8723B_2ANT_COEX_ALGO_A2DP = 0x3,
BT_8723B_2ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8723B_2ANT_COEX_ALGO_PANEDR = 0x5,
BT_8723B_2ANT_COEX_ALGO_PANHS = 0x6,
BT_8723B_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8723B_2ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8723B_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8723B_2ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8723B_2ANT_COEX_ALGO_MAX = 0xb,
};
struct coex_dm_8723b_2ant {
/* fw mechanism */
bool pre_dec_bt_pwr;
bool cur_dec_bt_pwr;
u8 pre_fw_dac_swing_lvl;
u8 cur_fw_dac_swing_lvl;
bool cur_ignore_wlan_act;
bool pre_ignore_wlan_act;
u8 pre_ps_tdma;
u8 cur_ps_tdma;
u8 ps_tdma_para[5];
u8 ps_tdma_du_adj_type;
bool reset_tdma_adjust;
bool auto_tdma_adjust;
bool pre_ps_tdma_on;
bool cur_ps_tdma_on;
bool pre_bt_auto_report;
bool cur_bt_auto_report;
/* sw mechanism */
bool pre_rf_rx_lpf_shrink;
bool cur_rf_rx_lpf_shrink;
u32 bt_rf0x1e_backup;
bool pre_low_penalty_ra;
bool cur_low_penalty_ra;
bool pre_dac_swing_on;
u32 pre_dac_swing_lvl;
bool cur_dac_swing_on;
u32 cur_dac_swing_lvl;
bool pre_adc_back_off;
bool cur_adc_back_off;
bool pre_agc_table_en;
bool cur_agc_table_en;
u32 pre_val0x6c0;
u32 cur_val0x6c0;
u32 pre_val0x6c4;
u32 cur_val0x6c4;
u32 pre_val0x6c8;
u32 cur_val0x6c8;
u8 pre_val0x6cc;
u8 cur_val0x6cc;
bool limited_dig;
/* algorithm related */
u8 pre_algorithm;
u8 cur_algorithm;
u8 bt_status;
u8 wifi_chnl_info[3];
bool need_recover_0x948;
u16 backup_0x948;
};
struct coex_sta_8723b_2ant {
bool bt_link_exist;
bool sco_exist;
bool a2dp_exist;
bool hid_exist;
bool pan_exist;
bool under_lps;
bool under_ips;
u32 high_priority_tx;
u32 high_priority_rx;
u32 low_priority_tx;
u32 low_priority_rx;
u8 bt_rssi;
u8 pre_bt_rssi_state;
u8 pre_wifi_rssi_state[4];
bool c2h_bt_info_req_sent;
u8 bt_info_c2h[BT_INFO_SRC_8723B_2ANT_MAX][10];
u32 bt_info_c2h_cnt[BT_INFO_SRC_8723B_2ANT_MAX];
bool c2h_bt_inquiry_page;
u8 bt_retry_cnt;
u8 bt_info_ext;
};
/*********************************************************************
* The following is interface which will notify coex module.
*********************************************************************/
void ex92e_halbtc8723b2ant_init_hwconfig(struct btc_coexist *btcoexist);
void ex92e_halbtc8723b2ant_init_coex_dm(struct btc_coexist *btcoexist);
void ex92e_halbtc8723b2ant_ips_notify(struct btc_coexist *btcoexist, u8 type);
void ex92e_halbtc8723b2ant_lps_notify(struct btc_coexist *btcoexist, u8 type);
void ex92e_halbtc8723b2ant_scan_notify(struct btc_coexist *btcoexist, u8 type);
void ex92e_halbtc8723b2ant_connect_notify(struct btc_coexist *btcoexist,
u8 type);
void ex92e_halbtc8723b2ant_media_status_notify(struct btc_coexist *btcoexist,
u8 type);
void ex92e_halbtc8723b2ant_special_packet_notify(struct btc_coexist *btcoexist,
u8 type);
void ex92e_halbtc8723b2ant_bt_info_notify(struct btc_coexist *btcoexist,
u8 *tmpbuf, u8 length);
void ex92e_halbtc8723b2ant_halt_notify(struct btc_coexist *btcoexist);
void ex92e_halbtc8723b2ant_periodical(struct btc_coexist *btcoexist);
void ex_halbtc8723b2ant92e_display_coex_info(struct btc_coexist *btcoexist);

2780
drivers/staging/rtl8192ee/btcoexist/halbtc8821a1ant.c
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drivers/staging/rtl8192ee/btcoexist/halbtc8821a1ant.h
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/* */
/* The following is for 8821A 1ANT BT Co-exist definition */
/* */
#define BT_AUTO_REPORT_ONLY_8821A_1ANT 0
#define BT_INFO_8821A_1ANT_B_FTP BIT(7)
#define BT_INFO_8821A_1ANT_B_A2DP BIT(6)
#define BT_INFO_8821A_1ANT_B_HID BIT(5)
#define BT_INFO_8821A_1ANT_B_SCO_BUSY BIT(4)
#define BT_INFO_8821A_1ANT_B_ACL_BUSY BIT(3)
#define BT_INFO_8821A_1ANT_B_INQ_PAGE BIT(2)
#define BT_INFO_8821A_1ANT_B_SCO_ESCO BIT(1)
#define BT_INFO_8821A_1ANT_B_CONNECTION BIT(0)
#define BT_INFO_8821A_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
(((_BT_INFO_EXT_&BIT(0))) ? true : false)
#define BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT 2
enum BT_INFO_SRC_8821A_1ANT {
BT_INFO_SRC_8821A_1ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8821A_1ANT_BT_RSP = 0x1,
BT_INFO_SRC_8821A_1ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8821A_1ANT_MAX
};
enum BT_8821A_1ANT_BT_STATUS {
BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8821A_1ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8821A_1ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8821A_1ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8821A_1ANT_BT_STATUS_MAX
};
enum BT_8821A_1ANT_WIFI_STATUS {
BT_8821A_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8821A_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1,
BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2,
BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT = 0x3,
BT_8821A_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4,
BT_8821A_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5,
BT_8821A_1ANT_WIFI_STATUS_MAX
};
enum BT_8821A_1ANT_COEX_ALGO {
BT_8821A_1ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8821A_1ANT_COEX_ALGO_SCO = 0x1,
BT_8821A_1ANT_COEX_ALGO_HID = 0x2,
BT_8821A_1ANT_COEX_ALGO_A2DP = 0x3,
BT_8821A_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8821A_1ANT_COEX_ALGO_PANEDR = 0x5,
BT_8821A_1ANT_COEX_ALGO_PANHS = 0x6,
BT_8821A_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8821A_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8821A_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8821A_1ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8821A_1ANT_COEX_ALGO_MAX = 0xb,
};
struct coex_dm_8821a_1ant {
/* fw mechanism */
bool cur_ignore_wlan_act;
bool pre_ignore_wlan_act;
u8 pre_ps_tdma;
u8 cur_ps_tdma;
u8 ps_tdma_para[5];
u8 ps_tdma_du_adj_type;
bool auto_tdma_adjust;
bool pre_ps_tdma_on;
bool cur_ps_tdma_on;
bool pre_bt_auto_report;
bool cur_bt_auto_report;
u8 pre_lps;
u8 cur_lps;
u8 pre_rpwm;
u8 cur_rpwm;
/* sw mechanism */
bool pre_low_penalty_ra;
bool cur_low_penalty_ra;
u32 pre_val_0x6c0;
u32 cur_val_0x6c0;
u32 pre_val_0x6c4;
u32 cur_val_0x6c4;
u32 pre_val_0x6c8;
u32 cur_val_0x6c8;
u8 pre_val_0x6cc;
u8 cur_val_0x6cc;
u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */
u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */
u16 backup_retry_limit;
u8 backup_ampdu_max_time;
/* algorithm related */
u8 pre_algorithm;
u8 cur_algorithm;
u8 bt_status;
u8 wifi_chnl_info[3];
u32 pre_ra_mask;
u32 cur_ra_mask;
u8 pre_arfr_type;
u8 cur_arfr_type;
u8 pre_retry_limit_type;
u8 cur_retry_limit_type;
u8 pre_ampdu_time_type;
u8 cur_ampdu_time_type;
u8 error_condition;
};
struct coex_sta_8821a_1ant {
bool bt_link_exist;
bool sco_exist;
bool a2dp_exist;
bool hid_exist;
bool pan_exist;
bool under_lps;
bool under_ips;
u32 special_pkt_period_cnt;
u32 high_priority_tx;
u32 high_priority_rx;
u32 low_priority_tx;
u32 low_priority_rx;
u8 bt_rssi;
u8 pre_bt_rssi_state;
u8 pre_wifi_rssi_state[4];
bool c2h_bt_info_req_sent;
u8 bt_info_c2h[BT_INFO_SRC_8821A_1ANT_MAX][10];
u32 bt_info_c2h_cnt[BT_INFO_SRC_8821A_1ANT_MAX];
bool c2h_bt_inquiry_page;
u8 bt_retry_cnt;
u8 bt_info_ext;
};
/* The following is interface which will notify coex module. */
void ex_halbtc8821a1ant_init_hwconfig(struct btc_coexist *btcoexist);
void ex_halbtc8821a1ant_init_coex_dm(struct btc_coexist *btcoexist);
void ex_halbtc8821a1ant_ips_notify(struct btc_coexist *btcoexist, u8 type);
void ex_halbtc8821a1ant_lps_notify(struct btc_coexist *btcoexist, u8 type);
void ex_halbtc8821a1ant_scan_notify(struct btc_coexist *btcoexist, u8 type);
void ex_halbtc8821a1ant_connect_notify(struct btc_coexist *btcoexist, u8 type);
void ex_halbtc8821a1ant_media_status_notify(struct btc_coexist *btcoexist,
u8 type);
void ex_halbtc8821a1ant_special_packet_notify(struct btc_coexist *btcoexist,
u8 type);
void ex_halbtc8821a1ant_bt_info_notify(struct btc_coexist *btcoexist,
u8 *tmpbuf, u8 length);
void ex_halbtc8821a1ant_halt_notify(struct btc_coexist *btcoexist);
void ex_halbtc8821a1ant_pnp_notify(struct btc_coexist *btcoexist, u8 pnpstate);
void ex_halbtc8821a1ant_periodical(struct btc_coexist *btcoexist);
void ex_halbtc8821a1ant_display_coex_info(struct btc_coexist *btcoexist);
void ex_halbtc8821a1ant_dbg_control(struct btc_coexist *btcoexist, u8 op_code,
u8 op_len, u8 *data);

3438
drivers/staging/rtl8192ee/btcoexist/halbtc8821a2ant.c
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drivers/staging/rtl8192ee/btcoexist/halbtc8821a2ant.h
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/* */
/* The following is for 8821A 2Ant BT Co-exist definition */
/* */
#define BT_INFO_8821A_2ANT_B_FTP BIT(7)
#define BT_INFO_8821A_2ANT_B_A2DP BIT(6)
#define BT_INFO_8821A_2ANT_B_HID BIT(5)
#define BT_INFO_8821A_2ANT_B_SCO_BUSY BIT(4)
#define BT_INFO_8821A_2ANT_B_ACL_BUSY BIT(3)
#define BT_INFO_8821A_2ANT_B_INQ_PAGE BIT(2)
#define BT_INFO_8821A_2ANT_B_SCO_ESCO BIT(1)
#define BT_INFO_8821A_2ANT_B_CONNECTION BIT(0)
#define BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT 2
enum BT_INFO_SRC_8821A_2ANT {
BT_INFO_SRC_8821A_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8821A_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8821A_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8821A_2ANT_MAX
};
enum BT_8821A_2ANT_BT_STATUS {
BT_8821A_2ANT_BT_STATUS_IDLE = 0x0,
BT_8821A_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8821A_2ANT_BT_STATUS_NON_IDLE = 0x2,
BT_8821A_2ANT_BT_STATUS_MAX
};
enum BT_8821A_2ANT_COEX_ALGO {
BT_8821A_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8821A_2ANT_COEX_ALGO_SCO = 0x1,
BT_8821A_2ANT_COEX_ALGO_HID = 0x2,
BT_8821A_2ANT_COEX_ALGO_A2DP = 0x3,
BT_8821A_2ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8821A_2ANT_COEX_ALGO_PANEDR = 0x5,
BT_8821A_2ANT_COEX_ALGO_PANHS = 0x6,
BT_8821A_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8821A_2ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8821A_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8821A_2ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8821A_2ANT_COEX_ALGO_MAX = 0xb,
};
struct coex_dm_8821a_2ant {
/* fw mechanism */
bool pre_dec_bt_pwr;
bool cur_dec_bt_pwr;
bool pre_bt_lna_constrain;
bool cur_bt_lna_constrain;
u8 pre_bt_psd_mode;
u8 cur_bt_psd_mode;
u8 pre_fw_dac_swing_lvl;
u8 cur_fw_dac_swing_lvl;
bool cur_ignore_wlan_act;
bool pre_ignore_wlan_act;
u8 pre_ps_tdma;
u8 cur_ps_tdma;
u8 ps_tdma_para[5];
u8 ps_tdma_du_adj_type;
bool reset_tdma_adjust;
bool pre_ps_tdma_on;
bool cur_ps_tdma_on;
bool pre_bt_auto_report;
bool cur_bt_auto_report;
/* sw mechanism */
bool pre_rf_rx_lpf_shrink;
bool cur_rf_rx_lpf_shrink;
u32 bt_rf0x1e_backup;
bool pre_low_penalty_ra;
bool cur_low_penalty_ra;
bool pre_dac_swing_on;
u32 pre_dac_swing_lvl;
bool cur_dac_swing_on;
u32 cur_dac_swing_lvl;
bool pre_adc_back_off;
bool cur_adc_back_off;
bool pre_agc_table_en;
bool cur_agc_table_en;
u32 pre_val0x6c0;
u32 cur_val0x6c0;
u32 pre_val0x6c4;
u32 cur_val0x6c4;
u32 pre_val0x6c8;
u32 cur_val0x6c8;
u8 pre_val0x6cc;
u8 cur_val0x6cc;
bool limited_dig;
/* algorithm related */
u8 pre_algorithm;
u8 cur_algorithm;
u8 bt_status;
u8 wifi_chnl_info[3];
};
struct coex_sta_8821a_2ant {
bool bt_link_exist;
bool sco_exist;
bool a2dp_exist;
bool hid_exist;
bool pan_exist;
bool under_lps;
bool under_ips;
u32 high_priority_tx;
u32 high_priority_rx;
u32 low_priority_tx;
u32 low_priority_rx;
u8 bt_rssi;
u8 pre_bt_rssi_state;
u8 pre_wifi_rssi_state[4];
bool c2h_bt_info_req_sent;
u8 bt_info_c2h[BT_INFO_SRC_8821A_2ANT_MAX][10];
u32 bt_info_c2h_cnt[BT_INFO_SRC_8821A_2ANT_MAX];
bool c2h_bt_inquiry_page;
u8 bt_retry_cnt;
u8 bt_info_ext;
};
/* */
/* The following is interface which will notify coex module. */
/* */
void
ex_halbtc8821a2ant_init_hwconfig(
struct btc_coexist *btcoexist
);
void
ex_halbtc8821a2ant_init_coex_dm(
struct btc_coexist *btcoexist
);
void
ex_halbtc8821a2ant_ips_notify(
struct btc_coexist *btcoexist,
u8 type
);
void
ex_halbtc8821a2ant_lps_notify(
struct btc_coexist *btcoexist,
u8 type
);
void
ex_halbtc8821a2ant_scan_notify(
struct btc_coexist *btcoexist,
u8 type
);
void
ex_halbtc8821a2ant_connect_notify(
struct btc_coexist *btcoexist,
u8 type
);
void
ex_halbtc8821a2ant_media_status_notify(
struct btc_coexist *btcoexist,
u8 type
);
void
ex_halbtc8821a2ant_special_packet_notify(
struct btc_coexist *btcoexist,
u8 type
);
void
ex_halbtc8821a2ant_bt_info_notify(
struct btc_coexist *btcoexist,
u8 *tmp_buf,
u8 length
);
void
ex_halbtc8821a2ant_halt_notify(
struct btc_coexist *btcoexist
);
void
ex_halbtc8821a2ant_periodical(
struct btc_coexist *btcoexist
);
void
ex_halbtc8821a2ant_display_coex_info(
struct btc_coexist *btcoexist
);

1297
drivers/staging/rtl8192ee/btcoexist/halbtcoutsrc.c
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drivers/staging/rtl8192ee/btcoexist/halbtcoutsrc.h
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#ifndef __HALBTC_OUT_SRC_H__
#define __HALBTC_OUT_SRC_H__
#include "../wifi.h"
#define NORMAL_EXEC false
#define FORCE_EXEC true
#define BTC_RF_A RF90_PATH_A
#define BTC_RF_B RF90_PATH_B
#define BTC_RF_C RF90_PATH_C
#define BTC_RF_D RF90_PATH_D
#define BTC_SMSP SINGLEMAC_SINGLEPHY
#define BTC_DMDP DUALMAC_DUALPHY
#define BTC_DMSP DUALMAC_SINGLEPHY
#define BTC_MP_UNKNOWN 0xff
#define IN
#define OUT
#define BT_TMP_BUF_SIZE 100
#define BT_COEX_ANT_TYPE_PG 0
#define BT_COEX_ANT_TYPE_ANTDIV 1
#define BT_COEX_ANT_TYPE_DETECTED 2
#define BTC_MIMO_PS_STATIC 0
#define BTC_MIMO_PS_DYNAMIC 1
#define BTC_RATE_DISABLE 0
#define BTC_RATE_ENABLE 1
/* single Antenna definition */
#define BTC_ANT_PATH_WIFI 0
#define BTC_ANT_PATH_BT 1
#define BTC_ANT_PATH_PTA 2
/* dual Antenna definition */
#define BTC_ANT_WIFI_AT_MAIN 0
#define BTC_ANT_WIFI_AT_AUX 1
/* coupler Antenna definition */
#define BTC_ANT_WIFI_AT_CPL_MAIN 0
#define BTC_ANT_WIFI_AT_CPL_AUX 1
enum btc_chip_interface {
BTC_INTF_UNKNOWN = 0,
BTC_INTF_PCI = 1,
BTC_INTF_USB = 2,
BTC_INTF_SDIO = 3,
BTC_INTF_GSPI = 4,
BTC_INTF_MAX
};
enum btc_chip_type {
BTC_CHIP_UNDEF = 0,
BTC_CHIP_CSR_BC4 = 1,
BTC_CHIP_CSR_BC8 = 2,
BTC_CHIP_RTL8723A = 3,
BTC_CHIP_RTL8821 = 4,
BTC_CHIP_RTL8723B = 5,
BTC_CHIP_MAX
};
enum btc_msg_type {
BTC_MSG_INTERFACE = 0x0,
BTC_MSG_ALGORITHM = 0x1,
BTC_MSG_MAX
};
extern u32 btc_92edbg_type[];
/* following is for BTC_MSG_INTERFACE */
#define INTF_INIT BIT(0)
#define INTF_NOTIFY BIT(2)
/* following is for BTC_ALGORITHM */
#define ALGO_BT_RSSI_STATE BIT(0)
#define ALGO_WIFI_RSSI_STATE BIT(1)
#define ALGO_BT_MONITOR BIT(2)
#define ALGO_TRACE BIT(3)
#define ALGO_TRACE_FW BIT(4)
#define ALGO_TRACE_FW_DETAIL BIT(5)
#define ALGO_TRACE_FW_EXEC BIT(6)
#define ALGO_TRACE_SW BIT(7)
#define ALGO_TRACE_SW_DETAIL BIT(8)
#define ALGO_TRACE_SW_EXEC BIT(9)
/* following is for wifi link status */
#define WIFI_STA_CONNECTED BIT(0)
#define WIFI_AP_CONNECTED BIT(1)
#define WIFI_HS_CONNECTED BIT(2)
#define WIFI_P2P_GO_CONNECTED BIT(3)
#define WIFI_P2P_GC_CONNECTED BIT(4)
#define CL_SPRINTF snprintf
#define CL_PRINTF(buf) printk("%s", buf)
#define BTC_PRINT(dbgtype, dbgflag, printstr, ...) \
do { \
if (unlikely(btc_92edbg_type[dbgtype] & dbgflag)) {\
pr_debug(printstr, ##__VA_ARGS__); \
} \
} while (0)
#define BTC_PRINT_F(dbgtype, dbgflag, printstr, ...) \
do { \
if (unlikely(btc_92edbg_type[dbgtype] & dbgflag)) {\
pr_debug("%s: ", __func__); \
pr_cont(printstr, ##__VA_ARGS__); \
} \
} while (0)
#define BTC_PRINT_ADDR(dbgtype, dbgflag, printstr, _ptr) \
do { \
if (unlikely(btc_92edbg_type[dbgtype] & dbgflag)) { \
int __i; \
u8 *__ptr = (u8 *)_ptr; \
pr_debug printstr; \
for (__i = 0; __i < 6; __i++) \
pr_cont("%02X%s", __ptr[__i], \
(__i == 5) ? "" : "-"); \
pr_debug("\n"); \
} \
} while (0)
#define BTC_PRINT_DATA(dbgtype, dbgflag, _titlestring, _hexdata, _hexdatalen) \
do { \
if (unlikely(btc_92edbg_type[dbgtype] & dbgflag)) { \
int __i; \
u8 *__ptr = (u8 *)_hexdata; \
pr_debug(_titlestring); \
for (__i = 0; __i < (int)_hexdatalen; __i++) { \
pr_cont("%02X%s", __ptr[__i], (((__i + 1) % 4) \
== 0) ? " " : " ");\
if (((__i + 1) % 16) == 0) \
pr_cont("\n"); \
} \
pr_debug("\n"); \
} \
} while (0)
#define BTC_RSSI_HIGH(_rssi_) \
((_rssi_ == BTC_RSSI_STATE_HIGH || \
_rssi_ == BTC_RSSI_STATE_STAY_HIGH) ? true : false)
#define BTC_RSSI_MEDIUM(_rssi_) \
((_rssi_ == BTC_RSSI_STATE_MEDIUM || \
_rssi_ == BTC_RSSI_STATE_STAY_MEDIUM) ? true : false)
#define BTC_RSSI_LOW(_rssi_) \
((_rssi_ == BTC_RSSI_STATE_LOW || \
_rssi_ == BTC_RSSI_STATE_STAY_LOW) ? true : false)
enum btc_power_save_type {
BTC_PS_WIFI_NATIVE = 0,
BTC_PS_LPS_ON = 1,
BTC_PS_LPS_OFF = 2,
BTC_PS_LPS_MAX
};
struct btc_board_info {
/* The following is some board information */
u8 bt_chip_type;
u8 pg_ant_num; /* pg ant number */
u8 btdm_ant_num; /* ant number for btdm */
u8 btdm_ant_pos;
bool bt_exist;
};
enum btc_dbg_opcode {
BTC_DBG_SET_COEX_NORMAL = 0x0,
BTC_DBG_SET_COEX_WIFI_ONLY = 0x1,
BTC_DBG_SET_COEX_BT_ONLY = 0x2,
BTC_DBG_MAX
};
enum btc_rssi_state {
BTC_RSSI_STATE_HIGH = 0x0,
BTC_RSSI_STATE_MEDIUM = 0x1,
BTC_RSSI_STATE_LOW = 0x2,
BTC_RSSI_STATE_STAY_HIGH = 0x3,
BTC_RSSI_STATE_STAY_MEDIUM = 0x4,
BTC_RSSI_STATE_STAY_LOW = 0x5,
BTC_RSSI_MAX
};
enum btc_wifi_role {
BTC_ROLE_STATION = 0x0,
BTC_ROLE_AP = 0x1,
BTC_ROLE_IBSS = 0x2,
BTC_ROLE_HS_MODE = 0x3,
BTC_ROLE_MAX
};
enum btc_wifi_bw_mode {
BTC_WIFI_BW_LEGACY = 0x0,
BTC_WIFI_BW_HT20 = 0x1,
BTC_WIFI_BW_HT40 = 0x2,
BTC_WIFI_BW_MAX
};
enum btc_wifi_traffic_dir {
BTC_WIFI_TRAFFIC_TX = 0x0,
BTC_WIFI_TRAFFIC_RX = 0x1,
BTC_WIFI_TRAFFIC_MAX
};
enum btc_wifi_pnp {
BTC_WIFI_PNP_WAKE_UP = 0x0,
BTC_WIFI_PNP_SLEEP = 0x1,
BTC_WIFI_PNP_MAX
};
enum btc_get_type {
/* type bool */
BTC_GET_BL_HS_OPERATION,
BTC_GET_BL_HS_CONNECTING,
BTC_GET_BL_WIFI_CONNECTED,
BTC_GET_BL_WIFI_BUSY,
BTC_GET_BL_WIFI_SCAN,
BTC_GET_BL_WIFI_LINK,
BTC_GET_BL_WIFI_DHCP,
BTC_GET_BL_WIFI_SOFTAP_IDLE,
BTC_GET_BL_WIFI_SOFTAP_LINKING,
BTC_GET_BL_WIFI_IN_EARLY_SUSPEND,
BTC_GET_BL_WIFI_ROAM,
BTC_GET_BL_WIFI_4_WAY_PROGRESS,
BTC_GET_BL_WIFI_UNDER_5G,
BTC_GET_BL_WIFI_AP_MODE_ENABLE,
BTC_GET_BL_WIFI_ENABLE_ENCRYPTION,
BTC_GET_BL_WIFI_UNDER_B_MODE,
BTC_GET_BL_EXT_SWITCH,
/* type s4Byte */
BTC_GET_S4_WIFI_RSSI,
BTC_GET_S4_HS_RSSI,
/* type u32 */
BTC_GET_U4_WIFI_BW,
BTC_GET_U4_WIFI_TRAFFIC_DIRECTION,
BTC_GET_U4_WIFI_FW_VER,
BTC_GET_U4_WIFI_LINK_STATUS,
BTC_GET_U4_BT_PATCH_VER,
/* type u1Byte */
BTC_GET_U1_WIFI_DOT11_CHNL,
BTC_GET_U1_WIFI_CENTRAL_CHNL,
BTC_GET_U1_WIFI_HS_CHNL,
BTC_GET_U1_MAC_PHY_MODE,
BTC_GET_U1_AP_NUM,
/* for 1Ant */
BTC_GET_U1_LPS_MODE,
BTC_GET_BL_BT_SCO_BUSY,
/* for test mode */
BTC_GET_DRIVER_TEST_CFG,
BTC_GET_MAX
};
enum btc_set_type {
/* type bool */
BTC_SET_BL_BT_DISABLE,
BTC_SET_BL_BT_TRAFFIC_BUSY,
BTC_SET_BL_BT_LIMITED_DIG,
BTC_SET_BL_FORCE_TO_ROAM,
BTC_SET_BL_TO_REJ_AP_AGG_PKT,
BTC_SET_BL_BT_CTRL_AGG_SIZE,
BTC_SET_BL_INC_SCAN_DEV_NUM,
/* type u1Byte */
BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON,
BTC_SET_U1_AGG_BUF_SIZE,
/* type trigger some action */
BTC_SET_ACT_GET_BT_RSSI,
BTC_SET_ACT_AGGREGATE_CTRL,
/********* for 1Ant **********/
/* type bool */
BTC_SET_BL_BT_SCO_BUSY,
/* type u1Byte */
BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE,
BTC_SET_U1_LPS_VAL,
BTC_SET_U1_RPWM_VAL,
BTC_SET_U1_1ANT_LPS,
BTC_SET_U1_1ANT_RPWM,
/* type trigger some action */
BTC_SET_ACT_LEAVE_LPS,
BTC_SET_ACT_ENTER_LPS,
BTC_SET_ACT_NORMAL_LPS,
BTC_SET_ACT_INC_FORCE_EXEC_PWR_CMD_CNT,
BTC_SET_ACT_DISABLE_LOW_POWER,
BTC_SET_ACT_UPDATE_ra_mask,
BTC_SET_ACT_SEND_MIMO_PS,
/* BT Coex related */
BTC_SET_ACT_CTRL_BT_INFO,
BTC_SET_ACT_CTRL_BT_COEX,
/***************************/
BTC_SET_MAX
};
enum btc_dbg_disp_type {
BTC_DBG_DISP_COEX_STATISTICS = 0x0,
BTC_DBG_DISP_BT_LINK_INFO = 0x1,
BTC_DBG_DISP_BT_FW_VER = 0x2,
BTC_DBG_DISP_FW_PWR_MODE_CMD = 0x3,
BTC_DBG_DISP_MAX
};
enum btc_notify_type_ips {
BTC_IPS_LEAVE = 0x0,
BTC_IPS_ENTER = 0x1,
BTC_IPS_MAX
};
enum btc_notify_type_lps {
BTC_LPS_DISABLE = 0x0,
BTC_LPS_ENABLE = 0x1,
BTC_LPS_MAX
};
enum btc_notify_type_scan {
BTC_SCAN_FINISH = 0x0,
BTC_SCAN_START = 0x1,
BTC_SCAN_MAX
};
enum btc_notify_type_associate {
BTC_ASSOCIATE_FINISH = 0x0,
BTC_ASSOCIATE_START = 0x1,
BTC_ASSOCIATE_MAX
};
enum btc_notify_type_media_status {
BTC_MEDIA_DISCONNECT = 0x0,
BTC_MEDIA_CONNECT = 0x1,
BTC_MEDIA_MAX
};
enum btc_notify_type_special_packet {
BTC_PACKET_UNKNOWN = 0x0,
BTC_PACKET_DHCP = 0x1,
BTC_PACKET_ARP = 0x2,
BTC_PACKET_EAPOL = 0x3,
BTC_PACKET_MAX
};
enum hci_ext_bt_operation {
HCI_BT_OP_NONE = 0x0,
HCI_BT_OP_INQUIRY_START = 0x1,
HCI_BT_OP_INQUIRY_FINISH = 0x2,
HCI_BT_OP_PAGING_START = 0x3,
HCI_BT_OP_PAGING_SUCCESS = 0x4,
HCI_BT_OP_PAGING_UNSUCCESS = 0x5,
HCI_BT_OP_PAIRING_START = 0x6,
HCI_BT_OP_PAIRING_FINISH = 0x7,
HCI_BT_OP_BT_DEV_ENABLE = 0x8,
HCI_BT_OP_BT_DEV_DISABLE = 0x9,
HCI_BT_OP_MAX
};
enum btc_notify_type_stack_operation {
BTC_STACK_OP_NONE = 0x0,
BTC_STACK_OP_INQ_PAGE_PAIR_START = 0x1,
BTC_STACK_OP_INQ_PAGE_PAIR_FINISH = 0x2,
BTC_STACK_OP_MAX
};
struct btc_bt_info {
bool bt_disabled;
u8 rssi_adjust_for_agc_table_on;
u8 rssi_adjust_for_1ant_coex_type;
bool bt_busy;
u8 agg_buf_size;
bool limited_dig;
bool reject_agg_pkt;
bool b_bt_ctrl_buf_size;
bool increase_scan_dev_num;
u16 bt_hci_ver;
u16 bt_real_fw_ver;
u8 bt_fw_ver;
bool bt_disable_low_pwr;
/* the following is for 1Ant solution */
bool bt_ctrl_lps;
bool bt_pwr_save_mode;
bool bt_lps_on;
bool force_to_roam;
u8 force_exec_pwr_cmd_cnt;
u8 lps_val;
u8 rpwm_val;
u32 ra_mask;
};
struct btc_stack_info {
bool profile_notified;
u16 hci_version; /* stack hci version */
u8 num_of_link;
bool bt_link_exist;
bool sco_exist;
bool acl_exist;
bool a2dp_exist;
bool hid_exist;
u8 num_of_hid;
bool pan_exist;
bool unknown_acl_exist;
char min_bt_rssi;
};
struct btc_statistics {
u32 cnt_bind;
u32 cnt_init_hw_config;
u32 cnt_init_coex_dm;
u32 cnt_ips_notify;
u32 cnt_lps_notify;
u32 cnt_scan_notify;
u32 cnt_connect_notify;
u32 cnt_media_status_notify;
u32 cnt_special_packet_notify;
u32 cnt_bt_info_notify;
u32 cnt_periodical;
u32 cnt_coex_dm_switch;
u32 cnt_stack_operation_notify;
u32 cnt_dbg_ctrl;
};
struct btc_bt_link_info {
bool bt_link_exist;
bool sco_exist;
bool sco_only;
bool a2dp_exist;
bool a2dp_only;
bool hid_exist;
bool hid_only;
bool pan_exist;
bool pan_only;
};
enum btc_antenna_pos {
BTC_ANTENNA_AT_MAIN_PORT = 0x1,
BTC_ANTENNA_AT_AUX_PORT = 0x2,
};
struct btc_coexist {
/* make sure only one adapter can bind the data context */
bool binded;
/* default adapter */
void *adapter;
struct btc_board_info board_info;
/* some bt info referenced by non-bt module */
struct btc_bt_info bt_info;
struct btc_stack_info stack_info;
enum btc_chip_interface chip_interface;
struct btc_bt_link_info bt_link_info;
bool initilized;
bool stop_coex_dm;
bool manual_control;
u8 *cli_buf;
struct btc_statistics statistics;
u8 pwr_mode_val[10];
/* function pointers io related */
u8 (*btc_read_1byte)(void *btc_context, u32 reg_addr);
void (*btc_write_1byte)(void *btc_context, u32 reg_addr, u8 data);
void (*btc_write_1byte_bitmask)(void *btc_context, u32 reg_addr,
u8 bit_mask, u8 data1b);
u16 (*btc_read_2byte)(void *btc_context, u32 reg_addr);
void (*btc_write_2byte)(void *btc_context, u32 reg_addr, u16 data);
u32 (*btc_read_4byte)(void *btc_context, u32 reg_addr);
void (*btc_write_4byte)(void *btc_context, u32 reg_addr, u32 data);
void (*btc_set_bb_reg)(void *btc_context, u32 reg_addr,
u32 bit_mask, u32 data);
u32 (*btc_get_bb_reg)(void *btc_context, u32 reg_addr,
u32 bit_mask);
void (*btc_set_rf_reg)(void *btc_context, u8 rf_path, u32 reg_addr,
u32 bit_mask, u32 data);
u32 (*btc_get_rf_reg)(void *btc_context, u8 rf_path,
u32 reg_addr, u32 bit_mask);
void (*btc_fill_h2c)(void *btc_context, u8 element_id,
u32 cmd_len, u8 *cmd_buffer);
void (*btc_disp_dbg_msg)(void *btcoexist, u8 disp_type);
bool (*btc_get)(void *btcoexist, u8 get_type, void *out_buf);
bool (*btc_set)(void *btcoexist, u8 set_type, void *in_buf);
};
bool halbtc92e_is_wifi_uplink(struct rtl_priv *adapter);
extern struct btc_coexist gl92e_bt_coexist;
bool exhalbtc92e_initlize_variables(struct rtl_priv *adapter);
void exhalbtc92e_init_hw_config(struct btc_coexist *btcoexist);
void exhalbtc92e_init_coex_dm(struct btc_coexist *btcoexist);
void exhalbtc92e_ips_notify(struct btc_coexist *btcoexist, u8 type);
void exhalbtc92e_lps_notify(struct btc_coexist *btcoexist, u8 type);
void exhalbtc92e_scan_notify(struct btc_coexist *btcoexist, u8 type);
void exhalbtc92e_connect_notify(struct btc_coexist *btcoexist, u8 action);
void exhalbtc92e_mediastatus_notify(struct btc_coexist *btcoexist,
enum rt_media_status media_status);
void exhalbtc92e_special_packet_notify(struct btc_coexist *btcoexist,
u8 pkt_type);
void exhalbtc92e_bt_info_notify(struct btc_coexist *btcoexist, u8 *tmp_buf,
u8 length);
void exhalbtc92e_stack_operation_notify(struct btc_coexist *btcoexist, u8 type);
void exhalbtc92e_halt_notify(struct btc_coexist *btcoexist);
void exhalbtc92e_pnp_notify(struct btc_coexist *btcoexist, u8 pnp_state);
void exhalbtc_coex_dm_switch(struct btc_coexist *btcoexist);
void exhalbtc92e_periodical(struct btc_coexist *btcoexist);
void exhalbtc92e_dbg_control(struct btc_coexist *btcoexist, u8 code, u8 len,
u8 *data);
void exhalbtc92e_stack_update_profile_info(void);
void exhalbtc92e_set_hci_version(u16 hci_version);
void exhalbtc92e_set_bt_patch_version(u16 bt_hci_version, u16 bt_patch_version);
void exhalbtc92e_update_min_bt_rssi(char bt_rssi);
void exhalbtc92e_set_bt_exist(bool bt_exist);
void exhalbtc92e_set_chip_type(u8 chip_type);
void exhalbtc92e_set_ant_num(u8 type, u8 ant_num);
void exhalbtc92e_display_bt_coex_info(struct btc_coexist *btcoexist);
void exhalbtc_signal_compensation(struct btc_coexist *btcoexist,
u8 *rssi_wifi, u8 *rssi_bt);
void exhalbtc_lps_leave(struct btc_coexist *btcoexist);
void exhalbtc_low_wifi_traffic_notify(struct btc_coexist *btcoexist);
#endif

191
drivers/staging/rtl8192ee/btcoexist/rtl_btc.c
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@ -1,191 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include <linux/vmalloc.h>
#include <linux/module.h>
#include "rtl_btc.h"
#include "halbt_precomp.h"
static struct rtl_btc_ops rtl_btc_operation = {
.btc_init_variables = rtl92e_btc_init_variables,
.btc_init_hal_vars = rtl92e_btc_init_hal_vars,
.btc_init_hw_config = rtl92e_btc_init_hw_config,
.btc_ips_notify = rtl92e_btc_ips_notify,
.btc_lps_notify = rtl_btc_lps_notify,
.btc_scan_notify = rtl92e_btc_scan_notify,
.btc_connect_notify = rtl92e_btc_connect_notify,
.btc_mediastatus_notify = rtl92e_btc_mediastatus_notify,
.btc_periodical = rtl92e_btc_periodical,
.btc_halt_notify = rtl92e_btc_halt_notify,
.btc_btinfo_notify = rtl92e_btc_btinfo_notify,
.btc_is_limited_dig = rtl92e_btc_is_limited_dig,
.btc_is_disable_edca_turbo = rtl92e_btc_is_disable_edca_turbo,
.btc_is_bt_disabled = rtl92e_btc_is_bt_disabled,
.btc_special_packet_notify = rtl_btc_special_packet_notify,
};
void rtl92e_btc_init_variables(struct rtl_priv *rtlpriv)
{
exhalbtc92e_initlize_variables(rtlpriv);
}
void rtl92e_btc_init_hal_vars(struct rtl_priv *rtlpriv)
{
u8 ant_num;
u8 bt_exist;
u8 bt_type;
ant_num = rtl92e_get_hwpg_ant_num(rtlpriv);
RT_TRACE(COMP_INIT, DBG_DMESG, "antNum is %d\n", ant_num);
bt_exist = rtl92e_get_hwpg_bt_exist(rtlpriv);
RT_TRACE(COMP_INIT, DBG_DMESG, "bt_exist is %d\n", bt_exist);
exhalbtc92e_set_bt_exist(bt_exist);
bt_type = rtl92e_get_hwpg_bt_type(rtlpriv);
RT_TRACE(COMP_INIT, DBG_DMESG, "bt_type is %d\n", bt_type);
exhalbtc92e_set_chip_type(bt_type);
exhalbtc92e_set_ant_num(BT_COEX_ANT_TYPE_PG, ant_num);
}
void rtl92e_btc_init_hw_config(struct rtl_priv *rtlpriv)
{
exhalbtc92e_init_hw_config(&gl92e_bt_coexist);
exhalbtc92e_init_coex_dm(&gl92e_bt_coexist);
}
void rtl92e_btc_ips_notify(struct rtl_priv *rtlpriv, u8 type)
{
exhalbtc92e_ips_notify(&gl92e_bt_coexist, type);
}
void rtl_btc_lps_notify(struct rtl_priv *rtlpriv, u8 type)
{
exhalbtc92e_lps_notify(&gl92e_bt_coexist, type);
}
void rtl92e_btc_scan_notify(struct rtl_priv *rtlpriv, u8 scantype)
{
exhalbtc92e_scan_notify(&gl92e_bt_coexist, scantype);
}
void rtl92e_btc_connect_notify(struct rtl_priv *rtlpriv, u8 action)
{
exhalbtc92e_connect_notify(&gl92e_bt_coexist, action);
}
void rtl92e_btc_mediastatus_notify(struct rtl_priv *rtlpriv,
enum rt_media_status mstatus)
{
exhalbtc92e_mediastatus_notify(&gl92e_bt_coexist, mstatus);
}
void rtl92e_btc_periodical(struct rtl_priv *rtlpriv)
{
exhalbtc92e_periodical(&gl92e_bt_coexist);
}
void rtl92e_btc_halt_notify(void)
{
exhalbtc92e_halt_notify(&gl92e_bt_coexist);
}
void rtl92e_btc_btinfo_notify(struct rtl_priv *rtlpriv, u8 *tmp_buf, u8 length)
{
exhalbtc92e_bt_info_notify(&gl92e_bt_coexist, tmp_buf, length);
}
bool rtl92e_btc_is_limited_dig(struct rtl_priv *rtlpriv)
{
return gl92e_bt_coexist.bt_info.limited_dig;
}
bool rtl92e_btc_is_disable_edca_turbo(struct rtl_priv *rtlpriv)
{
bool bt_change_edca = false;
u32 cur_edca_val;
u32 edca_bt_hs_uplink = 0x5ea42b, edca_bt_hs_downlink = 0x5ea42b;
u32 edca_hs;
u32 edca_addr = 0x504;
cur_edca_val = rtl_read_dword(rtlpriv, edca_addr);
if (halbtc92e_is_wifi_uplink(rtlpriv)) {
if (cur_edca_val != edca_bt_hs_uplink) {
edca_hs = edca_bt_hs_uplink;
bt_change_edca = true;
}
} else {
if (cur_edca_val != edca_bt_hs_downlink) {
edca_hs = edca_bt_hs_downlink;
bt_change_edca = true;
}
}
if (bt_change_edca)
rtl_write_dword(rtlpriv, edca_addr, edca_hs);
return true;
}
bool rtl92e_btc_is_bt_disabled(struct rtl_priv *rtlpriv)
{
/* It seems 'bt_disabled' is never be initialized or set. */
if (gl92e_bt_coexist.bt_info.bt_disabled)
return true;
else
return false;
}
void rtl_btc_special_packet_notify(struct rtl_priv *rtlpriv, u8 pkt_type)
{
return exhalbtc92e_special_packet_notify(&gl92e_bt_coexist, pkt_type);
}
struct rtl_btc_ops *stg_rtl_btc_get_ops_pointer(void)
{
return &rtl_btc_operation;
}
EXPORT_SYMBOL(stg_rtl_btc_get_ops_pointer);
u8 rtl92e_get_hwpg_ant_num(struct rtl_priv *rtlpriv)
{
u8 num;
if (rtlpriv->btcoexist.btc_info.ant_num == ANT_X2)
num = 2;
else
num = 1;
return num;
}
u8 rtl92e_get_hwpg_bt_exist(struct rtl_priv *rtlpriv)
{
return rtlpriv->btcoexist.btc_info.btcoexist;
}
u8 rtl92e_get_hwpg_bt_type(struct rtl_priv *rtlpriv)
{
return rtlpriv->btcoexist.btc_info.bt_type;
}

62
drivers/staging/rtl8192ee/btcoexist/rtl_btc.h
View File

@ -1,62 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL_BTC_H__
#define __RTL_BTC_H__
#include "halbt_precomp.h"
void rtl92e_btc_init_variables(struct rtl_priv *rtlpriv);
void rtl92e_btc_init_hal_vars(struct rtl_priv *rtlpriv);
void rtl92e_btc_init_hw_config(struct rtl_priv *rtlpriv);
void rtl92e_btc_ips_notify(struct rtl_priv *rtlpriv, u8 type);
void rtl_btc_lps_notify(struct rtl_priv *rtlpriv, u8 type);
void rtl92e_btc_scan_notify(struct rtl_priv *rtlpriv, u8 scantype);
void rtl92e_btc_connect_notify(struct rtl_priv *rtlpriv, u8 action);
void rtl92e_btc_mediastatus_notify(struct rtl_priv *rtlpriv,
enum rt_media_status mstatus);
void rtl92e_btc_periodical(struct rtl_priv *rtlpriv);
void rtl92e_btc_halt_notify(void);
void rtl92e_btc_btinfo_notify(struct rtl_priv *rtlpriv, u8 *tmpbuf, u8 length);
bool rtl92e_btc_is_limited_dig(struct rtl_priv *rtlpriv);
bool rtl92e_btc_is_disable_edca_turbo(struct rtl_priv *rtlpriv);
bool rtl92e_btc_is_bt_disabled(struct rtl_priv *rtlpriv);
void rtl_btc_special_packet_notify(struct rtl_priv *rtlpriv, u8 pkt_type);
struct rtl_btc_ops *stg_rtl_btc_get_ops_pointer(void);
u8 rtl92e_get_hwpg_ant_num(struct rtl_priv *rtlpriv);
u8 rtl92e_get_hwpg_bt_exist(struct rtl_priv *rtlpriv);
u8 rtl92e_get_hwpg_bt_type(struct rtl_priv *rtlpriv);
enum rt_media_status mgnt_link_status_query(struct ieee80211_hw *hw);
#endif

329
drivers/staging/rtl8192ee/cam.c
View File

@ -1,329 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "wifi.h"
#include "cam.h"
void rtl92e_cam_reset_sec_info(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
rtlpriv->sec.use_defaultkey = false;
rtlpriv->sec.pairwise_enc_algorithm = NO_ENCRYPTION;
rtlpriv->sec.group_enc_algorithm = NO_ENCRYPTION;
memset(rtlpriv->sec.key_buf, 0, KEY_BUF_SIZE * MAX_KEY_LEN);
memset(rtlpriv->sec.key_len, 0, KEY_BUF_SIZE);
rtlpriv->sec.pairwise_key = NULL;
}
static void rtl_cam_program_entry(struct ieee80211_hw *hw, u32 entry_no,
u8 *mac_addr, u8 *key_cont_128, u16 us_config)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 target_command;
u32 target_content = 0;
u8 entry_i;
RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_DMESG, "Key content:",
key_cont_128, 16);
for (entry_i = 0; entry_i < CAM_CONTENT_COUNT; entry_i++) {
target_command = entry_i + CAM_CONTENT_COUNT * entry_no;
target_command = target_command | BIT(31) | BIT(16);
if (entry_i == 0) {
target_content = (u32) (*(mac_addr + 0)) << 16 |
(u32) (*(mac_addr + 1)) << 24 | (u32) us_config;
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI],
target_content);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
target_command);
RT_TRACE(COMP_SEC, DBG_LOUD, "WRITE %x: %x\n",
rtlpriv->cfg->maps[WCAMI], target_content);
RT_TRACE(COMP_SEC, DBG_LOUD, "The Key ID is %d\n",
entry_no);
RT_TRACE(COMP_SEC, DBG_LOUD, "WRITE %x: %x\n",
rtlpriv->cfg->maps[RWCAM], target_command);
} else if (entry_i == 1) {
target_content = (u32) (*(mac_addr + 5)) << 24 |
(u32) (*(mac_addr + 4)) << 16 |
(u32) (*(mac_addr + 3)) << 8 |
(u32) (*(mac_addr + 2));
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI],
target_content);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
target_command);
RT_TRACE(COMP_SEC, DBG_LOUD, "WRITE A4: %x\n",
target_content);
RT_TRACE(COMP_SEC, DBG_LOUD, "WRITE A0: %x\n",
target_command);
} else {
target_content =
(u32) (*(key_cont_128 + (entry_i * 4 - 8) + 3)) <<
24 | (u32) (*(key_cont_128 + (entry_i * 4 - 8) + 2))
<< 16 |
(u32) (*(key_cont_128 + (entry_i * 4 - 8) + 1)) << 8
| (u32) (*(key_cont_128 + (entry_i * 4 - 8) + 0));
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI],
target_content);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
target_command);
udelay(100);
RT_TRACE(COMP_SEC, DBG_LOUD, "WRITE A4: %x\n",
target_content);
RT_TRACE(COMP_SEC, DBG_LOUD, "WRITE A0: %x\n",
target_command);
}
}
RT_TRACE(COMP_SEC, DBG_LOUD, "after set key, usconfig:%x\n", us_config);
}
u8 stg_rtl_cam_add_one_entry(struct ieee80211_hw *hw, u8 *mac_addr,
u32 ul_key_id, u32 ul_entry_idx, u32 ul_enc_alg,
u32 ul_default_key, u8 *key_content)
{
u32 us_config;
struct rtl_priv *rtlpriv = rtl_priv(hw);
RT_TRACE(COMP_SEC, DBG_DMESG,
"EntryNo:%x, ulKeyId=%x, ulEncAlg=%x, ulUseDK=%x MacAddr %pM\n",
ul_entry_idx, ul_key_id, ul_enc_alg, ul_default_key, mac_addr);
if (ul_key_id == TOTAL_CAM_ENTRY) {
RT_TRACE(COMP_ERR, DBG_WARNING, "ulKeyId exceed!\n");
return 0;
}
if (ul_default_key == 1)
us_config = CFG_VALID | ((u16) (ul_enc_alg) << 2);
else
us_config = CFG_VALID | ((ul_enc_alg) << 2) | ul_key_id;
rtl_cam_program_entry(hw, ul_entry_idx, mac_addr,
(u8 *)key_content, us_config);
RT_TRACE(COMP_SEC, DBG_DMESG, "end\n");
return 1;
}
EXPORT_SYMBOL(stg_rtl_cam_add_one_entry);
int stg_rtl_cam_delete_one_entry(struct ieee80211_hw *hw,
u8 *mac_addr, u32 ul_key_id)
{
u32 ul_command;
struct rtl_priv *rtlpriv = rtl_priv(hw);
RT_TRACE(COMP_SEC, DBG_DMESG, "key_idx:%d\n", ul_key_id);
ul_command = ul_key_id * CAM_CONTENT_COUNT;
ul_command = ul_command | BIT(31) | BIT(16);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI], 0);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], ul_command);
RT_TRACE(COMP_SEC, DBG_DMESG,
"stg_rtl_cam_delete_one_entry(): WRITE A4: %x\n", 0);
RT_TRACE(COMP_SEC, DBG_DMESG,
"stg_rtl_cam_delete_one_entry(): WRITE A0: %x\n",
ul_command);
return 0;
}
EXPORT_SYMBOL(stg_rtl_cam_delete_one_entry);
void stg_rtl_cam_reset_all_entry(struct ieee80211_hw *hw)
{
u32 ul_command;
struct rtl_priv *rtlpriv = rtl_priv(hw);
ul_command = BIT(31) | BIT(30);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], ul_command);
}
EXPORT_SYMBOL(stg_rtl_cam_reset_all_entry);
void stg_rtl_cam_mark_invalid(struct ieee80211_hw *hw, u8 uc_index)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 ul_command;
u32 ul_content;
u32 ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_AES];
switch (rtlpriv->sec.pairwise_enc_algorithm) {
case WEP40_ENCRYPTION:
ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_WEP40];
break;
case WEP104_ENCRYPTION:
ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_WEP104];
break;
case TKIP_ENCRYPTION:
ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_TKIP];
break;
case AESCCMP_ENCRYPTION:
ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_AES];
break;
default:
ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_AES];
}
ul_content = (uc_index & 3) | ((u16) (ul_enc_algo) << 2);
ul_content |= BIT(15);
ul_command = CAM_CONTENT_COUNT * uc_index;
ul_command = ul_command | BIT(31) | BIT(16);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI], ul_content);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], ul_command);
RT_TRACE(COMP_SEC, DBG_DMESG,
"stg_rtl_cam_mark_invalid(): WRITE A4: %x\n", ul_content);
RT_TRACE(COMP_SEC, DBG_DMESG,
"stg_rtl_cam_mark_invalid(): WRITE A0: %x\n", ul_command);
}
EXPORT_SYMBOL(stg_rtl_cam_mark_invalid);
void stg_rtl_cam_empty_entry(struct ieee80211_hw *hw, u8 uc_index)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 ul_command;
u32 ul_content;
u32 ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_AES];
u8 entry_i;
switch (rtlpriv->sec.pairwise_enc_algorithm) {
case WEP40_ENCRYPTION:
ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_WEP40];
break;
case WEP104_ENCRYPTION:
ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_WEP104];
break;
case TKIP_ENCRYPTION:
ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_TKIP];
break;
case AESCCMP_ENCRYPTION:
ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_AES];
break;
default:
ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_AES];
}
for (entry_i = 0; entry_i < CAM_CONTENT_COUNT; entry_i++) {
if (entry_i == 0) {
ul_content =
(uc_index & 0x03) | ((u16) (ul_encalgo) << 2);
ul_content |= BIT(15);
} else {
ul_content = 0;
}
ul_command = CAM_CONTENT_COUNT * uc_index + entry_i;
ul_command = ul_command | BIT(31) | BIT(16);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI], ul_content);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], ul_command);
RT_TRACE(COMP_SEC, DBG_LOUD,
"stg_rtl_cam_empty_entry(): WRITE A4: %x\n",
ul_content);
RT_TRACE(COMP_SEC, DBG_LOUD,
"stg_rtl_cam_empty_entry(): WRITE A0: %x\n",
ul_command);
}
}
EXPORT_SYMBOL(stg_rtl_cam_empty_entry);
u8 stg_rtl_cam_get_free_entry(struct ieee80211_hw *hw, u8 *sta_addr)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 bitmap = (rtlpriv->sec.hwsec_cam_bitmap) >> 4;
u8 entry_idx = 0;
u8 i, *addr;
if (!sta_addr) {
RT_TRACE(COMP_SEC, DBG_EMERG, "sta_addr is NULL\n");
return TOTAL_CAM_ENTRY;
}
/* Does STA already exist? */
for (i = 4; i < TOTAL_CAM_ENTRY; i++) {
addr = rtlpriv->sec.hwsec_cam_sta_addr[i];
if (memcmp(addr, sta_addr, ETH_ALEN) == 0)
return i;
}
/* Get a free CAM entry. */
for (entry_idx = 4; entry_idx < TOTAL_CAM_ENTRY; entry_idx++) {
if ((bitmap & BIT(0)) == 0) {
RT_TRACE(COMP_SEC, DBG_EMERG,
"-----hwsec_cam_bitmap: 0x%x entry_idx=%d\n",
rtlpriv->sec.hwsec_cam_bitmap, entry_idx);
rtlpriv->sec.hwsec_cam_bitmap |= BIT(0) << entry_idx;
memcpy(rtlpriv->sec.hwsec_cam_sta_addr[entry_idx],
sta_addr, ETH_ALEN);
return entry_idx;
}
bitmap = bitmap >> 1;
}
return TOTAL_CAM_ENTRY;
}
EXPORT_SYMBOL(stg_rtl_cam_get_free_entry);
void stg_rtl_cam_del_entry(struct ieee80211_hw *hw, u8 *sta_addr)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 bitmap;
u8 i, *addr;
if (NULL == sta_addr) {
RT_TRACE(COMP_SEC, DBG_EMERG, "sta_addr is NULL\n");
return;
}
if (is_zero_ether_addr(sta_addr)) {
RT_TRACE(COMP_SEC, DBG_EMERG,
"sta_addr is 00:00:00:00:00:00\n");
return;
}
/* Does STA already exist? */
for (i = 4; i < TOTAL_CAM_ENTRY; i++) {
addr = rtlpriv->sec.hwsec_cam_sta_addr[i];
bitmap = (rtlpriv->sec.hwsec_cam_bitmap) >> i;
if (((bitmap & BIT(0)) == BIT(0)) &&
(memcmp(addr, sta_addr, ETH_ALEN) == 0)) {
/* Remove from HW Security CAM */
memset(rtlpriv->sec.hwsec_cam_sta_addr[i], 0, ETH_ALEN);
rtlpriv->sec.hwsec_cam_bitmap &= ~(BIT(0) << i);
pr_info("&&&&&&&&&del entry %d\n", i);
}
}
}
EXPORT_SYMBOL(stg_rtl_cam_del_entry);

52
drivers/staging/rtl8192ee/cam.h
View File

@ -1,52 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL_CAM_H_
#define __RTL_CAM_H_
#define CAM_CONTENT_COUNT 8
#define CFG_DEFAULT_KEY BIT(5)
#define CFG_VALID BIT(15)
#define PAIRWISE_KEYIDX 0
#define CAM_PAIRWISE_KEY_POSITION 4
#define CAM_CONFIG_USEDK 1
#define CAM_CONFIG_NO_USEDK 0
void stg_rtl_cam_reset_all_entry(struct ieee80211_hw *hw);
u8 stg_rtl_cam_add_one_entry(struct ieee80211_hw *hw, u8 *mac_addr,
u32 ul_key_id, u32 ul_entry_idx, u32 ul_enc_alg,
u32 ul_default_key, u8 *key_content);
int stg_rtl_cam_delete_one_entry(struct ieee80211_hw *hw, u8 *mac_addr,
u32 ul_key_id);
void stg_rtl_cam_mark_invalid(struct ieee80211_hw *hw, u8 uc_index);
void stg_rtl_cam_empty_entry(struct ieee80211_hw *hw, u8 uc_index);
void rtl92e_cam_reset_sec_info(struct ieee80211_hw *hw);
u8 stg_rtl_cam_get_free_entry(struct ieee80211_hw *hw, u8 *sta_addr);
void stg_rtl_cam_del_entry(struct ieee80211_hw *hw, u8 *sta_addr);
#endif

70
drivers/staging/rtl8192ee/compat.h
View File

@ -1,70 +0,0 @@
#ifndef __RTL_COMPAT_H__
#define __RTL_COMPAT_H__
#define RX_FLAG_MACTIME_MPDU RX_FLAG_MACTIME_START
#define IEEE80211_KEY_FLAG_SW_MGMT IEEE80211_KEY_FLAG_SW_MGMT_TX
struct ieee80211_mgmt_compat {
__le16 frame_control;
__le16 duration;
u8 da[6];
u8 sa[6];
u8 bssid[6];
__le16 seq_ctrl;
union {
struct {
u8 category;
union {
struct {
u8 action_code;
u8 dialog_token;
u8 status_code;
u8 variable[0];
} __packed wme_action;
struct {
u8 action_code;
u8 dialog_token;
__le16 capab;
__le16 timeout;
__le16 start_seq_num;
} __packed addba_req;
struct{
u8 action_code;
u8 dialog_token;
__le16 status;
__le16 capab;
__le16 timeout;
} __packed addba_resp;
struct {
u8 action_code;
__le16 params;
__le16 reason_code;
} __packed delba;
struct {
u8 action_code;
/* capab_info for open and confirm,
* reason for close
*/
__le16 aux;
/* Followed in plink_confirm by status
* code, AID and supported rates,
* and directly by supported rates in
* plink_open and plink_close
*/
u8 variable[0];
} __packed plink_action;
struct {
u8 action_code;
u8 variable[0];
} __packed mesh_action;
struct {
u8 action;
u8 smps_control;
} __packed ht_smps;
} u;
} __packed action;
} u;
} __packed;
#endif

1584
drivers/staging/rtl8192ee/core.c
View File

File diff suppressed because it is too large Load Diff

39
drivers/staging/rtl8192ee/core.h
View File

@ -1,39 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* Tmis program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* Tme full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL_CORE_H__
#define __RTL_CORE_H__
#define RTL_SUPPORTED_FILTERS \
(FIF_PROMISC_IN_BSS | \
FIF_ALLMULTI | FIF_CONTROL | \
FIF_OTHER_BSS | \
FIF_FCSFAIL | \
FIF_BCN_PRBRESP_PROMISC)
#define RTL_SUPPORTED_CTRL_FILTER 0xFF
extern const struct ieee80211_ops rtl92e_ops;
#endif

978
drivers/staging/rtl8192ee/debug.c
View File

@ -1,978 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* Tmis program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "wifi.h"
#include "cam.h"
#define GET_INODE_DATA(__node) PDE_DATA(__node)
void rtl92e_dbgp_flag_init(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u8 i;
rtlpriv->dbg.global_debuglevel = DBG_DMESG;
rtlpriv->dbg.global_debugcomponents =
COMP_ERR |
COMP_FW |
COMP_INIT |
COMP_RECV |
COMP_SEND |
COMP_MLME |
COMP_SCAN |
COMP_INTR |
COMP_LED |
COMP_SEC |
COMP_BEACON |
COMP_RATE |
COMP_RXDESC |
COMP_DIG |
COMP_TXAGC |
COMP_POWER |
COMP_POWER_TRACKING |
COMP_BB_POWERSAVING |
COMP_SWAS |
COMP_RF |
COMP_TURBO |
COMP_RATR |
COMP_CMD |
COMP_EASY_CONCURRENT |
COMP_EFUSE |
COMP_QOS | COMP_MAC80211 | COMP_REGD |
COMP_CHAN |
COMP_BT_COEXIST |
COMP_IQK |
0;
for (i = 0; i < DBGP_TYPE_MAX; i++)
rtlpriv->dbg.dbgp_type[i] = 0;
/*Init Debug flag enable condition */
}
static struct proc_dir_entry *proc_topdir;
static int rtl_proc_get_mac_0(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
struct rtl_priv *rtlpriv = rtl_priv(hw);
int i, n, page;
int max = 0xff;
page = 0x000;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_read_dword(rtlpriv, (page | n)));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_mac_0(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_mac_0, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_mac_0 = {
.open = dl_proc_open_mac_0,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_mac_1(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
struct rtl_priv *rtlpriv = rtl_priv(hw);
int i, n, page;
int max = 0xff;
page = 0x100;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_read_dword(rtlpriv, (page | n)));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_mac_1(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_mac_1, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_mac_1 = {
.open = dl_proc_open_mac_1,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_mac_2(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
struct rtl_priv *rtlpriv = rtl_priv(hw);
int i, n, page;
int max = 0xff;
page = 0x200;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_read_dword(rtlpriv, (page | n)));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_mac_2(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_mac_2, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_mac_2 = {
.open = dl_proc_open_mac_2,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_mac_3(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
struct rtl_priv *rtlpriv = rtl_priv(hw);
int i, n, page;
int max = 0xff;
page = 0x300;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_read_dword(rtlpriv, (page | n)));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_mac_3(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_mac_3, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_mac_3 = {
.open = dl_proc_open_mac_3,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_mac_4(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
struct rtl_priv *rtlpriv = rtl_priv(hw);
int i, n, page;
int max = 0xff;
page = 0x400;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_read_dword(rtlpriv, (page | n)));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_mac_4(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_mac_4, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_mac_4 = {
.open = dl_proc_open_mac_4,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_mac_5(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
struct rtl_priv *rtlpriv = rtl_priv(hw);
int i, n, page;
int max = 0xff;
page = 0x500;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_read_dword(rtlpriv, (page | n)));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_mac_5(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_mac_5, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_mac_5 = {
.open = dl_proc_open_mac_5,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_mac_6(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
struct rtl_priv *rtlpriv = rtl_priv(hw);
int i, n, page;
int max = 0xff;
page = 0x600;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_read_dword(rtlpriv, (page | n)));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_mac_6(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_mac_6, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_mac_6 = {
.open = dl_proc_open_mac_6,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_mac_7(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
struct rtl_priv *rtlpriv = rtl_priv(hw);
int i, n, page;
int max = 0xff;
page = 0x700;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_read_dword(rtlpriv, (page | n)));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_mac_7(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_mac_7, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_mac_7 = {
.open = dl_proc_open_mac_7,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_bb_8(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
int i, n, page;
int max = 0xff;
page = 0x800;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_get_bbreg(hw, (page | n), 0xffffffff));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_bb_8(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_bb_8, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_bb_8 = {
.open = dl_proc_open_bb_8,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_bb_9(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
int i, n, page;
int max = 0xff;
page = 0x900;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_get_bbreg(hw, (page | n), 0xffffffff));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_bb_9(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_bb_9, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_bb_9 = {
.open = dl_proc_open_bb_9,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_bb_a(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
int i, n, page;
int max = 0xff;
page = 0xa00;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_get_bbreg(hw, (page | n), 0xffffffff));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_bb_a(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_bb_a, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_bb_a = {
.open = dl_proc_open_bb_a,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_bb_b(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
int i, n, page;
int max = 0xff;
page = 0xb00;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_get_bbreg(hw, (page | n), 0xffffffff));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_bb_b(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_bb_b, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_bb_b = {
.open = dl_proc_open_bb_b,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_bb_c(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
int i, n, page;
int max = 0xff;
page = 0xc00;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_get_bbreg(hw, (page | n), 0xffffffff));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_bb_c(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_bb_c, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_bb_c = {
.open = dl_proc_open_bb_c,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_bb_d(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
int i, n, page;
int max = 0xff;
page = 0xd00;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_get_bbreg(hw, (page | n), 0xffffffff));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_bb_d(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_bb_d, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_bb_d = {
.open = dl_proc_open_bb_d,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_bb_e(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
int i, n, page;
int max = 0xff;
page = 0xe00;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_get_bbreg(hw, (page | n), 0xffffffff));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_bb_e(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_bb_e, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_bb_e = {
.open = dl_proc_open_bb_e,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_bb_f(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
int i, n, page;
int max = 0xff;
page = 0xf00;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_get_bbreg(hw, (page | n), 0xffffffff));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_bb_f(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_bb_f, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_bb_f = {
.open = dl_proc_open_bb_f,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_reg_rf_a(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
int i, n;
int max = 0x40;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n);
for (i = 0; i < 4 && n <= max; n += 1, i++)
seq_printf(m, "%8.8x ",
rtl_get_rfreg(hw, RF90_PATH_A, n, 0xffffffff));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_rf_a(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_reg_rf_a, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_rf_a = {
.open = dl_proc_open_rf_a,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_reg_rf_b(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
int i, n;
int max = 0x40;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n);
for (i = 0; i < 4 && n <= max; n += 1, i++)
seq_printf(m, "%8.8x ",
rtl_get_rfreg(hw, RF90_PATH_B, n,
0xffffffff));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_rf_b(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_reg_rf_b, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_rf_b = {
.open = dl_proc_open_rf_b,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_cam_register_1(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 target_cmd = 0;
u32 target_val = 0;
u8 entry_i = 0;
u32 ulstatus;
int i = 100, j = 0;
/* This dump the current register page */
seq_puts(m,
"\n#################### SECURITY CAM (0-10) ##################\n ");
for (j = 0; j < 11; j++) {
seq_printf(m, "\nD: %2x > ", j);
for (entry_i = 0; entry_i < CAM_CONTENT_COUNT; entry_i++) {
/* polling bit, and No Write enable, and address */
target_cmd = entry_i + CAM_CONTENT_COUNT * j;
target_cmd = target_cmd | BIT(31);
/* Check polling bit is clear */
while ((i--) >= 0) {
ulstatus = rtl_read_dword(rtlpriv,
rtlpriv->cfg->maps[RWCAM]);
if (ulstatus & BIT(31))
continue;
else
break;
}
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
target_cmd);
target_val = rtl_read_dword(rtlpriv,
rtlpriv->cfg->maps[RCAMO]);
seq_printf(m, "%8.8x ", target_val);
}
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_cam_1(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_cam_register_1,
GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_cam_1 = {
.open = dl_proc_open_cam_1,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_cam_register_2(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 target_cmd = 0;
u32 target_val = 0;
u8 entry_i = 0;
u32 ulstatus;
int i = 100, j = 0;
/* This dump the current register page */
seq_puts(m,
"\n################### SECURITY CAM (11-21) ##################\n ");
for (j = 11; j < 22; j++) {
seq_printf(m, "\nD: %2x > ", j);
for (entry_i = 0; entry_i < CAM_CONTENT_COUNT; entry_i++) {
target_cmd = entry_i + CAM_CONTENT_COUNT * j;
target_cmd = target_cmd | BIT(31);
while ((i--) >= 0) {
ulstatus = rtl_read_dword(rtlpriv,
rtlpriv->cfg->maps[RWCAM]);
if (ulstatus & BIT(31))
continue;
else
break;
}
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
target_cmd);
target_val = rtl_read_dword(rtlpriv,
rtlpriv->cfg->maps[RCAMO]);
seq_printf(m, "%8.8x ", target_val);
}
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_cam_2(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_cam_register_2,
GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_cam_2 = {
.open = dl_proc_open_cam_2,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_cam_register_3(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 target_cmd = 0;
u32 target_val = 0;
u8 entry_i = 0;
u32 ulstatus;
int i = 100, j = 0;
/* This dump the current register page */
seq_puts(m,
"\n################### SECURITY CAM (22-31) ##################\n ");
for (j = 22; j < TOTAL_CAM_ENTRY; j++) {
seq_printf(m, "\nD: %2x > ", j);
for (entry_i = 0; entry_i < CAM_CONTENT_COUNT; entry_i++) {
target_cmd = entry_i+CAM_CONTENT_COUNT*j;
target_cmd = target_cmd | BIT(31);
while ((i--) >= 0) {
ulstatus = rtl_read_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM]);
if (ulstatus & BIT(31))
continue;
else
break;
}
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
target_cmd);
target_val = rtl_read_dword(rtlpriv,
rtlpriv->cfg->maps[RCAMO]);
seq_printf(m, "%8.8x ", target_val);
}
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_cam_3(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_cam_register_3,
GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_cam_3 = {
.open = dl_proc_open_cam_3,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
void rtl_proc_add_one(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
struct proc_dir_entry *entry;
snprintf(rtlpriv->dbg.proc_name, 18, "%x-%x-%x-%x-%x-%x",
rtlefuse->dev_addr[0], rtlefuse->dev_addr[1],
rtlefuse->dev_addr[2], rtlefuse->dev_addr[3],
rtlefuse->dev_addr[4], rtlefuse->dev_addr[5]);
rtlpriv->dbg.proc_dir = proc_mkdir(rtlpriv->dbg.proc_name, proc_topdir);
if (!rtlpriv->dbg.proc_dir) {
RT_TRACE(COMP_INIT, DBG_EMERG,
"Unable to init /proc/net/%s/%s\n",
rtlpriv->cfg->name,
rtlpriv->dbg.proc_name);
return;
}
entry = proc_create_data("mac-0", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_mac_0, hw);
if (!entry)
RT_TRACE(COMP_INIT, DBG_EMERG,
"Unable to initialize /proc/net/%s/%s/mac-0\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name);
entry = proc_create_data("mac-1", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_mac_1, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
"Unable to initialize /proc/net/%s/%s/mac-1\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name);
entry = proc_create_data("mac-2", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_mac_2, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
"Unable to initialize /proc/net/%s/%s/mac-2\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name);
entry = proc_create_data("mac-3", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_mac_3, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
"Unable to initialize /proc/net/%s/%s/mac-3\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name);
entry = proc_create_data("mac-4", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_mac_4, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
"Unable to initialize /proc/net/%s/%s/mac-4\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name);
entry = proc_create_data("mac-5", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_mac_5, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
"Unable to initialize /proc/net/%s/%s/mac-5\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name);
entry = proc_create_data("mac-6", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_mac_6, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
"Unable to initialize /proc/net/%s/%s/mac-6\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name);
entry = proc_create_data("mac-7", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_mac_7, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
"Unable to initialize /proc/net/%s/%s/mac-7\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name);
entry = proc_create_data("bb-8", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_bb_8, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
"Unable to initialize /proc/net/%s/%s/bb-8\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name);
entry = proc_create_data("bb-9", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_bb_9, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
"Unable to initialize /proc/net/%s/%s/bb-9\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name);
entry = proc_create_data("bb-a", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_bb_a, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
"Unable to initialize /proc/net/%s/%s/bb-a\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name);
entry = proc_create_data("bb-b", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_bb_b, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
"Unable to initialize /proc/net/%s/%s/bb-b\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name);
entry = proc_create_data("bb-c", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_bb_c, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
"Unable to initialize /proc/net/%s/%s/bb-c\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name);
entry = proc_create_data("bb-d", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_bb_d, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
"Unable to initialize /proc/net/%s/%s/bb-d\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name);
entry = proc_create_data("bb-e", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_bb_e, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
"Unable to initialize /proc/net/%s/%s/bb-e\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name);
entry = proc_create_data("bb-f", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_bb_f, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
"Unable to initialize /proc/net/%s/%s/bb-f\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name);
entry = proc_create_data("rf-a", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_rf_a, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
"Unable to initialize /proc/net/%s/%s/rf-a\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name);
entry = proc_create_data("rf-b", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_rf_b, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
"Unable to initialize /proc/net/%s/%s/rf-b\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name);
entry = proc_create_data("cam-1", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_cam_1, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
"Unable to initialize /proc/net/%s/%s/cam-1\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name);
entry = proc_create_data("cam-2", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_cam_2, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
"Unable to initialize /proc/net/%s/%s/cam-2\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name);
entry = proc_create_data("cam-3", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_cam_3, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
"Unable to initialize /proc/net/%s/%s/cam-3\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name);
}
void rtl_proc_remove_one(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
if (rtlpriv->dbg.proc_dir) {
remove_proc_entry("mac-0", rtlpriv->dbg.proc_dir);
remove_proc_entry("mac-1", rtlpriv->dbg.proc_dir);
remove_proc_entry("mac-2", rtlpriv->dbg.proc_dir);
remove_proc_entry("mac-3", rtlpriv->dbg.proc_dir);
remove_proc_entry("mac-4", rtlpriv->dbg.proc_dir);
remove_proc_entry("mac-5", rtlpriv->dbg.proc_dir);
remove_proc_entry("mac-6", rtlpriv->dbg.proc_dir);
remove_proc_entry("mac-7", rtlpriv->dbg.proc_dir);
remove_proc_entry("bb-8", rtlpriv->dbg.proc_dir);
remove_proc_entry("bb-9", rtlpriv->dbg.proc_dir);
remove_proc_entry("bb-a", rtlpriv->dbg.proc_dir);
remove_proc_entry("bb-b", rtlpriv->dbg.proc_dir);
remove_proc_entry("bb-c", rtlpriv->dbg.proc_dir);
remove_proc_entry("bb-d", rtlpriv->dbg.proc_dir);
remove_proc_entry("bb-e", rtlpriv->dbg.proc_dir);
remove_proc_entry("bb-f", rtlpriv->dbg.proc_dir);
remove_proc_entry("rf-a", rtlpriv->dbg.proc_dir);
remove_proc_entry("rf-b", rtlpriv->dbg.proc_dir);
remove_proc_entry("cam-1", rtlpriv->dbg.proc_dir);
remove_proc_entry("cam-2", rtlpriv->dbg.proc_dir);
remove_proc_entry("cam-3", rtlpriv->dbg.proc_dir);
remove_proc_entry(rtlpriv->dbg.proc_name, proc_topdir);
rtlpriv->dbg.proc_dir = NULL;
}
}
void rtl_proc_add_topdir(void)
{
proc_topdir = proc_mkdir("rtlwifi", init_net.proc_net);
}
void rtl_proc_remove_topdir(void)
{
if (proc_topdir)
remove_proc_entry("rtlwifi", init_net.proc_net);
}

219
drivers/staging/rtl8192ee/debug.h
View File

@ -1,219 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* Tmis program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* Tmis program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* Tme full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL_DEBUG_H__
#define __RTL_DEBUG_H__
/*--------------------------------------------------------------
Debug level
--------------------------------------------------------------*/
/*
*Fatal bug.
*For example, Tx/Rx/IO locked up,
*memory access violation,
*resource allocation failed,
*unexpected HW behavior, HW BUG
*and so on.
*/
#define DBG_EMERG 1
/*
*Abnormal, rare, or unexpeted cases.
*For example, Packet/IO Ctl canceled,
*device suprisely unremoved and so on.
*/
#define DBG_WARNING 2
/*
*Normal case driver developer should
*open, we can see link status like
*assoc/AddBA/DHCP/adapter start and
*so on basic and useful infromations.
*/
#define DBG_DMESG 3
/*
*Normal case with useful information
*about current SW or HW state.
*For example, Tx/Rx descriptor to fill,
*Tx/Rx descriptor completed status,
*SW protocol state change, dynamic
*mechanism state change and so on.
*/
#define DBG_LOUD 4
/*
*Normal case with detail execution
*flow or information.
*/
#define DBG_TRACE 5
/*--------------------------------------------------------------
Define the rt_trace components
--------------------------------------------------------------*/
#define COMP_ERR BIT(0)
#define COMP_FW BIT(1)
#define COMP_INIT BIT(2) /*For init/deinit */
#define COMP_RECV BIT(3) /*For Rx. */
#define COMP_SEND BIT(4) /*For Tx. */
#define COMP_MLME BIT(5) /*For MLME. */
#define COMP_SCAN BIT(6) /*For Scan. */
#define COMP_INTR BIT(7) /*For interrupt Related. */
#define COMP_LED BIT(8) /*For LED. */
#define COMP_SEC BIT(9) /*For sec. */
#define COMP_BEACON BIT(10) /*For beacon. */
#define COMP_RATE BIT(11) /*For rate. */
#define COMP_RXDESC BIT(12) /*For rx desc. */
#define COMP_DIG BIT(13) /*For DIG */
#define COMP_TXAGC BIT(14) /*For Tx power */
#define COMP_HIPWR BIT(15) /*For High Power Mechanism */
#define COMP_POWER BIT(16) /*For lps/ips/aspm. */
#define COMP_POWER_TRACKING BIT(17) /*For TX POWER TRACKING */
#define COMP_BB_POWERSAVING BIT(18)
#define COMP_SWAS BIT(19) /*For SW Antenna Switch */
#define COMP_RF BIT(20) /*For RF. */
#define COMP_TURBO BIT(21) /*For EDCA TURBO. */
#define COMP_RATR BIT(22)
#define COMP_CMD BIT(23)
#define COMP_EFUSE BIT(24)
#define COMP_QOS BIT(25)
#define COMP_MAC80211 BIT(26)
#define COMP_REGD BIT(27)
#define COMP_CHAN BIT(28)
#define COMP_EASY_CONCURRENT BIT(29)
#define COMP_BT_COEXIST BIT(30)
#define COMP_IQK BIT(31)
/*--------------------------------------------------------------
Define the rt_print components
--------------------------------------------------------------*/
/* Define EEPROM and EFUSE check module bit*/
#define EEPROM_W BIT(0)
#define EFUSE_PG BIT(1)
#define EFUSE_READ_ALL BIT(2)
/* Define init check for module bit*/
#define INIT_EEPROM BIT(0)
#define INIT_TxPower BIT(1)
#define INIT_IQK BIT(2)
#define INIT_RF BIT(3)
/* Define PHY-BB/RF/MAC check module bit */
#define PHY_BBR BIT(0)
#define PHY_BBW BIT(1)
#define PHY_RFR BIT(2)
#define PHY_RFW BIT(3)
#define PHY_MACR BIT(4)
#define PHY_MACW BIT(5)
#define PHY_ALLR BIT(6)
#define PHY_ALLW BIT(7)
#define PHY_TXPWR BIT(8)
#define PHY_PWRDIFF BIT(9)
/* Define Dynamic Mechanism check module bit --> FDM */
#define WA_IOT BIT(0)
#define DM_PWDB BIT(1)
#define DM_MONITOR BIT(2)
#define DM_DIG BIT(3)
#define DM_EDCA_TURBO BIT(4)
enum dbgp_flag_e {
FQOS = 0,
FTX = 1,
FRX = 2,
FSEC = 3,
FMGNT = 4,
FMLME = 5,
FRESOURCE = 6,
FBEACON = 7,
FISR = 8,
FPHY = 9,
FMP = 10,
FEEPROM = 11,
FPWR = 12,
FDM = 13,
FDBGCtrl = 14,
FC2H = 15,
FBT = 16,
FINIT = 17,
FIOCTL = 18,
DBGP_TYPE_MAX
};
#define RT_ASSERT(_exp , fmt) \
do { \
if (!(_exp)) { \
pr_debug("%s:%s(): ", KBUILD_MODNAME, \
__func__); \
pr_cont fmt; \
} \
} while (0)
#define RT_TRACE(comp, level, fmt, ...) \
do { \
if (unlikely(((comp) & rtlpriv->dbg.global_debugcomponents) && \
((level) <= rtlpriv->dbg.global_debuglevel))) { \
pr_debug("%d:<%lx> " fmt, \
rtlpriv->rtlhal.interfaceindex, \
in_interrupt(), ##__VA_ARGS__); \
} \
} while (0)
#define RTPRINT(rtlpriv, dbgtype, dbgflag, fmt, ...) \
do { \
if (unlikely(rtlpriv->dbg.dbgp_type[dbgtype] & dbgflag)) { \
pr_debug(KBUILD_MODNAME ": " fmt, \
##__VA_ARGS__); \
} \
} while (0)
#define RT_PRINT_DATA(rtlpriv, _comp, _level, _titlestring, _hexdata, \
_hexdatalen) \
do {\
if (unlikely(((_comp) & rtlpriv->dbg.global_debugcomponents) &&\
(_level <= rtlpriv->dbg.global_debuglevel))) { \
int __i; \
u8 *ptr = (u8 *)_hexdata; \
pr_debug("%s: ", KBUILD_MODNAME); \
pr_cont("In process \"%s\" (pid %i):", \
current->comm, \
current->pid); \
pr_cont(_titlestring); \
for (__i = 0; __i < (int)_hexdatalen; __i++) { \
pr_cont("%02X%s", ptr[__i], (((__i + 1) % 4) \
== 0) ? " " : " ");\
if (((__i + 1) % 16) == 0) \
pr_cont("\n"); \
} \
pr_cont("\n"); \
} \
} while (0)
void rtl92e_dbgp_flag_init(struct ieee80211_hw *hw);
void rtl_proc_add_one(struct ieee80211_hw *hw);
void rtl_proc_remove_one(struct ieee80211_hw *hw);
void rtl_proc_add_topdir(void);
void rtl_proc_remove_topdir(void);
#endif

1233
drivers/staging/rtl8192ee/efuse.c
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File diff suppressed because it is too large Load Diff

127
drivers/staging/rtl8192ee/efuse.h
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@ -1,127 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL_EFUSE_H_
#define __RTL_EFUSE_H_
#define EFUSE_IC_ID_OFFSET 506
/*
#define EFUSE_REAL_CONTENT_LEN 512
#define EFUSE_MAP_LEN 128
#define EFUSE_MAX_SECTION 16
#define EFUSE_MAX_WORD_UNIT 4
#define EFUSE_IC_ID_OFFSET 506
*/
#define EFUSE_MAX_WORD_UNIT 4
#define EFUSE_INIT_MAP 0
#define EFUSE_MODIFY_MAP 1
#define PG_STATE_HEADER 0x01
#define PG_STATE_WORD_0 0x02
#define PG_STATE_WORD_1 0x04
#define PG_STATE_WORD_2 0x08
#define PG_STATE_WORD_3 0x10
#define PG_STATE_DATA 0x20
#define PG_SWBYTE_H 0x01
#define PG_SWBYTE_L 0x02
#define _POWERON_DELAY_
#define _PRE_EXECUTE_READ_CMD_
#define EFUSE_REPEAT_THRESHOLD_ 3
#define EFUSE_ERROE_HANDLE 1
struct efuse_map {
u8 offset;
u8 word_start;
u8 byte_start;
u8 byte_cnts;
};
struct pgpkt_struct {
u8 offset;
u8 word_en;
u8 data[8];
};
enum efuse_data_item {
EFUSE_CHIP_ID = 0,
EFUSE_LDO_SETTING,
EFUSE_CLK_SETTING,
EFUSE_SDIO_SETTING,
EFUSE_CCCR,
EFUSE_SDIO_MODE,
EFUSE_OCR,
EFUSE_F0CIS,
EFUSE_F1CIS,
EFUSE_MAC_ADDR,
EFUSE_EEPROM_VER,
EFUSE_CHAN_PLAN,
EFUSE_TXPW_TAB
};
enum {
VOLTAGE_V25 = 0x03,
LDOE25_SHIFT = 28,
};
struct efuse_priv {
u8 id[2];
u8 ldo_setting[2];
u8 clk_setting[2];
u8 cccr;
u8 sdio_mode;
u8 ocr[3];
u8 cis0[17];
u8 cis1[48];
u8 mac_addr[6];
u8 eeprom_verno;
u8 channel_plan;
u8 tx_power_b[14];
u8 tx_power_g[14];
};
void read92e_efuse_byte(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
void efuse92e_initialize(struct ieee80211_hw *hw);
u8 stg_efuse_read_1byte(struct ieee80211_hw *hw, u16 address);
int stg_efuse_one_byte_read(struct ieee80211_hw *hw, u16 addr, u8 *data);
void efuse92e_write_1byte(struct ieee80211_hw *hw, u16 address, u8 value);
void read92e_efuse(struct ieee80211_hw *hw, u16 _offset,
u16 _size_byte, u8 *pbuf);
void efuse92e_shadow_read(struct ieee80211_hw *hw, u8 type,
u16 offset, u32 *value);
void efuse92e_shadow_write(struct ieee80211_hw *hw, u8 type,
u16 offset, u32 value);
bool efuse92e_shadow_update(struct ieee80211_hw *hw);
bool efuse92e_shadow_update_chk(struct ieee80211_hw *hw);
void stg_rtl_efuse92e_shadow_map_update(struct ieee80211_hw *hw);
void efuse92e_force_write_vendor_Id(struct ieee80211_hw *hw);
void efuse92e_re_pg_section(struct ieee80211_hw *hw, u8 section_idx);
#endif

2373
drivers/staging/rtl8192ee/pci.c
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File diff suppressed because it is too large Load Diff

342
drivers/staging/rtl8192ee/pci.h
View File

@ -1,342 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL_PCI_H__
#define __RTL_PCI_H__
#include <linux/pci.h>
/*
1: MSDU packet queue,
2: Rx Command Queue
*/
#define RTL_PCI_RX_MPDU_QUEUE 0
#define RTL_PCI_RX_CMD_QUEUE 1
#define RTL_PCI_MAX_RX_QUEUE 2
#define RTL_PCI_MAX_RX_COUNT 512/*64*/
#define RTL_PCI_MAX_TX_QUEUE_COUNT 9
#define RT_TXDESC_NUM 128
#define TX_DESC_NUM_92E 512
#define RT_TXDESC_NUM_BE_QUEUE 256
#define BK_QUEUE 0
#define BE_QUEUE 1
#define VI_QUEUE 2
#define VO_QUEUE 3
#define BEACON_QUEUE 4
#define TXCMD_QUEUE 5
#define MGNT_QUEUE 6
#define HIGH_QUEUE 7
#define HCCA_QUEUE 8
#define RTL_PCI_DEVICE(vend, dev, cfg) \
.vendor = (vend), \
.device = (dev), \
.subvendor = PCI_ANY_ID, \
.subdevice = PCI_ANY_ID,\
.driver_data = (kernel_ulong_t)&(cfg)
#define INTEL_VENDOR_ID 0x8086
#define SIS_VENDOR_ID 0x1039
#define ATI_VENDOR_ID 0x1002
#define ATI_DEVICE_ID 0x7914
#define AMD_VENDOR_ID 0x1022
#define PCI_MAX_BRIDGE_NUMBER 255
#define PCI_MAX_DEVICES 32
#define PCI_MAX_FUNCTION 8
#define PCI_CONF_ADDRESS 0x0CF8 /*PCI Configuration Space Address */
#define PCI_CONF_DATA 0x0CFC /*PCI Configuration Space Data */
#define PCI_CLASS_BRIDGE_DEV 0x06
#define PCI_SUBCLASS_BR_PCI_TO_PCI 0x04
#define PCI_CAPABILITY_ID_PCI_EXPRESS 0x10
#define PCI_CAP_ID_EXP 0x10
#define U1DONTCARE 0xFF
#define U2DONTCARE 0xFFFF
#define U4DONTCARE 0xFFFFFFFF
#define RTL_PCI_8192_DID 0x8192 /*8192 PCI-E */
#define RTL_PCI_8192SE_DID 0x8192 /*8192 SE */
#define RTL_PCI_8174_DID 0x8174 /*8192 SE */
#define RTL_PCI_8173_DID 0x8173 /*8191 SE Crab */
#define RTL_PCI_8172_DID 0x8172 /*8191 SE RE */
#define RTL_PCI_8171_DID 0x8171 /*8191 SE Unicron */
#define RTL_PCI_0045_DID 0x0045 /*8190 PCI for Ceraga */
#define RTL_PCI_0046_DID 0x0046 /*8190 Cardbus for Ceraga */
#define RTL_PCI_0044_DID 0x0044 /*8192e PCIE for Ceraga */
#define RTL_PCI_0047_DID 0x0047 /*8192e Express Card for Ceraga */
#define RTL_PCI_700F_DID 0x700F
#define RTL_PCI_701F_DID 0x701F
#define RTL_PCI_DLINK_DID 0x3304
#define RTL_PCI_8723AE_DID 0x8723 /*8723e */
#define RTL_PCI_8192CET_DID 0x8191 /*8192ce */
#define RTL_PCI_8192CE_DID 0x8178 /*8192ce */
#define RTL_PCI_8191CE_DID 0x8177 /*8192ce */
#define RTL_PCI_8188CE_DID 0x8176 /*8192ce */
#define RTL_PCI_8192CU_DID 0x8191 /*8192ce */
#define RTL_PCI_8192DE_DID 0x8193 /*8192de */
#define RTL_PCI_8192DE_DID2 0x002B /*92DE*/
#define RTL_PCI_8188EE_DID 0x8179 /*8188ee*/
#define RTL_PCI_8723BE_DID 0xB723 /*8723be*/
#define RTL_PCI_8192EE_DID 0x818B /*8192ee*/
#define RTL_PCI_8821AE_DID 0x8821 /*8821ae*/
#define RTL_PCI_8812AE_DID 0x8812 /*8812ae*/
/*8192 support 16 pages of IO registers*/
#define RTL_MEM_MAPPED_IO_RANGE_8190PCI 0x1000
#define RTL_MEM_MAPPED_IO_RANGE_8192PCIE 0x4000
#define RTL_MEM_MAPPED_IO_RANGE_8192SE 0x4000
#define RTL_MEM_MAPPED_IO_RANGE_8192CE 0x4000
#define RTL_MEM_MAPPED_IO_RANGE_8192DE 0x4000
#define RTL_PCI_REVISION_ID_8190PCI 0x00
#define RTL_PCI_REVISION_ID_8192PCIE 0x01
#define RTL_PCI_REVISION_ID_8192SE 0x10
#define RTL_PCI_REVISION_ID_8192CE 0x1
#define RTL_PCI_REVISION_ID_8192DE 0x0
#define RTL_DEFAULT_HARDWARE_TYPE HARDWARE_TYPE_RTL8192CE
enum pci_bridge_vendor {
PCI_BRIDGE_VENDOR_INTEL = 0x0, /*0b'0000,0001 */
PCI_BRIDGE_VENDOR_ATI, /*0b'0000,0010*/
PCI_BRIDGE_VENDOR_AMD, /*0b'0000,0100*/
PCI_BRIDGE_VENDOR_SIS, /*0b'0000,1000*/
PCI_BRIDGE_VENDOR_UNKNOWN, /*0b'0100,0000*/
PCI_BRIDGE_VENDOR_MAX,
};
struct rtl_pci_capabilities_header {
u8 capability_id;
u8 next;
};
/* In new TRX flow, Buffer_desc is new concept
* But TX wifi info == TX descriptor in old flow
* RX wifi info == RX descriptor in old flow */
struct rtl_tx_buffer_desc {
#if (RTL8192EE_SEG_NUM == 2)
u32 dword[2*(DMA_IS_64BIT + 1)*8]; /*seg = 8*/
#elif (RTL8192EE_SEG_NUM == 1)
u32 dword[2*(DMA_IS_64BIT + 1)*4]; /*seg = 4*/
#elif (RTL8192EE_SEG_NUM == 0)
u32 dword[2*(DMA_IS_64BIT + 1)*2]; /*seg = 2*/
#endif
} __packed;
struct rtl_tx_desc {/*old: tx desc new: tx wifi info*/
u32 dword[16];
} __packed;
struct rtl_rx_buffer_desc { /*rx buffer desc*/
u32 dword[2];
} __packed;
struct rtl_rx_desc { /*old: rx desc new: rx wifi info*/
u32 dword[8];
} __packed;
struct rtl_tx_cmd_desc {
u32 dword[16];
} __packed;
struct rtl8192_tx_ring {
struct rtl_tx_desc *desc; /*tx desc / tx wifi info*/
dma_addr_t dma; /*tx desc dma memory / tx wifi info dma memory*/
unsigned int idx;
unsigned int entries;
struct sk_buff_head queue;
/*add for new trx flow*/
struct rtl_tx_buffer_desc *buffer_desc; /*tx buffer descriptor*/
dma_addr_t buffer_desc_dma; /*tx bufferd desc dma memory*/
u16 avl_desc; /* available_desc_to_write */
u16 cur_tx_wp; /* current_tx_write_point */
u16 cur_tx_rp; /* current_tx_read_point */
};
struct rtl8192_rx_ring {
struct rtl_rx_desc *desc;/*for old trx flow, not uesd in new trx*/
/*dma matches either 'desc' or 'buffer_desc'*/
dma_addr_t dma;
unsigned int idx;
struct sk_buff *rx_buf[RTL_PCI_MAX_RX_COUNT];
/*add for new trx flow*/
struct rtl_rx_buffer_desc *buffer_desc; /*rx buffer descriptor*/
u16 next_rx_rp; /* next_rx_read_point */
};
struct rtl_pci {
struct pci_dev *pdev;
bool irq_enabled;
/*Tx */
struct rtl8192_tx_ring tx_ring[RTL_PCI_MAX_TX_QUEUE_COUNT];
int txringcount[RTL_PCI_MAX_TX_QUEUE_COUNT];
u32 transmit_config;
/*Rx */
struct rtl8192_rx_ring rx_ring[RTL_PCI_MAX_RX_QUEUE];
int rxringcount;
u16 rxbuffersize;
u32 receive_config;
/*irq */
u8 irq_alloc;
u32 irq_mask[2];
u32 sys_irq_mask;
/*Bcn control register setting */
u32 reg_bcn_ctrl_val;
/*ASPM*/ u8 const_pci_aspm;
u8 const_amdpci_aspm;
u8 const_hwsw_rfoff_d3;
u8 const_support_pciaspm;
/*pci-e bridge */
u8 const_hostpci_aspm_setting;
/*pci-e device */
u8 const_devicepci_aspm_setting;
/*If it supports ASPM, Offset[560h] = 0x40,
otherwise Offset[560h] = 0x00. */
bool b_support_aspm;
bool b_support_backdoor;
/*QOS & EDCA */
enum acm_method acm_method;
u16 shortretry_limit;
u16 longretry_limit;
/* MSI support */
bool msi_support;
bool using_msi;
};
struct mp_adapter {
u8 linkctrl_reg;
u8 busnumber;
u8 devnumber;
u8 funcnumber;
u8 pcibridge_busnum;
u8 pcibridge_devnum;
u8 pcibridge_funcnum;
u8 pcibridge_vendor;
u16 pcibridge_vendorid;
u16 pcibridge_deviceid;
u32 pcicfg_addrport;
u8 num4bytes;
u8 pcibridge_pciehdr_offset;
u8 pcibridge_linkctrlreg;
bool amd_l1_patch;
};
struct rtl_pci_priv {
struct rtl_pci dev;
struct mp_adapter ndis_adapter;
struct rtl_led_ctl ledctl;
struct bt_coexist_info btcoexist;
};
#define rtl_pcipriv(hw) (((struct rtl_pci_priv *)(rtl_priv(hw))->priv))
#define rtl_pcidev(pcipriv) (&((pcipriv)->dev))
int rtl92e_pci_reset_trx_ring(struct ieee80211_hw *hw);
extern struct rtl_intf_ops rtl92e_pci_ops;
int stg_rtl_pci_probe(struct pci_dev *pdev,
const struct pci_device_id *id);
void stg_rtl_pci_disconnect(struct pci_dev *pdev);
int stg_rtl_pci_suspend(struct device *dev);
int stg_rtl_pci_resume(struct device *dev);
static inline u8 pci_read8_sync(struct rtl_priv *rtlpriv, u32 addr)
{
return 0xff & readb((u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
}
static inline u16 pci_read16_sync(struct rtl_priv *rtlpriv, u32 addr)
{
return readw((u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
}
static inline u32 pci_read32_sync(struct rtl_priv *rtlpriv, u32 addr)
{
return readl((u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
}
static inline void pci_write8_async(struct rtl_priv *rtlpriv, u32 addr, u8 val)
{
writeb(val, (u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
}
static inline void pci_write16_async(struct rtl_priv *rtlpriv,
u32 addr, u16 val)
{
writew(val, (u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
}
static inline void pci_write32_async(struct rtl_priv *rtlpriv,
u32 addr, u32 val)
{
writel(val, (u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
}
static inline void rtl_pci_raw_write_port_ulong(u32 port, u32 val)
{
outl(val, port);
}
static inline void rtl_pci_raw_write_port_uchar(u32 port, u8 val)
{
outb(val, port);
}
static inline void rtl_pci_raw_read_port_uchar(u32 port, u8 *pval)
{
*pval = inb(port);
}
static inline void rtl_pci_raw_read_port_ushort(u32 port, u16 *pval)
{
*pval = inw(port);
}
static inline void rtl_pci_raw_read_port_ulong(u32 port, u32 *pval)
{
*pval = inl(port);
}
#endif

980
drivers/staging/rtl8192ee/ps.c
View File

@ -1,980 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "wifi.h"
#include "base.h"
#include "ps.h"
#include "btcoexist/rtl_btc.h"
bool stg_rtl_ps_enable_nic(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
bool init_status = true;
/*<1> reset trx ring */
if (rtlhal->interface == INTF_PCI)
rtlpriv->intf_ops->reset_trx_ring(hw);
if (is_hal_stop(rtlhal))
RT_TRACE(COMP_ERR, DBG_WARNING, "Driver is already down!\n");
/*<2> Enable Adapter */
rtlpriv->cfg->ops->hw_init(hw);
RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
/*init_status = false; */
/*<3> Enable Interrupt */
rtlpriv->cfg->ops->enable_interrupt(hw);
/*<enable timer> */
rtl92e_watch_dog_timer_callback((unsigned long)hw);
return init_status;
}
EXPORT_SYMBOL(stg_rtl_ps_enable_nic);
bool stg_rtl_ps_disable_nic(struct ieee80211_hw *hw)
{
bool status = true;
struct rtl_priv *rtlpriv = rtl_priv(hw);
/*<1> Stop all timer */
rtl92e_deinit_deferred_work(hw);
/*<2> Disable Interrupt */
rtlpriv->cfg->ops->disable_interrupt(hw);
/*<3> Disable Adapter */
rtlpriv->cfg->ops->hw_disable(hw);
return status;
}
EXPORT_SYMBOL(stg_rtl_ps_disable_nic);
bool stg_rtl_ps_set_rf_state(struct ieee80211_hw *hw,
enum rf_pwrstate state_toset,
u32 changesource, bool protect_or_not)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
enum rf_pwrstate rtstate;
bool b_actionallowed = false;
u16 rfwait_cnt = 0;
/*protect_or_not = true; */
if (protect_or_not)
goto no_protect;
/*
*Only one thread can change
*the RF state at one time, and others
*should wait to be executed.
*/
while (true) {
spin_lock(&rtlpriv->locks.rf_ps_lock);
if (ppsc->rfchange_inprogress) {
spin_unlock(&rtlpriv->locks.rf_ps_lock);
RT_TRACE(COMP_ERR, DBG_WARNING,
"RF Change in progress! Wait to set..state_toset(%d)\n",
state_toset);
/* Set RF after the previous action is done. */
while (ppsc->rfchange_inprogress) {
rfwait_cnt++;
mdelay(1);
/*
*Wait too long, return false to avoid
*to be stuck here.
*/
if (rfwait_cnt > 100)
return false;
}
} else {
ppsc->rfchange_inprogress = true;
spin_unlock(&rtlpriv->locks.rf_ps_lock);
break;
}
}
no_protect:
rtstate = ppsc->rfpwr_state;
switch (state_toset) {
case ERFON:
ppsc->rfoff_reason &= (~changesource);
if ((changesource == RF_CHANGE_BY_HW) &&
(ppsc->b_hwradiooff)) {
ppsc->b_hwradiooff = false;
}
if (!ppsc->rfoff_reason) {
ppsc->rfoff_reason = 0;
b_actionallowed = true;
}
break;
case ERFOFF:
if ((changesource == RF_CHANGE_BY_HW) &&
(!ppsc->b_hwradiooff)) {
ppsc->b_hwradiooff = true;
}
ppsc->rfoff_reason |= changesource;
b_actionallowed = true;
break;
case ERFSLEEP:
ppsc->rfoff_reason |= changesource;
b_actionallowed = true;
break;
default:
RT_TRACE(COMP_ERR, DBG_EMERG, "switch case not process\n");
break;
}
if (b_actionallowed)
rtlpriv->cfg->ops->set_rf_power_state(hw, state_toset);
if (!protect_or_not) {
spin_lock(&rtlpriv->locks.rf_ps_lock);
ppsc->rfchange_inprogress = false;
spin_unlock(&rtlpriv->locks.rf_ps_lock);
}
return b_actionallowed;
}
EXPORT_SYMBOL(stg_rtl_ps_set_rf_state);
static void _rtl_ps_inactive_ps(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
ppsc->b_swrf_processing = true;
if (ppsc->inactive_pwrstate == ERFON && rtlhal->interface == INTF_PCI) {
if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) &&
RT_IN_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM) &&
rtlhal->interface == INTF_PCI) {
rtlpriv->intf_ops->disable_aspm(hw);
RT_CLEAR_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM);
}
}
stg_rtl_ps_set_rf_state(hw, ppsc->inactive_pwrstate,
RF_CHANGE_BY_IPS, false);
if (ppsc->inactive_pwrstate == ERFOFF &&
rtlhal->interface == INTF_PCI) {
if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM &&
!RT_IN_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM)) {
rtlpriv->intf_ops->enable_aspm(hw);
RT_SET_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM);
}
}
ppsc->b_swrf_processing = false;
}
void rtl92e_ips_nic_off_wq_callback(void *data)
{
struct rtl_works *rtlworks =
container_of_dwork_rtl(data, struct rtl_works, ips_nic_off_wq);
struct ieee80211_hw *hw = rtlworks->hw;
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
enum rf_pwrstate rtstate;
if (mac->opmode != NL80211_IFTYPE_STATION) {
RT_TRACE(COMP_ERR, DBG_WARNING, "not station return\n");
return;
}
if (mac->p2p_in_use)
return;
if (mac->link_state > MAC80211_NOLINK)
return;
if (is_hal_stop(rtlhal))
return;
if (rtlpriv->sec.being_setkey)
return;
if (rtlpriv->cfg->ops->bt_turn_off_bt_coexist_before_enter_lps)
rtlpriv->cfg->ops->bt_turn_off_bt_coexist_before_enter_lps(hw);
if (ppsc->b_inactiveps) {
rtstate = ppsc->rfpwr_state;
/*
*Do not enter IPS in the following conditions:
*(1) RF is already OFF or Sleep
*(2) b_swrf_processing (indicates the IPS is still under going)
*(3) Connectted (only disconnected can trigger IPS)
*(4) IBSS (send Beacon)
*(5) AP mode (send Beacon)
*(6) monitor mode (rcv packet)
*/
if (rtstate == ERFON &&
!ppsc->b_swrf_processing &&
(mac->link_state == MAC80211_NOLINK) &&
!mac->act_scanning) {
RT_TRACE(COMP_RF, DBG_LOUD,
"IPSEnter(): Turn off RF\n");
ppsc->inactive_pwrstate = ERFOFF;
ppsc->b_in_powersavemode = true;
/* call before RF off */
if (rtlpriv->cfg->ops->get_btc_status())
rtlpriv->btcoexist.btc_ops->btc_ips_notify(rtlpriv,
ppsc->inactive_pwrstate);
/*rtl92e_pci_reset_trx_ring(hw); */
_rtl_ps_inactive_ps(hw);
}
}
}
void rtl92e_ips_nic_off(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
/*
*because when link with ap, mac80211 will ask us
*to disable nic quickly after scan before linking,
*this will cause link failed, so we delay 100ms here
*/
queue_delayed_work(rtlpriv->works.rtl_wq,
&rtlpriv->works.ips_nic_off_wq, MSECS(100));
}
/* NOTICE: any opmode should exc nic_on, or disable without
* nic_on may something wrong, like adhoc TP*/
void rtl92e_ips_nic_on(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
enum rf_pwrstate rtstate;
cancel_delayed_work(&rtlpriv->works.ips_nic_off_wq);
spin_lock(&rtlpriv->locks.ips_lock);
if (ppsc->b_inactiveps) {
rtstate = ppsc->rfpwr_state;
if (rtstate != ERFON &&
!ppsc->b_swrf_processing &&
ppsc->rfoff_reason <= RF_CHANGE_BY_IPS) {
ppsc->inactive_pwrstate = ERFON;
ppsc->b_in_powersavemode = false;
_rtl_ps_inactive_ps(hw);
/* call after RF on */
if (rtlpriv->cfg->ops->get_btc_status())
rtlpriv->btcoexist.btc_ops->btc_ips_notify(rtlpriv,
ppsc->inactive_pwrstate);
}
}
spin_unlock(&rtlpriv->locks.ips_lock);
}
/*for FW LPS*/
/*
*Determine if we can set Fw into PS mode
*in current condition.Return true if it
*can enter PS mode.
*/
static bool rtl_get_fwlps_doze(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
u32 ps_timediff;
ps_timediff = jiffies_to_msecs(jiffies -
ppsc->last_delaylps_stamp_jiffies);
if (ps_timediff < 2000) {
RT_TRACE(COMP_POWER, DBG_LOUD,
"Delay enter Fw LPS for DHCP, ARP, or EAPOL exchanging state\n");
return false;
}
if (mac->link_state != MAC80211_LINKED)
return false;
if (mac->opmode == NL80211_IFTYPE_ADHOC)
return false;
return true;
}
/* Change current and default preamble mode.*/
void rtl_lps_set_psmode(struct ieee80211_hw *hw, u8 rt_psmode)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
bool enter_fwlps;
if (mac->opmode == NL80211_IFTYPE_ADHOC)
return;
if (mac->link_state != MAC80211_LINKED)
return;
if (ppsc->dot11_psmode == rt_psmode)
return;
/* Update power save mode configured. */
ppsc->dot11_psmode = rt_psmode;
/*
*<FW control LPS>
*1. Enter PS mode
* Set RPWM to Fw to turn RF off and send H2C fw_pwrmode
* cmd to set Fw into PS mode.
*2. Leave PS mode
* Send H2C fw_pwrmode cmd to Fw to set Fw into Active
* mode and set RPWM to turn RF on.
*/
if ((ppsc->b_fwctrl_lps) && ppsc->report_linked) {
if (ppsc->dot11_psmode == EACTIVE) {
RT_TRACE(COMP_RF, DBG_DMESG,
"FW LPS leave ps_mode:%x\n",
FW_PS_ACTIVE_MODE);
enter_fwlps = false;
ppsc->pwr_mode = FW_PS_ACTIVE_MODE;
ppsc->smart_ps = 0;
rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_LPS_ACTION,
(u8 *)(&enter_fwlps));
if (ppsc->p2p_ps_info.opp_ps)
rtl92e_p2p_ps_cmd(hw , P2P_PS_ENABLE);
if (rtlpriv->cfg->ops->get_btc_status())
rtlpriv->btcoexist.btc_ops->btc_lps_notify(rtlpriv, rt_psmode);
} else {
if (rtl_get_fwlps_doze(hw)) {
RT_TRACE(COMP_RF, DBG_DMESG,
"FW LPS enter ps_mode:%x\n",
ppsc->fwctrl_psmode);
if (rtlpriv->cfg->ops->get_btc_status())
rtlpriv->btcoexist.btc_ops->btc_lps_notify(rtlpriv, rt_psmode);
enter_fwlps = true;
ppsc->pwr_mode = ppsc->fwctrl_psmode;
ppsc->smart_ps = 2;
rtlpriv->cfg->ops->set_hw_reg(hw,
HW_VAR_FW_LPS_ACTION,
(u8 *)(&enter_fwlps));
} else {
/* Reset the power save related parameters. */
ppsc->dot11_psmode = EACTIVE;
}
}
}
}
/*Enter the leisure power save mode.*/
void rtl92e_lps_enter(struct ieee80211_hw *hw)
{
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
struct rtl_priv *rtlpriv = rtl_priv(hw);
unsigned long flag;
if (!ppsc->b_fwctrl_lps)
return;
if (rtlpriv->sec.being_setkey)
return;
if (rtlpriv->link_info.b_busytraffic)
return;
/*sleep after linked 10s, to let DHCP and 4-way handshake ok enough!! */
if (mac->cnt_after_linked < 5)
return;
if (mac->opmode == NL80211_IFTYPE_ADHOC)
return;
if (mac->link_state != MAC80211_LINKED)
return;
spin_lock_irqsave(&rtlpriv->locks.lps_lock, flag);
/* Idle for a while if we connect to AP a while ago. */
if (mac->cnt_after_linked >= 2) {
if (ppsc->dot11_psmode == EACTIVE) {
RT_TRACE(COMP_POWER, DBG_LOUD,
"Enter 802.11 power save mode...\n");
rtl_lps_set_psmode(hw, EAUTOPS);
}
}
spin_unlock_irqrestore(&rtlpriv->locks.lps_lock, flag);
}
EXPORT_SYMBOL(rtl92e_lps_enter);
/*Leave the leisure power save mode.*/
void rtl92e_lps_leave(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
unsigned long flag;
spin_lock_irqsave(&rtlpriv->locks.lps_lock, flag);
if (ppsc->b_fwctrl_lps) {
if (ppsc->dot11_psmode != EACTIVE) {
if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM &&
RT_IN_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM) &&
rtlhal->interface == INTF_PCI) {
rtlpriv->intf_ops->disable_aspm(hw);
RT_CLEAR_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM);
}
RT_TRACE(COMP_POWER, DBG_LOUD,
"Busy Traffic,Leave 802.11 power save..\n");
rtl_lps_set_psmode(hw, EACTIVE);
}
}
spin_unlock_irqrestore(&rtlpriv->locks.lps_lock, flag);
}
EXPORT_SYMBOL(rtl92e_lps_leave);
/* For sw LPS*/
void rtl92e_swlps_beacon(struct ieee80211_hw *hw, void *data, unsigned int len)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
struct ieee80211_hdr *hdr = (void *)data;
struct ieee80211_tim_ie *tim_ie;
u8 *tim;
u8 tim_len;
bool u_buffed;
bool m_buffed;
if (mac->opmode != NL80211_IFTYPE_STATION)
return;
if (!rtlpriv->psc.b_swctrl_lps)
return;
if (rtlpriv->mac80211.link_state != MAC80211_LINKED)
return;
if (!rtlpriv->psc.sw_ps_enabled)
return;
if (rtlpriv->psc.b_fwctrl_lps)
return;
if (likely(!(hw->conf.flags & IEEE80211_CONF_PS)))
return;
/* check if this really is a beacon */
if (!ieee80211_is_beacon(hdr->frame_control))
return;
/* min. beacon length + FCS_LEN */
if (len <= 40 + FCS_LEN)
return;
/* and only beacons from the associated BSSID, please */
if (!ether_addr_equal(hdr->addr3, rtlpriv->mac80211.bssid))
return;
rtlpriv->psc.last_beacon = jiffies;
tim = rtl92e_find_ie(data, len - FCS_LEN, WLAN_EID_TIM);
if (!tim)
return;
if (tim[1] < sizeof(*tim_ie))
return;
tim_len = tim[1];
tim_ie = (struct ieee80211_tim_ie *)&tim[2];
if (!WARN_ON_ONCE(!hw->conf.ps_dtim_period))
rtlpriv->psc.dtim_counter = tim_ie->dtim_count;
/* Check whenever the PHY can be turned off again. */
/* 1. What about buffered unicast traffic for our AID? */
u_buffed = ieee80211_check_tim(tim_ie, tim_len,
rtlpriv->mac80211.assoc_id);
/* 2. Maybe the AP wants to send multicast/broadcast data? */
m_buffed = tim_ie->bitmap_ctrl & 0x01;
rtlpriv->psc.multi_buffered = m_buffed;
/* unicast will process by mac80211 through
* set ~IEEE80211_CONF_PS, So we just check
* multicast frames here */
if (!m_buffed) {/*&&) { !rtlpriv->psc.tx_doing) { */
/* back to low-power land. and delay is
* prevent null power save frame tx fail */
queue_delayed_work(rtlpriv->works.rtl_wq,
&rtlpriv->works.ps_work, MSECS(5));
} else {
RT_TRACE(COMP_POWER, DBG_DMESG,
"u_bufferd: %x, m_buffered: %x\n",
u_buffed, m_buffed);
}
}
void rtl92e_swlps_rf_awake(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
unsigned long flag;
if (!rtlpriv->psc.b_swctrl_lps)
return;
if (mac->link_state != MAC80211_LINKED)
return;
if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM &&
RT_IN_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM)) {
rtlpriv->intf_ops->disable_aspm(hw);
RT_CLEAR_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM);
}
spin_lock_irqsave(&rtlpriv->locks.lps_lock, flag);
stg_rtl_ps_set_rf_state(hw, ERFON, RF_CHANGE_BY_PS, false);
spin_unlock_irqrestore(&rtlpriv->locks.lps_lock, flag);
}
void rtl92e_swlps_rfon_wq_callback(void *data)
{
struct rtl_works *rtlworks =
container_of_dwork_rtl(data, struct rtl_works, ps_rfon_wq);
struct ieee80211_hw *hw = rtlworks->hw;
rtl92e_swlps_rf_awake(hw);
}
void rtl92e_swlps_rf_sleep(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
unsigned long flag;
u8 sleep_intv;
if (!rtlpriv->psc.sw_ps_enabled)
return;
if ((rtlpriv->sec.being_setkey) ||
(mac->opmode == NL80211_IFTYPE_ADHOC))
return;
/*sleep after linked 10s, to let DHCP and 4-way handshake ok enough!! */
if ((mac->link_state != MAC80211_LINKED) || (mac->cnt_after_linked < 5))
return;
if (rtlpriv->link_info.b_busytraffic)
return;
spin_lock(&rtlpriv->locks.rf_ps_lock);
if (rtlpriv->psc.rfchange_inprogress) {
spin_unlock(&rtlpriv->locks.rf_ps_lock);
return;
}
spin_unlock(&rtlpriv->locks.rf_ps_lock);
spin_lock_irqsave(&rtlpriv->locks.lps_lock, flag);
stg_rtl_ps_set_rf_state(hw, ERFSLEEP, RF_CHANGE_BY_PS , false);
spin_unlock_irqrestore(&rtlpriv->locks.lps_lock, flag);
if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM &&
!RT_IN_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM)) {
rtlpriv->intf_ops->enable_aspm(hw);
RT_SET_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM);
}
/* here is power save alg, when this beacon is DTIM
* we will set sleep time to dtim_period * n;
* when this beacon is not DTIM, we will set sleep
* time to sleep_intv = rtlpriv->psc.dtim_counter or
* MAX_SW_LPS_SLEEP_INTV(default set to 5) */
if (rtlpriv->psc.dtim_counter == 0) {
if (hw->conf.ps_dtim_period == 1)
sleep_intv = hw->conf.ps_dtim_period * 2;
else
sleep_intv = hw->conf.ps_dtim_period;
} else {
sleep_intv = rtlpriv->psc.dtim_counter;
}
if (sleep_intv > MAX_SW_LPS_SLEEP_INTV)
sleep_intv = MAX_SW_LPS_SLEEP_INTV;
/* this print should always be dtim_conter = 0 &
* sleep = dtim_period, that meaons, we should
* awake before every dtim */
RT_TRACE(COMP_POWER, DBG_DMESG,
"dtim_counter:%x will sleep :%d beacon_intv\n",
rtlpriv->psc.dtim_counter, sleep_intv);
/* we tested that 40ms is enough for sw & hw sw delay */
queue_delayed_work(rtlpriv->works.rtl_wq, &rtlpriv->works.ps_rfon_wq,
MSECS(sleep_intv*mac->vif->bss_conf.beacon_int-40));
}
void rtl92e_swlps_wq_callback(void *data)
{
struct rtl_works *rtlworks =
container_of_dwork_rtl(data, struct rtl_works, ps_work);
struct ieee80211_hw *hw = rtlworks->hw;
struct rtl_priv *rtlpriv = rtl_priv(hw);
bool ps = false;
ps = (hw->conf.flags & IEEE80211_CONF_PS);
/* we can sleep after ps null send ok */
if (rtlpriv->psc.state_inap) {
rtl92e_swlps_rf_sleep(hw);
if (rtlpriv->psc.state && !ps) {
rtlpriv->psc.sleep_ms =
jiffies_to_msecs(jiffies -
rtlpriv->psc.last_action);
}
if (ps)
rtlpriv->psc.last_slept = jiffies;
rtlpriv->psc.last_action = jiffies;
rtlpriv->psc.state = ps;
}
}
static void rtl_p2p_noa_ie(struct ieee80211_hw *hw, void *data,
unsigned int len)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct ieee80211_mgmt *mgmt = (void *)data;
struct rtl_p2p_ps_info *p2pinfo = &(rtlpriv->psc.p2p_ps_info);
u8 *pos, *end, *ie;
u16 noa_len;
static u8 p2p_oui_ie_type[4] = {0x50, 0x6f, 0x9a, 0x09};
u8 noa_num, index , i, noa_index = 0;
bool find_p2p_ie = false , find_p2p_ps_ie = false;
pos = (u8 *)mgmt->u.beacon.variable;
end = data + len;
ie = NULL;
while (pos + 1 < end) {
if (pos + 2 + pos[1] > end)
return;
if (pos[0] == 221 && pos[1] > 4) {
if (memcmp(&pos[2], p2p_oui_ie_type, 4) == 0) {
ie = pos + 2+4;
break;
}
}
pos += 2 + pos[1];
}
if (ie == NULL)
return;
find_p2p_ie = true;
/*to find noa ie*/
while (ie + 1 < end) {
noa_len = READEF2BYTE((__le16 *)&ie[1]);
if (ie + 3 + ie[1] > end)
return;
if (ie[0] == 12) {
find_p2p_ps_ie = true;
if ((noa_len - 2) % 13 != 0) {
RT_TRACE(COMP_INIT, DBG_LOUD,
"P2P notice of absence: invalid length%d\n",
noa_len);
return;
}
noa_num = (noa_len - 2) / 13;
noa_index = ie[3];
if (rtlpriv->psc.p2p_ps_info.p2p_ps_mode ==
P2P_PS_NONE || noa_index != p2pinfo->noa_index) {
RT_TRACE(COMP_FW, DBG_LOUD, "update NOA ie\n");
p2pinfo->noa_index = noa_index;
p2pinfo->opp_ps = (ie[4] >> 7);
p2pinfo->ctwindow = ie[4] & 0x7F;
p2pinfo->noa_num = noa_num;
index = 5;
for (i = 0; i < noa_num; i++) {
p2pinfo->noa_count_type[i] =
READEF1BYTE(ie+index);
index += 1;
p2pinfo->noa_duration[i] =
READEF4BYTE((__le32 *)ie+index);
index += 4;
p2pinfo->noa_interval[i] =
READEF4BYTE((__le32 *)ie+index);
index += 4;
p2pinfo->noa_start_time[i] =
READEF4BYTE((__le32 *)ie+index);
index += 4;
}
if (p2pinfo->opp_ps == 1) {
p2pinfo->p2p_ps_mode = P2P_PS_CTWINDOW;
/* Driver should wait LPS
* entering CTWindow*/
if (rtlpriv->psc.b_fw_current_inpsmode) {
rtl92e_p2p_ps_cmd(hw,
P2P_PS_ENABLE);
}
} else if (p2pinfo->noa_num > 0) {
p2pinfo->p2p_ps_mode = P2P_PS_NOA;
rtl92e_p2p_ps_cmd(hw, P2P_PS_ENABLE);
} else if (p2pinfo->p2p_ps_mode > P2P_PS_NONE) {
rtl92e_p2p_ps_cmd(hw, P2P_PS_DISABLE);
}
}
break;
}
ie += 3 + noa_len;
}
if (find_p2p_ie) {
if ((p2pinfo->p2p_ps_mode > P2P_PS_NONE) &&
(!find_p2p_ps_ie))
rtl92e_p2p_ps_cmd(hw, P2P_PS_DISABLE);
}
}
static void rtl_p2p_action_ie(struct ieee80211_hw *hw, void *data,
unsigned int len)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct ieee80211_mgmt *mgmt = (void *)data;
struct rtl_p2p_ps_info *p2pinfo = &(rtlpriv->psc.p2p_ps_info);
bool find_p2p_ie = false, find_p2p_ps_ie = false;
u8 noa_num, index, i, noa_index = 0;
u8 *pos, *end, *ie;
u16 noa_len;
static u8 p2p_oui_ie_type[4] = {0x50, 0x6f, 0x9a, 0x09};
pos = (u8 *)&mgmt->u.action.category;
end = data + len;
ie = NULL;
if (pos[0] == 0x7f) {
if (memcmp(&pos[1], p2p_oui_ie_type, 4) == 0)
ie = pos + 3+4;
}
if (ie == NULL)
return;
find_p2p_ie = true;
RT_TRACE(COMP_FW, DBG_LOUD, "action frame find P2P IE.\n");
/*to find noa ie*/
while (ie + 1 < end) {
noa_len = READEF2BYTE((__le16 *)&ie[1]);
if (ie + 3 + ie[1] > end)
return;
if (ie[0] == 12) {
RT_TRACE(COMP_FW, DBG_LOUD, "find NOA IE\n");
RT_PRINT_DATA(rtlpriv, COMP_FW, DBG_LOUD, "noa ie ",
ie, noa_len);
find_p2p_ps_ie = true;
if ((noa_len - 2) % 13 != 0) {
RT_TRACE(COMP_FW, DBG_LOUD,
"P2P notice of absence: invalid length%d\n",
noa_len);
return;
}
noa_num = (noa_len - 2) / 13;
noa_index = ie[3];
if (rtlpriv->psc.p2p_ps_info.p2p_ps_mode ==
P2P_PS_NONE ||
noa_index != p2pinfo->noa_index) {
p2pinfo->noa_index = noa_index;
p2pinfo->opp_ps = (ie[4] >> 7);
p2pinfo->ctwindow = ie[4] & 0x7F;
p2pinfo->noa_num = noa_num;
index = 5;
for (i = 0; i < noa_num; i++) {
p2pinfo->noa_count_type[i] =
READEF1BYTE(ie+index);
index += 1;
p2pinfo->noa_duration[i] =
READEF4BYTE((__le32 *)ie+index);
index += 4;
p2pinfo->noa_interval[i] =
READEF4BYTE((__le32 *)ie+index);
index += 4;
p2pinfo->noa_start_time[i] =
READEF4BYTE((__le32 *)ie+index);
index += 4;
}
if (p2pinfo->opp_ps == 1) {
p2pinfo->p2p_ps_mode = P2P_PS_CTWINDOW;
/* Driver should wait LPS
* entering CTWindow */
if (rtlpriv->psc.b_fw_current_inpsmode) {
rtl92e_p2p_ps_cmd(hw,
P2P_PS_ENABLE);
}
} else if (p2pinfo->noa_num > 0) {
p2pinfo->p2p_ps_mode = P2P_PS_NOA;
rtl92e_p2p_ps_cmd(hw, P2P_PS_ENABLE);
} else if (p2pinfo->p2p_ps_mode > P2P_PS_NONE) {
rtl92e_p2p_ps_cmd(hw, P2P_PS_DISABLE);
}
}
break;
}
ie += 3 + noa_len;
}
}
void rtl92e_p2p_ps_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_ps_ctl *rtlps = rtl_psc(rtl_priv(hw));
struct rtl_p2p_ps_info *p2pinfo = &(rtlpriv->psc.p2p_ps_info);
RT_TRACE(COMP_FW, DBG_LOUD, "p2p state %x\n", p2p_ps_state);
switch (p2p_ps_state) {
case P2P_PS_DISABLE:
p2pinfo->p2p_ps_state = p2p_ps_state;
rtlpriv->cfg->ops->set_hw_reg(hw,
HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
(u8 *)(&p2p_ps_state));
p2pinfo->noa_index = 0;
p2pinfo->ctwindow = 0;
p2pinfo->opp_ps = 0;
p2pinfo->noa_num = 0;
p2pinfo->p2p_ps_mode = P2P_PS_NONE;
if (rtlps->b_fw_current_inpsmode) {
if (rtlps->smart_ps == 0) {
rtlps->smart_ps = 2;
rtlpriv->cfg->ops->set_hw_reg(hw,
HW_VAR_H2C_FW_PWRMODE,
(u8 *)(&rtlps->pwr_mode));
}
}
break;
case P2P_PS_ENABLE:
if (p2pinfo->p2p_ps_mode > P2P_PS_NONE) {
p2pinfo->p2p_ps_state = p2p_ps_state;
if (p2pinfo->ctwindow > 0) {
if (rtlps->smart_ps != 0) {
rtlps->smart_ps = 0;
rtlpriv->cfg->ops->set_hw_reg(
hw, HW_VAR_H2C_FW_PWRMODE,
(u8 *)(&rtlps->pwr_mode));
}
}
rtlpriv->cfg->ops->set_hw_reg(hw,
HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
(u8 *)(&p2p_ps_state));
}
break;
case P2P_PS_SCAN:
case P2P_PS_SCAN_DONE:
case P2P_PS_ALLSTASLEEP:
if (p2pinfo->p2p_ps_mode > P2P_PS_NONE) {
p2pinfo->p2p_ps_state = p2p_ps_state;
rtlpriv->cfg->ops->set_hw_reg(hw,
HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
(u8 *)(&p2p_ps_state));
}
break;
default:
break;
}
RT_TRACE(COMP_FW, DBG_LOUD, " ctwindow %x oppps %x\n",
p2pinfo->ctwindow , p2pinfo->opp_ps);
RT_TRACE(COMP_FW, DBG_LOUD,
"count %x duration %x index %x interval %x start time %x noa num %x\n",
p2pinfo->noa_count_type[0],
p2pinfo->noa_duration[0],
p2pinfo->noa_index,
p2pinfo->noa_interval[0],
p2pinfo->noa_start_time[0],
p2pinfo->noa_num);
RT_TRACE(COMP_FW, DBG_LOUD, "end\n");
}
void rtl92e_p2p_info(struct ieee80211_hw *hw, void *data, unsigned int len)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
struct ieee80211_hdr *hdr = (void *)data;
if (!mac->p2p)
return;
if (mac->link_state != MAC80211_LINKED)
return;
/* min. beacon length + FCS_LEN */
if (len <= 40 + FCS_LEN)
return;
/* and only beacons from the associated BSSID, please */
if (!ether_addr_equal(hdr->addr3, rtlpriv->mac80211.bssid))
return;
/* check if this really is a beacon */
if (!(ieee80211_is_beacon(hdr->frame_control) ||
ieee80211_is_probe_resp(hdr->frame_control) ||
ieee80211_is_action(hdr->frame_control)))
return;
if (ieee80211_is_action(hdr->frame_control))
rtl_p2p_action_ie(hw , data , len - FCS_LEN);
else
rtl_p2p_noa_ie(hw , data , len - FCS_LEN);
}

52
drivers/staging/rtl8192ee/ps.h
View File

@ -1,52 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __REALTEK_RTL_PCI_PS_H__
#define __REALTEK_RTL_PCI_PS_H__
#define MAX_SW_LPS_SLEEP_INTV 5
bool stg_rtl_ps_set_rf_state(struct ieee80211_hw *hw,
enum rf_pwrstate state_toset, u32 changesource,
bool protect_or_not);
bool stg_rtl_ps_enable_nic(struct ieee80211_hw *hw);
bool stg_rtl_ps_disable_nic(struct ieee80211_hw *hw);
void rtl92e_ips_nic_off(struct ieee80211_hw *hw);
void rtl92e_ips_nic_on(struct ieee80211_hw *hw);
void rtl92e_ips_nic_off_wq_callback(void *data);
void rtl92e_lps_enter(struct ieee80211_hw *hw);
void rtl92e_lps_leave(struct ieee80211_hw *hw);
void rtl_lps_set_psmode(struct ieee80211_hw *hw, u8 rt_psmode);
void rtl92e_swlps_beacon(struct ieee80211_hw *hw, void *data, unsigned int len);
void rtl92e_swlps_wq_callback(void *data);
void rtl92e_swlps_rfon_wq_callback(void *data);
void rtl92e_swlps_rf_awake(struct ieee80211_hw *hw);
void rtl92e_swlps_rf_sleep(struct ieee80211_hw *hw);
void rtl92e_p2p_ps_cmd(struct ieee80211_hw *hw , u8 p2p_ps_state);
void rtl92e_p2p_info(struct ieee80211_hw *hw, void *data, unsigned int len);
#endif

290
drivers/staging/rtl8192ee/rc.c
View File

@ -1,290 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "wifi.h"
#include "base.h"
#include "rc.h"
/*
*Finds the highest rate index we can use
*if skb is special data like DHCP/EAPOL, we set should
*it to lowest rate CCK_1M, otherwise we set rate to
*highest rate based on wireless mode used for iwconfig
*show Tx rate.
*/
static u8 _rtl_rc_get_highest_rix(struct rtl_priv *rtlpriv,
struct ieee80211_sta *sta,
struct sk_buff *skb, bool not_data)
{
struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
struct rtl_sta_info *sta_entry = NULL;
u8 wireless_mode = 0;
/*
*this rate is no use for true rate, firmware
*will control rate at all it just used for
*1.show in iwconfig in B/G mode
*2.in stg_rtl_get_tcb_desc when we check rate is
* 1M we will not use FW rate but user rate.
*/
if (sta) {
sta_entry = (struct rtl_sta_info *)sta->drv_priv;
wireless_mode = sta_entry->wireless_mode;
}
if (rtl92e_is_special_data(rtlpriv->mac80211.hw, skb, true) ||
not_data) {
return 0;
} else {
if (rtlhal->current_bandtype == BAND_ON_2_4G) {
if (wireless_mode == WIRELESS_MODE_B) {
return B_MODE_MAX_RIX;
} else if (wireless_mode == WIRELESS_MODE_G) {
return G_MODE_MAX_RIX;
} else if (wireless_mode == WIRELESS_MODE_N_24G) {
if (get_rf_type(rtlphy) != RF_2T2R)
return N_MODE_MCS7_RIX;
else
return N_MODE_MCS15_RIX;
} else if (wireless_mode == WIRELESS_MODE_AC_24G) {
return AC_MODE_MCS9_RIX;
} else {
return 0;
}
} else {
if (wireless_mode == WIRELESS_MODE_A) {
return A_MODE_MAX_RIX;
} else if (wireless_mode == WIRELESS_MODE_N_5G) {
if (get_rf_type(rtlphy) != RF_2T2R)
return N_MODE_MCS7_RIX;
else
return N_MODE_MCS15_RIX;
} else if (wireless_mode == WIRELESS_MODE_AC_5G) {
return AC_MODE_MCS9_RIX;
} else {
return 0;
}
}
}
}
static void _rtl_rc_rate_set_series(struct rtl_priv *rtlpriv,
struct ieee80211_sta *sta,
struct ieee80211_tx_rate *rate,
struct ieee80211_tx_rate_control *txrc,
u8 tries, char rix, int rtsctsenable,
bool not_data)
{
struct rtl_mac *mac = rtl_mac(rtlpriv);
u8 sgi_20 = 0, sgi_40 = 0, sgi_80 = 0;
if (sta) {
sgi_20 = sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20;
sgi_40 = sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40;
sgi_80 = sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80;
}
rate->count = tries;
rate->idx = rix >= 0x00 ? rix : 0x00;
if (!not_data) {
if (txrc->short_preamble)
rate->flags |= IEEE80211_TX_RC_USE_SHORT_PREAMBLE;
if (mac->opmode == NL80211_IFTYPE_AP ||
mac->opmode == NL80211_IFTYPE_ADHOC) {
if (sta && (sta->ht_cap.cap &
IEEE80211_HT_CAP_SUP_WIDTH_20_40))
rate->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
if (sta && (sta->vht_cap.vht_supported))
rate->flags |= IEEE80211_TX_RC_80_MHZ_WIDTH;
} else {
if (mac->bw_40)
rate->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
if (mac->bw_80)
rate->flags |= IEEE80211_TX_RC_80_MHZ_WIDTH;
}
if (sgi_20 || sgi_40 || sgi_80)
rate->flags |= IEEE80211_TX_RC_SHORT_GI;
if (sta && sta->ht_cap.ht_supported)
rate->flags |= IEEE80211_TX_RC_MCS;
if (sta && sta->vht_cap.vht_supported)
rate->flags |= IEEE80211_TX_RC_VHT_MCS;
}
}
static void rtl_get_rate(void *ppriv, struct ieee80211_sta *sta,
void *priv_sta,
struct ieee80211_tx_rate_control *txrc)
{
struct rtl_priv *rtlpriv = ppriv;
struct sk_buff *skb = txrc->skb;
struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
struct ieee80211_tx_rate *rates = tx_info->control.rates;
__le16 fc = rtl_get_fc(skb);
u8 try_per_rate, i, rix;
bool not_data = !ieee80211_is_data(fc);
if (rate_control_send_low(sta, priv_sta, txrc))
return;
rix = _rtl_rc_get_highest_rix(rtlpriv, sta, skb, not_data);
try_per_rate = 1;
_rtl_rc_rate_set_series(rtlpriv, sta, &rates[0], txrc,
try_per_rate, rix, 1, not_data);
if (!not_data) {
for (i = 1; i < 4; i++)
_rtl_rc_rate_set_series(rtlpriv, sta, &rates[i],
txrc, i, (rix - i), 1,
not_data);
}
}
static bool _rtl_tx_aggr_check(struct rtl_priv *rtlpriv,
struct rtl_sta_info *sta_entry, u16 tid)
{
struct rtl_mac *mac = rtl_mac(rtlpriv);
if (mac->act_scanning)
return false;
if (mac->opmode == NL80211_IFTYPE_STATION &&
mac->cnt_after_linked < 3)
return false;
if (sta_entry->tids[tid].agg.agg_state == RTL_AGG_STOP)
return true;
return false;
}
/*mac80211 Rate Control callbacks*/
static void rtl_tx_status(void *ppriv,
struct ieee80211_supported_band *sband,
struct ieee80211_sta *sta, void *priv_sta,
struct sk_buff *skb)
{
struct rtl_priv *rtlpriv = ppriv;
struct rtl_mac *mac = rtl_mac(rtlpriv);
struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
__le16 fc = rtl_get_fc(skb);
struct rtl_sta_info *sta_entry;
if (!priv_sta || !ieee80211_is_data(fc))
return;
if (rtl92e_is_special_data(mac->hw, skb, true))
return;
if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
return;
if (sta) {
/* Check if aggregation has to be enabled for this tid */
sta_entry = (struct rtl_sta_info *)sta->drv_priv;
if ((sta->ht_cap.ht_supported) &&
!(skb->protocol == cpu_to_be16(ETH_P_PAE))) {
if (ieee80211_is_data_qos(fc)) {
u8 tid = rtl_get_tid(skb);
if (_rtl_tx_aggr_check(rtlpriv, sta_entry,
tid)) {
sta_entry->tids[tid].agg.agg_state =
RTL_AGG_PROGRESS;
ieee80211_start_tx_ba_session(sta, tid,
5000);
}
}
}
}
}
static void rtl_rate_init(void *ppriv,
struct ieee80211_supported_band *sband,
struct cfg80211_chan_def *chandef,
struct ieee80211_sta *sta, void *priv_sta)
{
}
static void *rtl_rate_alloc(struct ieee80211_hw *hw, struct dentry *debugfsdir)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
return rtlpriv;
}
static void rtl_rate_free(void *rtlpriv)
{
}
static void *rtl_rate_alloc_sta(void *ppriv,
struct ieee80211_sta *sta, gfp_t gfp)
{
struct rtl_priv *rtlpriv = ppriv;
struct rtl_rate_priv *rate_priv;
rate_priv = kzalloc(sizeof(*rate_priv), gfp);
if (!rate_priv) {
RT_TRACE(COMP_ERR, DBG_EMERG,
"Unable to allocate private rc structure\n");
return NULL;
}
rtlpriv->rate_priv = rate_priv;
return rate_priv;
}
static void rtl_rate_free_sta(void *rtlpriv,
struct ieee80211_sta *sta, void *priv_sta)
{
struct rtl_rate_priv *rate_priv = priv_sta;
kfree(rate_priv);
}
static struct rate_control_ops rtl_rate_ops = {
.name = "rtl_rc_92e",
.alloc = rtl_rate_alloc,
.free = rtl_rate_free,
.alloc_sta = rtl_rate_alloc_sta,
.free_sta = rtl_rate_free_sta,
.rate_init = rtl_rate_init,
.tx_status = rtl_tx_status,
.get_rate = rtl_get_rate,
};
int rtl92e_rate_control_register(void)
{
return ieee80211_rate_control_register(&rtl_rate_ops);
}
void rtl92e_rate_control_unregister(void)
{
ieee80211_rate_control_unregister(&rtl_rate_ops);
}

47
drivers/staging/rtl8192ee/rc.h
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@ -1,47 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL_RC_H__
#define __RTL_RC_H__
#define B_MODE_MAX_RIX 3
#define G_MODE_MAX_RIX 11
#define A_MODE_MAX_RIX 7
/* in mac80211 mcs0-mcs15 is idx0-idx15*/
#define N_MODE_MCS7_RIX 7
#define N_MODE_MCS15_RIX 15
#define AC_MODE_MCS7_RIX 7
#define AC_MODE_MCS8_RIX 8
#define AC_MODE_MCS9_RIX 9
struct rtl_rate_priv {
u8 ht_cap;
};
int rtl92e_rate_control_register(void);
void rtl92e_rate_control_unregister(void);
#endif

447
drivers/staging/rtl8192ee/regd.c
View File

@ -1,447 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "wifi.h"
#include "regd.h"
static struct country_code_to_enum_rd allcountries[] = {
{COUNTRY_CODE_FCC, "US"},
{COUNTRY_CODE_IC, "US"},
{COUNTRY_CODE_ETSI, "EC"},
{COUNTRY_CODE_SPAIN, "EC"},
{COUNTRY_CODE_FRANCE, "EC"},
{COUNTRY_CODE_MKK, "JP"},
{COUNTRY_CODE_MKK1, "JP"},
{COUNTRY_CODE_ISRAEL, "EC"},
{COUNTRY_CODE_TELEC, "JP"},
{COUNTRY_CODE_MIC, "JP"},
{COUNTRY_CODE_GLOBAL_DOMAIN, "JP"},
{COUNTRY_CODE_WORLD_WIDE_13, "EC"},
{COUNTRY_CODE_TELEC_NETGEAR, "EC"},
};
/*
*Only these channels all allow active
*scan on all world regulatory domains
*/
#define RTL819x_2GHZ_CH01_11 \
REG_RULE(2412-10, 2462+10, 40, 0, 20, 0)
/*
*We enable active scan on these a case
*by case basis by regulatory domain
*/
#define RTL819x_2GHZ_CH12_13 \
REG_RULE(2467-10, 2472+10, 40, 0, 20,\
NL80211_RRF_PASSIVE_SCAN)
#define RTL819x_2GHZ_CH14 \
REG_RULE(2484-10, 2484+10, 40, 0, 20, \
NL80211_RRF_PASSIVE_SCAN | \
NL80211_RRF_NO_OFDM)
/* 5G chan 36 - chan 64*/
#define RTL819x_5GHZ_5150_5350 \
REG_RULE(5150-10, 5350+10, 80, 0, 30, \
NL80211_RRF_PASSIVE_SCAN | \
NL80211_RRF_NO_IBSS)
/* 5G chan 100 - chan 165*/
#define RTL819x_5GHZ_5470_5850 \
REG_RULE(5470-10, 5850+10, 80, 0, 30, \
NL80211_RRF_PASSIVE_SCAN | \
NL80211_RRF_NO_IBSS)
/* 5G chan 149 - chan 165*/
#define RTL819x_5GHZ_5725_5850 \
REG_RULE(5725-10, 5850+10, 80, 0, 30, \
NL80211_RRF_PASSIVE_SCAN | \
NL80211_RRF_NO_IBSS)
#define RTL819x_5GHZ_ALL \
(RTL819x_5GHZ_5150_5350, RTL819x_5GHZ_5470_5850)
static const struct ieee80211_regdomain rtl_regdom_11 = {
.n_reg_rules = 1,
.alpha2 = "99",
.reg_rules = {
RTL819x_2GHZ_CH01_11,
}
};
static const struct ieee80211_regdomain rtl_regdom_12_13 = {
.n_reg_rules = 2,
.alpha2 = "99",
.reg_rules = {
RTL819x_2GHZ_CH01_11,
RTL819x_2GHZ_CH12_13,
}
};
static const struct ieee80211_regdomain rtl_regdom_no_midband = {
.n_reg_rules = 3,
.alpha2 = "99",
.reg_rules = {
RTL819x_2GHZ_CH01_11,
RTL819x_5GHZ_5150_5350,
RTL819x_5GHZ_5725_5850,
}
};
static const struct ieee80211_regdomain rtl_regdom_60_64 = {
.n_reg_rules = 3,
.alpha2 = "99",
.reg_rules = {
RTL819x_2GHZ_CH01_11,
RTL819x_2GHZ_CH12_13,
RTL819x_5GHZ_5725_5850,
}
};
static const struct ieee80211_regdomain rtl_regdom_14_60_64 = {
.n_reg_rules = 4,
.alpha2 = "99",
.reg_rules = {
RTL819x_2GHZ_CH01_11,
RTL819x_2GHZ_CH12_13,
RTL819x_2GHZ_CH14,
RTL819x_5GHZ_5725_5850,
}
};
static const struct ieee80211_regdomain rtl_regdom_14 = {
.n_reg_rules = 3,
.alpha2 = "99",
.reg_rules = {
RTL819x_2GHZ_CH01_11,
RTL819x_2GHZ_CH12_13,
RTL819x_2GHZ_CH14,
}
};
static bool _rtl_is_radar_freq(u16 center_freq)
{
return center_freq >= 5260 && center_freq <= 5700;
}
static void _rtl_reg_apply_beaconing_flags(struct wiphy *wiphy,
enum nl80211_reg_initiator initiator)
{
enum ieee80211_band band;
struct ieee80211_supported_band *sband;
const struct ieee80211_reg_rule *reg_rule;
struct ieee80211_channel *ch;
unsigned int i;
for (band = 0; band < IEEE80211_NUM_BANDS; band++) {
if (!wiphy->bands[band])
continue;
sband = wiphy->bands[band];
for (i = 0; i < sband->n_channels; i++) {
ch = &sband->channels[i];
if (_rtl_is_radar_freq(ch->center_freq) ||
(ch->flags & IEEE80211_CHAN_RADAR))
continue;
if (initiator == NL80211_REGDOM_SET_BY_COUNTRY_IE) {
reg_rule = freq_reg_info(wiphy,
ch->center_freq);
if (IS_ERR(reg_rule))
continue;
/*
*If 11d had a rule for this channel ensure
*we enable adhoc/beaconing if it allows us to
*use it. Note that we would have disabled it
*by applying our static world regdomain by
*default during init, prior to calling our
*regulatory_hint().
*/
if (!(reg_rule->flags & NL80211_RRF_NO_IBSS))
ch->flags &= ~IEEE80211_CHAN_NO_IBSS;
if (!(reg_rule->flags &
NL80211_RRF_PASSIVE_SCAN))
ch->flags &=
~IEEE80211_CHAN_PASSIVE_SCAN;
} else {
if (ch->beacon_found)
ch->flags &= ~(IEEE80211_CHAN_NO_IBSS |
IEEE80211_CHAN_PASSIVE_SCAN);
}
}
}
}
/* Allows active scan scan on Ch 12 and 13 */
static void _rtl_reg_apply_active_scan_flags(struct wiphy *wiphy,
enum nl80211_reg_initiator
initiator)
{
struct ieee80211_supported_band *sband;
struct ieee80211_channel *ch;
const struct ieee80211_reg_rule *reg_rule;
if (!wiphy->bands[IEEE80211_BAND_2GHZ])
return;
sband = wiphy->bands[IEEE80211_BAND_2GHZ];
/*
*If no country IE has been received always enable active scan
*on these channels. This is only done for specific regulatory SKUs
*/
if (initiator != NL80211_REGDOM_SET_BY_COUNTRY_IE) {
ch = &sband->channels[11]; /* CH 12 */
if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
ch = &sband->channels[12]; /* CH 13 */
if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
return;
}
/*
*If a country IE has been recieved check its rule for this
*channel first before enabling active scan. The passive scan
*would have been enforced by the initial processing of our
*custom regulatory domain.
*/
ch = &sband->channels[11]; /* CH 12 */
reg_rule = freq_reg_info(wiphy, ch->center_freq);
if (!IS_ERR(reg_rule)) {
if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
}
ch = &sband->channels[12]; /* CH 13 */
reg_rule = freq_reg_info(wiphy, ch->center_freq);
if (!IS_ERR(reg_rule)) {
if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
}
}
/*
*Always apply Radar/DFS rules on
*freq range 5260 MHz - 5700 MHz
*/
static void _rtl_reg_apply_radar_flags(struct wiphy *wiphy)
{
struct ieee80211_supported_band *sband;
struct ieee80211_channel *ch;
unsigned int i;
if (!wiphy->bands[IEEE80211_BAND_5GHZ])
return;
sband = wiphy->bands[IEEE80211_BAND_5GHZ];
for (i = 0; i < sband->n_channels; i++) {
ch = &sband->channels[i];
if (!_rtl_is_radar_freq(ch->center_freq))
continue;
/*
*We always enable radar detection/DFS on this
*frequency range. Additionally we also apply on
*this frequency range:
*- If STA mode does not yet have DFS supports disable
* active scanning
*- If adhoc mode does not support DFS yet then disable
* adhoc in the frequency.
*- If AP mode does not yet support radar detection/DFS
*do not allow AP mode
*/
if (!(ch->flags & IEEE80211_CHAN_DISABLED))
ch->flags |= IEEE80211_CHAN_RADAR |
IEEE80211_CHAN_NO_IBSS |
IEEE80211_CHAN_PASSIVE_SCAN;
}
}
static void _rtl_reg_apply_world_flags(struct wiphy *wiphy,
enum nl80211_reg_initiator initiator,
struct rtl_regulatory *reg)
{
_rtl_reg_apply_beaconing_flags(wiphy, initiator);
_rtl_reg_apply_active_scan_flags(wiphy, initiator);
}
static void _rtl_dump_channel_map(struct wiphy *wiphy)
{
enum ieee80211_band band;
struct ieee80211_supported_band *sband;
struct ieee80211_channel *ch;
unsigned int i;
for (band = 0; band < IEEE80211_NUM_BANDS; band++) {
if (!wiphy->bands[band])
continue;
sband = wiphy->bands[band];
for (i = 0; i < sband->n_channels; i++)
ch = &sband->channels[i];
}
}
static int _rtl92e_reg_notifier_apply(struct wiphy *wiphy,
struct regulatory_request *request,
struct rtl_regulatory *reg)
{
/* We always apply this */
_rtl_reg_apply_radar_flags(wiphy);
switch (request->initiator) {
case NL80211_REGDOM_SET_BY_DRIVER:
case NL80211_REGDOM_SET_BY_CORE:
case NL80211_REGDOM_SET_BY_USER:
break;
case NL80211_REGDOM_SET_BY_COUNTRY_IE:
_rtl_reg_apply_world_flags(wiphy, request->initiator, reg);
break;
}
_rtl_dump_channel_map(wiphy);
return 0;
}
static const struct ieee80211_regdomain *_rtl_regdomain_select(
struct rtl_regulatory *reg)
{
switch (reg->country_code) {
case COUNTRY_CODE_FCC:
return &rtl_regdom_no_midband;
case COUNTRY_CODE_IC:
return &rtl_regdom_11;
case COUNTRY_CODE_ETSI:
case COUNTRY_CODE_TELEC_NETGEAR:
return &rtl_regdom_60_64;
case COUNTRY_CODE_SPAIN:
case COUNTRY_CODE_FRANCE:
case COUNTRY_CODE_ISRAEL:
case COUNTRY_CODE_WORLD_WIDE_13:
return &rtl_regdom_12_13;
case COUNTRY_CODE_MKK:
case COUNTRY_CODE_MKK1:
case COUNTRY_CODE_TELEC:
case COUNTRY_CODE_MIC:
return &rtl_regdom_14_60_64;
case COUNTRY_CODE_GLOBAL_DOMAIN:
return &rtl_regdom_14;
default:
return &rtl_regdom_no_midband;
}
}
static int
_rtl92e_regd_init_wiphy(struct rtl_regulatory *reg,
struct wiphy *wiphy,
void (*reg_notifier)(struct wiphy *wiphy,
struct regulatory_request *req))
{
const struct ieee80211_regdomain *regd;
wiphy->reg_notifier = reg_notifier;
wiphy->regulatory_flags |= REGULATORY_CUSTOM_REG;
wiphy->regulatory_flags &= ~REGULATORY_STRICT_REG;
wiphy->regulatory_flags &= ~REGULATORY_DISABLE_BEACON_HINTS;
regd = _rtl_regdomain_select(reg);
wiphy_apply_custom_regulatory(wiphy, regd);
_rtl_reg_apply_radar_flags(wiphy);
_rtl_reg_apply_world_flags(wiphy, NL80211_REGDOM_SET_BY_DRIVER, reg);
return 0;
}
static struct country_code_to_enum_rd *_rtl_regd_find_country(u16 countrycode)
{
int i;
for (i = 0; i < ARRAY_SIZE(allcountries); i++) {
if (allcountries[i].countrycode == countrycode)
return &allcountries[i];
}
return NULL;
}
int rtl92e_regd_init(struct ieee80211_hw *hw,
void (*reg_notifier)(struct wiphy *wiphy,
struct regulatory_request *request))
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct wiphy *wiphy = hw->wiphy;
struct country_code_to_enum_rd *country = NULL;
if (wiphy == NULL || &rtlpriv->regd == NULL)
return -EINVAL;
/* init country_code from efuse channel plan */
rtlpriv->regd.country_code = rtlpriv->efuse.channel_plan;
RT_TRACE(COMP_REGD, DBG_TRACE,
KERN_DEBUG "rtl: EEPROM regdomain: 0x%0x\n",
rtlpriv->regd.country_code);
if (rtlpriv->regd.country_code >= COUNTRY_CODE_MAX) {
RT_TRACE(COMP_REGD, DBG_DMESG,
"rtl: EEPROM indicates invalid contry code world wide 13 should be used\n");
rtlpriv->regd.country_code = COUNTRY_CODE_WORLD_WIDE_13;
}
country = _rtl_regd_find_country(rtlpriv->regd.country_code);
if (country) {
rtlpriv->regd.alpha2[0] = country->iso_name[0];
rtlpriv->regd.alpha2[1] = country->iso_name[1];
} else {
rtlpriv->regd.alpha2[0] = '0';
rtlpriv->regd.alpha2[1] = '0';
}
RT_TRACE(COMP_REGD, DBG_TRACE,
KERN_DEBUG "rtl: Country alpha2 being used: %c%c\n",
rtlpriv->regd.alpha2[0], rtlpriv->regd.alpha2[1]);
_rtl92e_regd_init_wiphy(&rtlpriv->regd, wiphy, reg_notifier);
return 0;
}
void rtl92e_reg_notifier(struct wiphy *wiphy,
struct regulatory_request *request)
{
struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
struct rtl_priv *rtlpriv = rtl_priv(hw);
RT_TRACE(COMP_REGD, DBG_LOUD, "\n");
_rtl92e_reg_notifier_apply(wiphy, request, &rtlpriv->regd);
}

63
drivers/staging/rtl8192ee/regd.h
View File

@ -1,63 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL_REGD_H__
#define __RTL_REGD_H__
/* for kernel 3.14 , both value are changed to IEEE80211_CHAN_NO_IR*/
#define IEEE80211_CHAN_NO_IBSS IEEE80211_CHAN_NO_IR
#define IEEE80211_CHAN_PASSIVE_SCAN IEEE80211_CHAN_NO_IR
struct country_code_to_enum_rd {
u16 countrycode;
const char *iso_name;
};
enum country_code_type_t {
COUNTRY_CODE_FCC = 0,
COUNTRY_CODE_IC = 1,
COUNTRY_CODE_ETSI = 2,
COUNTRY_CODE_SPAIN = 3,
COUNTRY_CODE_FRANCE = 4,
COUNTRY_CODE_MKK = 5,
COUNTRY_CODE_MKK1 = 6,
COUNTRY_CODE_ISRAEL = 7,
COUNTRY_CODE_TELEC = 8,
COUNTRY_CODE_MIC = 9,
COUNTRY_CODE_GLOBAL_DOMAIN = 10,
COUNTRY_CODE_WORLD_WIDE_13 = 11,
COUNTRY_CODE_TELEC_NETGEAR = 12,
/*add new channel plan above this line */
COUNTRY_CODE_MAX
};
int rtl92e_regd_init(struct ieee80211_hw *hw,
void (*reg_notifier)(struct wiphy *wiphy,
struct regulatory_request *request));
void rtl92e_reg_notifier(struct wiphy *wiphy,
struct regulatory_request *request);
#endif

106
drivers/staging/rtl8192ee/rtl8192ee/def.h
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@ -1,106 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL92E_DEF_H__
#define __RTL92E_DEF_H__
#define RX_DESC_NUM_92E 512
#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
#define HAL_PRIME_CHNL_OFFSET_LOWER 1
#define HAL_PRIME_CHNL_OFFSET_UPPER 2
#define RX_MPDU_QUEUE 0
#define IS_HT_RATE(_rate) \
(_rate >= DESC92C_RATEMCS0)
#define IS_CCK_RATE(_rate) \
(_rate >= DESC92C_RATE1M && _rate <= DESC92C_RATE11M)
#define IS_OFDM_RATE(_rate) \
(_rate >= DESC92C_RATE6M && _rate <= DESC92C_RATE54M)
enum version_8192e {
VERSION_TEST_CHIP_2T2R_8192E = 0x0024,
VERSION_NORMAL_CHIP_2T2R_8192E = 0x102C,
VERSION_UNKNOWN = 0xFF,
};
enum rx_packet_type {
NORMAL_RX,
TX_REPORT1,
TX_REPORT2,
HIS_REPORT,
C2H_PACKET,
};
enum rtl_desc_qsel {
QSLT_BK = 0x2,
QSLT_BE = 0x0,
QSLT_VI = 0x5,
QSLT_VO = 0x7,
QSLT_BEACON = 0x10,
QSLT_HIGH = 0x11,
QSLT_MGNT = 0x12,
QSLT_CMD = 0x13,
};
enum rtl_desc92c_rate {
DESC92C_RATE1M = 0x00,
DESC92C_RATE2M = 0x01,
DESC92C_RATE5_5M = 0x02,
DESC92C_RATE11M = 0x03,
DESC92C_RATE6M = 0x04,
DESC92C_RATE9M = 0x05,
DESC92C_RATE12M = 0x06,
DESC92C_RATE18M = 0x07,
DESC92C_RATE24M = 0x08,
DESC92C_RATE36M = 0x09,
DESC92C_RATE48M = 0x0a,
DESC92C_RATE54M = 0x0b,
DESC92C_RATEMCS0 = 0x0c,
DESC92C_RATEMCS1 = 0x0d,
DESC92C_RATEMCS2 = 0x0e,
DESC92C_RATEMCS3 = 0x0f,
DESC92C_RATEMCS4 = 0x10,
DESC92C_RATEMCS5 = 0x11,
DESC92C_RATEMCS6 = 0x12,
DESC92C_RATEMCS7 = 0x13,
DESC92C_RATEMCS8 = 0x14,
DESC92C_RATEMCS9 = 0x15,
DESC92C_RATEMCS10 = 0x16,
DESC92C_RATEMCS11 = 0x17,
DESC92C_RATEMCS12 = 0x18,
DESC92C_RATEMCS13 = 0x19,
DESC92C_RATEMCS14 = 0x1a,
DESC92C_RATEMCS15 = 0x1b,
};
#endif

1263
drivers/staging/rtl8192ee/rtl8192ee/dm.c
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343
drivers/staging/rtl8192ee/rtl8192ee/dm.h
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@ -1,343 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL92E_DM_H__
#define __RTL92E_DM_H__
#define OFDMCCA_TH 500
#define BW_IND_BIAS 500
#define MF_USC 2
#define MF_LSC 1
#define MF_USC_LSC 0
#define MONITOR_TIME 30
#define MAIN_ANT 0
#define AUX_ANT 1
#define MAIN_ANT_CG_TRX 1
#define AUX_ANT_CG_TRX 0
#define MAIN_ANT_CGCS_RX 0
#define AUX_ANT_CGCS_RX 1
/*RF REG LIST*/
#define DM_REG_RF_MODE_11N 0x00
#define DM_REG_RF_0B_11N 0x0B
#define DM_REG_CHNBW_11N 0x18
#define DM_REG_T_METER_11N 0x24
#define DM_REG_RF_25_11N 0x25
#define DM_REG_RF_26_11N 0x26
#define DM_REG_RF_27_11N 0x27
#define DM_REG_RF_2B_11N 0x2B
#define DM_REG_RF_2C_11N 0x2C
#define DM_REG_RXRF_A3_11N 0x3C
#define DM_REG_T_METER_92D_11N 0x42
#define DM_REG_T_METER_92E_11N 0x42
/*BB REG LIST*/
/*PAGE 8 */
#define DM_REG_BB_CTRL_11N 0x800
#define DM_REG_RF_PIN_11N 0x804
#define DM_REG_PSD_CTRL_11N 0x808
#define DM_REG_TX_ANT_CTRL_11N 0x80C
#define DM_REG_BB_PWR_SAV5_11N 0x818
#define DM_REG_CCK_RPT_FORMAT_11N 0x824
#define DM_REG_RX_DEFUALT_A_11N 0x858
#define DM_REG_RX_DEFUALT_B_11N 0x85A
#define DM_REG_BB_PWR_SAV3_11N 0x85C
#define DM_REG_ANTSEL_CTRL_11N 0x860
#define DM_REG_RX_ANT_CTRL_11N 0x864
#define DM_REG_PIN_CTRL_11N 0x870
#define DM_REG_BB_PWR_SAV1_11N 0x874
#define DM_REG_ANTSEL_PATH_11N 0x878
#define DM_REG_BB_3WIRE_11N 0x88C
#define DM_REG_SC_CNT_11N 0x8C4
#define DM_REG_PSD_DATA_11N 0x8B4
/*PAGE 9*/
#define DM_REG_ANT_MAPPING1_11N 0x914
#define DM_REG_ANT_MAPPING2_11N 0x918
/*PAGE A*/
#define DM_REG_CCK_ANTDIV_PARA1_11N 0xA00
#define DM_REG_CCK_CCA_11N 0xA0A
#define DM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
#define DM_REG_CCK_ANTDIV_PARA3_11N 0xA10
#define DM_REG_CCK_ANTDIV_PARA4_11N 0xA14
#define DM_REG_CCK_FILTER_PARA1_11N 0xA22
#define DM_REG_CCK_FILTER_PARA2_11N 0xA23
#define DM_REG_CCK_FILTER_PARA3_11N 0xA24
#define DM_REG_CCK_FILTER_PARA4_11N 0xA25
#define DM_REG_CCK_FILTER_PARA5_11N 0xA26
#define DM_REG_CCK_FILTER_PARA6_11N 0xA27
#define DM_REG_CCK_FILTER_PARA7_11N 0xA28
#define DM_REG_CCK_FILTER_PARA8_11N 0xA29
#define DM_REG_CCK_FA_RST_11N 0xA2C
#define DM_REG_CCK_FA_MSB_11N 0xA58
#define DM_REG_CCK_FA_LSB_11N 0xA5C
#define DM_REG_CCK_CCA_CNT_11N 0xA60
#define DM_REG_BB_PWR_SAV4_11N 0xA74
/*PAGE B */
#define DM_REG_LNA_SWITCH_11N 0xB2C
#define DM_REG_PATH_SWITCH_11N 0xB30
#define DM_REG_RSSI_CTRL_11N 0xB38
#define DM_REG_CONFIG_ANTA_11N 0xB68
#define DM_REG_RSSI_BT_11N 0xB9C
/*PAGE C */
#define DM_REG_OFDM_FA_HOLDC_11N 0xC00
#define DM_REG_RX_PATH_11N 0xC04
#define DM_REG_TRMUX_11N 0xC08
#define DM_REG_OFDM_FA_RSTC_11N 0xC0C
#define DM_REG_RXIQI_MATRIX_11N 0xC14
#define DM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
#define DM_REG_IGI_A_11N 0xC50
#define DM_REG_ANTDIV_PARA2_11N 0xC54
#define DM_REG_IGI_B_11N 0xC58
#define DM_REG_ANTDIV_PARA3_11N 0xC5C
#define DM_REG_L1SBD_PD_CH_11N 0XC6C
#define DM_REG_BB_PWR_SAV2_11N 0xC70
#define DM_REG_RX_OFF_11N 0xC7C
#define DM_REG_TXIQK_MATRIXA_11N 0xC80
#define DM_REG_TXIQK_MATRIXB_11N 0xC88
#define DM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
#define DM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
#define DM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
#define DM_REG_ANTDIV_PARA1_11N 0xCA4
#define DM_REG_OFDM_FA_TYPE1_11N 0xCF0
/*PAGE D */
#define DM_REG_OFDM_FA_RSTD_11N 0xD00
#define DM_REG_OFDM_FA_TYPE2_11N 0xDA0
#define DM_REG_OFDM_FA_TYPE3_11N 0xDA4
#define DM_REG_OFDM_FA_TYPE4_11N 0xDA8
/*PAGE E */
#define DM_REG_TXAGC_A_6_18_11N 0xE00
#define DM_REG_TXAGC_A_24_54_11N 0xE04
#define DM_REG_TXAGC_A_1_MCS32_11N 0xE08
#define DM_REG_TXAGC_A_MCS0_3_11N 0xE10
#define DM_REG_TXAGC_A_MCS4_7_11N 0xE14
#define DM_REG_TXAGC_A_MCS8_11_11N 0xE18
#define DM_REG_TXAGC_A_MCS12_15_11N 0xE1C
#define DM_REG_FPGA0_IQK_11N 0xE28
#define DM_REG_TXIQK_TONE_A_11N 0xE30
#define DM_REG_RXIQK_TONE_A_11N 0xE34
#define DM_REG_TXIQK_PI_A_11N 0xE38
#define DM_REG_RXIQK_PI_A_11N 0xE3C
#define DM_REG_TXIQK_11N 0xE40
#define DM_REG_RXIQK_11N 0xE44
#define DM_REG_IQK_AGC_PTS_11N 0xE48
#define DM_REG_IQK_AGC_RSP_11N 0xE4C
#define DM_REG_BLUETOOTH_11N 0xE6C
#define DM_REG_RX_WAIT_CCA_11N 0xE70
#define DM_REG_TX_CCK_RFON_11N 0xE74
#define DM_REG_TX_CCK_BBON_11N 0xE78
#define DM_REG_OFDM_RFON_11N 0xE7C
#define DM_REG_OFDM_BBON_11N 0xE80
#define DM_REG_TX2RX_11N 0xE84
#define DM_REG_TX2TX_11N 0xE88
#define DM_REG_RX_CCK_11N 0xE8C
#define DM_REG_RX_OFDM_11N 0xED0
#define DM_REG_RX_WAIT_RIFS_11N 0xED4
#define DM_REG_RX2RX_11N 0xED8
#define DM_REG_STANDBY_11N 0xEDC
#define DM_REG_SLEEP_11N 0xEE0
#define DM_REG_PMPD_ANAEN_11N 0xEEC
/*MAC REG LIST*/
#define DM_REG_BB_RST_11N 0x02
#define DM_REG_ANTSEL_PIN_11N 0x4C
#define DM_REG_EARLY_MODE_11N 0x4D0
#define DM_REG_RSSI_MONITOR_11N 0x4FE
#define DM_REG_EDCA_VO_11N 0x500
#define DM_REG_EDCA_VI_11N 0x504
#define DM_REG_EDCA_BE_11N 0x508
#define DM_REG_EDCA_BK_11N 0x50C
#define DM_REG_TXPAUSE_11N 0x522
#define DM_REG_RESP_TX_11N 0x6D8
#define DM_REG_ANT_TRAIN_PARA1_11N 0x7b0
#define DM_REG_ANT_TRAIN_PARA2_11N 0x7b4
/*DIG Related*/
#define DM_BIT_IGI_11N 0x0000007F
#define HAL_DM_DIG_DISABLE BIT(0)
#define HAL_DM_HIPWR_DISABLE BIT(1)
#define OFDM_TABLE_LENGTH 43
#define CCK_TABLE_LENGTH 33
#define OFDM_TABLE_SIZE 43
#define CCK_TABLE_SIZE 33
#define BW_AUTO_SWITCH_HIGH_LOW 25
#define BW_AUTO_SWITCH_LOW_HIGH 30
#define DM_DIG_THRESH_HIGH 40
#define DM_DIG_THRESH_LOW 35
#define DM_FALSEALARM_THRESH_LOW 400
#define DM_FALSEALARM_THRESH_HIGH 1000
#define DM_DIG_MAX 0x3e
#define DM_DIG_MIN 0x1e
#define DM_DIG_MAX_AP 0x32
#define DM_DIG_MIN_AP 0x20
#define DM_DIG_FA_UPPER 0x3e
#define DM_DIG_FA_LOWER 0x1e
#define DM_DIG_FA_TH0 0x200
#define DM_DIG_FA_TH1 0x300
#define DM_DIG_FA_TH2 0x400
#define DM_DIG_BACKOFF_MAX 12
#define DM_DIG_BACKOFF_MIN -4
#define DM_DIG_BACKOFF_DEFAULT 10
#define RXPATHSELECTION_SS_TH_lOW 30
#define RXPATHSELECTION_DIFF_TH 18
#define DM_RATR_STA_INIT 0
#define DM_RATR_STA_HIGH 1
#define DM_RATR_STA_MIDDLE 2
#define DM_RATR_STA_LOW 3
#define CTS2SELF_THVAL 30
#define REGC38_TH 20
#define WAIOTTHVal 25
#define TXHIGHPWRLEVEL_NORMAL 0
#define TXHIGHPWRLEVEL_LEVEL1 1
#define TXHIGHPWRLEVEL_LEVEL2 2
#define TXHIGHPWRLEVEL_BT1 3
#define TXHIGHPWRLEVEL_BT2 4
#define DM_TYPE_BYFW 0
#define DM_TYPE_BYDRIVER 1
#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
#define TXPWRTRACK_MAX_IDX 6
/* Dynamic ATC switch */
#define ATC_STATUS_OFF 0x0 /* enable */
#define ATC_STATUS_ON 0x1 /* disable */
#define CFO_THRESHOLD_XTAL 10 /* kHz */
#define CFO_THRESHOLD_ATC 80 /* kHz */
/* RSSI Dump Message */
#define RA_RSSIDUMP 0xcb0
#define RB_RSSIDUMP 0xcb1
#define RS1_RXEVMDUMP 0xcb2
#define RS2_RXEVMDUMP 0xcb3
#define RA_RXSNRDUMP 0xcb4
#define RB_RXSNRDUMP 0xcb5
#define RA_CFOSHORTDUMP 0xcb6
#define RB_CFOSHORTDUMP 0xcb8
#define RA_CFOLONGDUMP 0xcba
#define RB_CFOLONGDUMP 0xcbc
struct ps_t {
u8 pre_ccastate;
u8 cur_ccasate;
u8 pre_rfstate;
u8 cur_rfstate;
long rssi_val_min;
};
struct dig_t {
u8 dig_enable_flag;
u8 dig_ext_port_stage;
u32 rssi_lowthresh;
u32 rssi_highthresh;
u32 fa_lowthresh;
u32 fa_highthresh;
u8 cursta_connectctate;
u8 presta_connectstate;
u8 curmultista_connectstate;
u8 pre_igvalue;
u8 cur_igvalue;
u8 backup_igvalue;
u8 bt30_cur_igi;
u8 stop_dig;
char backoff_val;
char backoff_val_range_max;
char backoff_val_range_min;
u8 rx_gain_range_max;
u8 rx_gain_range_min;
u8 rssi_val_min;
u8 pre_cck_cca_thres;
u8 cur_cck_cca_thres;
u8 pre_cck_pd_state;
u8 cur_cck_pd_state;
u8 large_fa_hit;
u8 forbidden_igi;
u32 recover_cnt;
char th_l2h_ini;
char th_edcca_hl_diff;
char igi_base;
u8 igi_target;
bool force_edcca;
u8 adapen_rssi;
u8 dig_dynamic_min_0;
u8 dig_dynamic_min_1;
bool b_media_connect_0;
bool b_media_connect_1;
u32 antdiv_rssi_max;
u32 rssi_max;
};
enum pwr_track_control_method {
BBSWING,
TXAGC
};
extern struct dig_t dm_dig;
void rtl92ee_dm_init(struct ieee80211_hw *hw);
void rtl92ee_dm_watchdog(struct ieee80211_hw *hw);
void rtl92ee_dm_write_cck_cca_thres(struct ieee80211_hw *hw,
u8 cur_thres);
void rtl92ee_dm_write_dig(struct ieee80211_hw *hw, u8 current_igi);
void rtl92ee_dm_init_edca_turbo(struct ieee80211_hw *hw);
void rtl92ee_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
void rtl92ee_dm_dynamic_arfb_select(struct ieee80211_hw *hw,
u8 rate, bool collision_state);
#endif

939
drivers/staging/rtl8192ee/rtl8192ee/fw.c
View File

@ -1,939 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../wifi.h"
#include "../pci.h"
#include "../base.h"
#include "reg.h"
#include "def.h"
#include "fw.h"
#include "dm.h"
static void _rtl92ee_enable_fw_download(struct ieee80211_hw *hw, bool enable)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u8 tmp;
if (enable) {
rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x05);
tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL + 2);
rtl_write_byte(rtlpriv, REG_MCUFWDL + 2, tmp & 0xf7);
} else {
tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp & 0xfe);
}
}
static void _rtl92ee_fw_block_write(struct ieee80211_hw *hw,
const u8 *buffer, u32 size)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 blockSize = sizeof(u32);
u8 *bufferPtr = (u8 *) buffer;
u32 *pu4BytePtr = (u32 *) buffer;
u32 i, offset, blockCount, remainSize;
blockCount = size / blockSize;
remainSize = size % blockSize;
for (i = 0; i < blockCount; i++) {
offset = i * blockSize;
rtl_write_dword(rtlpriv, (FW_8192C_START_ADDRESS + offset),
*(pu4BytePtr + i));
}
if (remainSize) {
offset = blockCount * blockSize;
bufferPtr += offset;
for (i = 0; i < remainSize; i++) {
rtl_write_byte(rtlpriv,
(FW_8192C_START_ADDRESS + offset + i),
*(bufferPtr + i));
}
}
}
static void _rtl92ee_fw_page_write(struct ieee80211_hw *hw, u32 page,
const u8 *buffer, u32 size)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u8 value8;
u8 u8page = (u8) (page & 0x07);
value8 = (rtl_read_byte(rtlpriv, REG_MCUFWDL + 2) & 0xF8) | u8page;
rtl_write_byte(rtlpriv, (REG_MCUFWDL + 2), value8);
_rtl92ee_fw_block_write(hw, buffer, size);
}
static void _rtl92ee_fill_dummy(u8 *pfwbuf, u32 *pfwlen)
{
u32 fwlen = *pfwlen;
u8 remain = (u8) (fwlen % 4);
remain = (remain == 0) ? 0 : (4 - remain);
while (remain > 0) {
pfwbuf[fwlen] = 0;
fwlen++;
remain--;
}
*pfwlen = fwlen;
}
static void _rtl92ee_write_fw(struct ieee80211_hw *hw,
enum version_8192e version,
u8 *buffer, u32 size)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u8 *bufferPtr = (u8 *) buffer;
u32 pageNums, remainSize;
u32 page, offset;
RT_TRACE(COMP_FW, DBG_LOUD , "FW size is %d bytes\n", size);
_rtl92ee_fill_dummy(bufferPtr, &size);
pageNums = size / FW_8192C_PAGE_SIZE;
remainSize = size % FW_8192C_PAGE_SIZE;
if (pageNums > 8) {
RT_TRACE(COMP_ERR, DBG_EMERG,
"Page numbers should not greater then 8\n");
}
for (page = 0; page < pageNums; page++) {
offset = page * FW_8192C_PAGE_SIZE;
_rtl92ee_fw_page_write(hw, page, (bufferPtr + offset),
FW_8192C_PAGE_SIZE);
udelay(2);
}
if (remainSize) {
offset = pageNums * FW_8192C_PAGE_SIZE;
page = pageNums;
_rtl92ee_fw_page_write(hw, page, (bufferPtr + offset),
remainSize);
}
}
static int _rtl92ee_fw_free_to_go(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
int err = -EIO;
u32 counter = 0;
u32 value32;
do {
value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
} while ((counter++ < FW_8192C_POLLING_TIMEOUT_COUNT) &&
(!(value32 & FWDL_ChkSum_rpt)));
if (counter >= FW_8192C_POLLING_TIMEOUT_COUNT) {
RT_TRACE(COMP_ERR, DBG_EMERG,
"chksum report faill ! REG_MCUFWDL:0x%08x\n",
value32);
goto exit;
}
RT_TRACE(COMP_FW, DBG_TRACE,
"Checksum report OK ! REG_MCUFWDL:0x%08x\n", value32);
value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
value32 |= MCUFWDL_RDY;
value32 &= ~WINTINI_RDY;
rtl_write_dword(rtlpriv, REG_MCUFWDL, value32);
rtl92ee_firmware_selfreset(hw);
counter = 0;
do {
value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
if (value32 & WINTINI_RDY) {
RT_TRACE(COMP_FW, DBG_LOUD,
"Polling FW ready success!! REG_MCUFWDL:0x%08x. count = %d\n",
value32, counter);
err = 0;
goto exit;
}
udelay(FW_8192C_POLLING_DELAY*10);
} while (counter++ < FW_8192C_POLLING_TIMEOUT_COUNT);
RT_TRACE(COMP_ERR, DBG_EMERG,
"Polling FW ready fail!! REG_MCUFWDL:0x%08x. count = %d\n",
value32, counter);
exit:
return err;
}
int rtl92ee_download_fw(struct ieee80211_hw *hw, bool buse_wake_on_wlan_fw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
struct rtl92c_firmware_header *pfwheader;
u8 *pfwdata;
u32 fwsize;
int err;
enum version_8192e version = rtlhal->version;
if (!rtlhal->pfirmware)
return 1;
pfwheader = (struct rtl92c_firmware_header *)rtlhal->pfirmware;
rtlhal->fw_version = pfwheader->version;
rtlhal->fw_subversion = pfwheader->subversion;
pfwdata = (u8 *) rtlhal->pfirmware;
fwsize = rtlhal->fwsize;
RT_TRACE(COMP_FW, DBG_DMESG, "normal Firmware SIZE %d\n", fwsize);
if (IS_FW_HEADER_EXIST(pfwheader)) {
RT_TRACE(COMP_FW, DBG_DMESG,
"Firmware Version(%d), Signature(%#x), Size(%d)\n",
pfwheader->version, pfwheader->signature,
(int)sizeof(struct rtl92c_firmware_header));
pfwdata = pfwdata + sizeof(struct rtl92c_firmware_header);
fwsize = fwsize - sizeof(struct rtl92c_firmware_header);
} else {
RT_TRACE(COMP_FW, DBG_DMESG,
"Firmware no Header, Signature(%#x)\n",
pfwheader->signature);
}
if (rtlhal->b_mac_func_enable) {
if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) {
rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
rtl92ee_firmware_selfreset(hw);
}
}
_rtl92ee_enable_fw_download(hw, true);
_rtl92ee_write_fw(hw, version, pfwdata, fwsize);
_rtl92ee_enable_fw_download(hw, false);
err = _rtl92ee_fw_free_to_go(hw);
if (err) {
RT_TRACE(COMP_ERR, DBG_EMERG,
"Firmware is not ready to run!\n");
} else {
RT_TRACE(COMP_FW, DBG_LOUD, "Firmware is ready to run!\n");
}
return 0;
}
static bool _rtl92ee_check_fw_read_last_h2c(struct ieee80211_hw *hw, u8 boxnum)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u8 val_hmetfr;
bool result = false;
val_hmetfr = rtl_read_byte(rtlpriv, REG_HMETFR);
if (((val_hmetfr >> boxnum) & BIT(0)) == 0)
result = true;
return result;
}
static void _rtl92ee_fill_h2c_command(struct ieee80211_hw *hw, u8 element_id,
u32 cmd_len, u8 *p_cmdbuffer)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
u8 boxnum;
u16 box_reg = 0, box_extreg = 0;
u8 u1b_tmp;
bool isfw_read = false;
u8 buf_index = 0;
bool bwrite_sucess = false;
u8 wait_h2c_limmit = 100;
u8 boxcontent[4], boxextcontent[4];
u32 h2c_waitcounter = 0;
unsigned long flag;
u8 idx;
if (ppsc->dot11_psmode != EACTIVE ||
ppsc->inactive_pwrstate == ERFOFF) {
RT_TRACE(COMP_CMD, DBG_LOUD,
"FillH2CCommand8192E(): Return because RF is off!!!\n");
return;
}
RT_TRACE(COMP_CMD, DBG_LOUD, "come in\n");
/* 1. Prevent race condition in setting H2C cmd.
* (copy from MgntActSet_RF_State().)
*/
while (true) {
spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
if (rtlhal->b_h2c_setinprogress) {
RT_TRACE(COMP_CMD, DBG_LOUD ,
"H2C set in progress! Wait to set..element_id(%d)\n",
element_id);
while (rtlhal->b_h2c_setinprogress) {
spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock,
flag);
h2c_waitcounter++;
RT_TRACE(COMP_CMD, DBG_LOUD,
"Wait 100 us (%d times)...\n",
h2c_waitcounter);
udelay(100);
if (h2c_waitcounter > 1000)
return;
spin_lock_irqsave(&rtlpriv->locks.h2c_lock,
flag);
}
spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
} else {
rtlhal->b_h2c_setinprogress = true;
spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
break;
}
}
while (!bwrite_sucess) {
/* cosa remove this because never reach this. */
/*wait_writeh2c_limmit--;
if (wait_writeh2c_limmit == 0) {
RT_TRACE(COMP_ERR, DBG_EMERG,
"Write H2C fail because no trigger for FW INT!\n");
break;
}
*/
/* 2. Find the last BOX number which has been writen. */
boxnum = rtlhal->last_hmeboxnum;
switch (boxnum) {
case 0:
box_reg = REG_HMEBOX_0;
box_extreg = REG_HMEBOX_EXT_0;
break;
case 1:
box_reg = REG_HMEBOX_1;
box_extreg = REG_HMEBOX_EXT_1;
break;
case 2:
box_reg = REG_HMEBOX_2;
box_extreg = REG_HMEBOX_EXT_2;
break;
case 3:
box_reg = REG_HMEBOX_3;
box_extreg = REG_HMEBOX_EXT_3;
break;
default:
RT_TRACE(COMP_ERR, DBG_EMERG,
"switch case not processed\n");
break;
}
/* 3. Check if the box content is empty. */
isfw_read = false;
u1b_tmp = rtl_read_byte(rtlpriv, REG_CR);
if (u1b_tmp != 0xea) {
isfw_read = true;
} else {
if (rtl_read_byte(rtlpriv, REG_TXDMA_STATUS) == 0xea ||
rtl_read_byte(rtlpriv, REG_TXPKT_EMPTY) == 0xea)
rtl_write_byte(rtlpriv, REG_SYS_CFG1 + 3, 0xff);
}
if (isfw_read == true) {
wait_h2c_limmit = 100;
isfw_read = _rtl92ee_check_fw_read_last_h2c(hw, boxnum);
while (!isfw_read) {
wait_h2c_limmit--;
if (wait_h2c_limmit == 0) {
RT_TRACE(COMP_CMD, DBG_LOUD,
"Wating too long for FW read clear HMEBox(%d)!!!\n",
boxnum);
break;
}
udelay(10);
isfw_read = _rtl92ee_check_fw_read_last_h2c(hw,
boxnum);
u1b_tmp = rtl_read_byte(rtlpriv, 0x130);
RT_TRACE(COMP_CMD, DBG_LOUD,
"Waiting for FW read clear HMEBox(%d)!!! 0x130 = %2x\n",
boxnum, u1b_tmp);
}
}
/* If Fw has not read the last
H2C cmd, break and give up this H2C. */
if (!isfw_read) {
RT_TRACE(COMP_CMD, DBG_LOUD ,
"Write H2C reg BOX[%d] fail, Fw doesn't read\n",
boxnum);
break;
}
/* 4. Fill the H2C cmd into box */
memset(boxcontent, 0, sizeof(boxcontent));
memset(boxextcontent, 0, sizeof(boxextcontent));
boxcontent[0] = element_id;
RT_TRACE(COMP_CMD, DBG_LOUD,
"Write element_id box_reg(%4x) = %2x\n",
box_reg, element_id);
switch (cmd_len) {
case 1:
case 2:
case 3:
/*boxcontent[0] &= ~(BIT(7));*/
memcpy((u8 *) (boxcontent) + 1,
p_cmdbuffer + buf_index, cmd_len);
for (idx = 0; idx < 4; idx++) {
rtl_write_byte(rtlpriv, box_reg + idx,
boxcontent[idx]);
}
break;
case 4:
case 5:
case 6:
case 7:
/*boxcontent[0] |= (BIT(7));*/
memcpy((u8 *) (boxextcontent),
p_cmdbuffer + buf_index+3, cmd_len-3);
memcpy((u8 *) (boxcontent) + 1,
p_cmdbuffer + buf_index, 3);
for (idx = 0; idx < 4; idx++) {
rtl_write_byte(rtlpriv, box_extreg + idx,
boxextcontent[idx]);
}
for (idx = 0; idx < 4; idx++) {
rtl_write_byte(rtlpriv, box_reg + idx,
boxcontent[idx]);
}
break;
default:
RT_TRACE(COMP_ERR, DBG_EMERG,
"switch case not processed\n");
break;
}
bwrite_sucess = true;
rtlhal->last_hmeboxnum = boxnum + 1;
if (rtlhal->last_hmeboxnum == 4)
rtlhal->last_hmeboxnum = 0;
RT_TRACE(COMP_CMD, DBG_LOUD, "pHalData->last_hmeboxnum = %d\n",
rtlhal->last_hmeboxnum);
}
spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
rtlhal->b_h2c_setinprogress = false;
spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
RT_TRACE(COMP_CMD, DBG_LOUD, "go out\n");
}
void rtl92ee_fill_h2c_cmd(struct ieee80211_hw *hw,
u8 element_id, u32 cmd_len, u8 *p_cmdbuffer)
{
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
u32 tmp_cmdbuf[2];
if (rtlhal->bfw_ready == false) {
RT_ASSERT(false, ("return H2C cmd because of Fw "
"download fail!!!\n"));
return;
}
memset(tmp_cmdbuf, 0, 8);
memcpy(tmp_cmdbuf, p_cmdbuffer, cmd_len);
_rtl92ee_fill_h2c_command(hw, element_id, cmd_len, (u8 *)&tmp_cmdbuf);
return;
}
void rtl92ee_firmware_selfreset(struct ieee80211_hw *hw)
{
u8 u1b_tmp;
struct rtl_priv *rtlpriv = rtl_priv(hw);
u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
udelay(50);
u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp | BIT(0)));
u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp | BIT(2)));
RT_TRACE(COMP_INIT, DBG_LOUD,
" _8051Reset92E(): 8051 reset success\n");
}
void rtl92ee_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u8 u1_h2c_set_pwrmode[H2C_92E_PWEMODE_LENGTH] = { 0 };
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
u8 rlbm , power_state = 0;
RT_TRACE(COMP_POWER, DBG_LOUD, "FW LPS mode = %d\n", mode);
SET_H2CCMD_PWRMODE_PARM_MODE(u1_h2c_set_pwrmode, ((mode) ? 1 : 0));
rlbm = 0;/*YJ, temp, 120316. FW now not support RLBM = 2.*/
SET_H2CCMD_PWRMODE_PARM_RLBM(u1_h2c_set_pwrmode, rlbm);
SET_H2CCMD_PWRMODE_PARM_SMART_PS(u1_h2c_set_pwrmode,
(rtlpriv->mac80211.p2p) ?
ppsc->smart_ps : 1);
SET_H2CCMD_PWRMODE_PARM_AWAKE_INTERVAL(u1_h2c_set_pwrmode,
ppsc->reg_max_lps_awakeintvl);
SET_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(u1_h2c_set_pwrmode, 0);
if (mode == FW_PS_ACTIVE_MODE)
power_state |= FW_PWR_STATE_ACTIVE;
else
power_state |= FW_PWR_STATE_RF_OFF;
SET_H2CCMD_PWRMODE_PARM_PWR_STATE(u1_h2c_set_pwrmode, power_state);
RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
"rtl92c_set_fw_pwrmode(): u1_h2c_set_pwrmode\n",
u1_h2c_set_pwrmode, H2C_92E_PWEMODE_LENGTH);
rtl92ee_fill_h2c_cmd(hw, H2C_92E_SETPWRMODE, H2C_92E_PWEMODE_LENGTH,
u1_h2c_set_pwrmode);
}
void rtl92ee_set_fw_media_status_rpt_cmd(struct ieee80211_hw *hw, u8 mstatus)
{
u8 parm[3] = { 0 , 0 , 0 };
/* parm[0]: bit0 = 0-->Disconnect, bit0 = 1-->Connect
* bit1 = 0-->update Media Status to MACID
* bit1 = 1-->update Media Status from MACID to MACID_End
* parm[1]: MACID, if this is INFRA_STA, MacID = 0
* parm[2]: MACID_End*/
SET_H2CCMD_MSRRPT_PARM_OPMODE(parm, mstatus);
SET_H2CCMD_MSRRPT_PARM_MACID_IND(parm, 0);
rtl92ee_fill_h2c_cmd(hw, H2C_92E_MSRRPT, 3, parm);
}
static bool _rtl92ee_cmd_send_packet(struct ieee80211_hw *hw,
struct sk_buff *skb)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
struct rtl8192_tx_ring *ring;
struct rtl_tx_desc *pdesc;
unsigned long flags;
struct sk_buff *pskb = NULL;
ring = &rtlpci->tx_ring[BEACON_QUEUE];
pskb = __skb_dequeue(&ring->queue);
if (pskb)
kfree_skb(pskb);
spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
/*this is wrong, fill_tx_cmddesc needs update*/
pdesc = &ring->desc[0];
rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *) pdesc, 1, 1, skb);
__skb_queue_tail(&ring->queue, skb);
spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
return true;
}
#define BEACON_PG 0 /* ->1 */
#define PSPOLL_PG 2
#define NULL_PG 3
#define PROBERSP_PG 4 /* ->5 */
#define TOTAL_RESERVED_PKT_LEN 768
static u8 reserved_page_packet[TOTAL_RESERVED_PKT_LEN] = {
/* page 0 beacon */
0x80, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0x00, 0xE0, 0x4C, 0x02, 0xB1, 0x78,
0xEC, 0x1A, 0x59, 0x0B, 0xAD, 0xD4, 0x20, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x64, 0x00, 0x10, 0x04, 0x00, 0x05, 0x54, 0x65,
0x73, 0x74, 0x32, 0x01, 0x08, 0x82, 0x84, 0x0B,
0x16, 0x24, 0x30, 0x48, 0x6C, 0x03, 0x01, 0x06,
0x06, 0x02, 0x00, 0x00, 0x2A, 0x01, 0x02, 0x32,
0x04, 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C,
0x09, 0x03, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x3D, 0x00, 0xDD, 0x07, 0x00, 0xE0, 0x4C,
0x02, 0x02, 0x00, 0x00, 0xDD, 0x18, 0x00, 0x50,
0xF2, 0x01, 0x01, 0x00, 0x00, 0x50, 0xF2, 0x04,
0x01, 0x00, 0x00, 0x50, 0xF2, 0x04, 0x01, 0x00,
/* page 1 beacon */
0x00, 0x50, 0xF2, 0x02, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x10, 0x00, 0x28, 0x8C, 0x00, 0x12, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* page 2 ps-poll */
0xA4, 0x10, 0x01, 0xC0, 0xEC, 0x1A, 0x59, 0x0B,
0xAD, 0xD4, 0x00, 0xE0, 0x4C, 0x02, 0xB1, 0x78,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x18, 0x00, 0x28, 0x8C, 0x00, 0x12, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* page 3 null */
0x48, 0x01, 0x00, 0x00, 0xEC, 0x1A, 0x59, 0x0B,
0xAD, 0xD4, 0x00, 0xE0, 0x4C, 0x02, 0xB1, 0x78,
0xEC, 0x1A, 0x59, 0x0B, 0xAD, 0xD4, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x72, 0x00, 0x28, 0x8C, 0x00, 0x12, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* page 4 probe_resp */
0x50, 0x00, 0x00, 0x00, 0x00, 0x40, 0x10, 0x10,
0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x00, 0x00,
0x9E, 0x46, 0x15, 0x32, 0x27, 0xF2, 0x2D, 0x00,
0x64, 0x00, 0x00, 0x04, 0x00, 0x0C, 0x6C, 0x69,
0x6E, 0x6B, 0x73, 0x79, 0x73, 0x5F, 0x77, 0x6C,
0x61, 0x6E, 0x01, 0x04, 0x82, 0x84, 0x8B, 0x96,
0x03, 0x01, 0x01, 0x06, 0x02, 0x00, 0x00, 0x2A,
0x01, 0x00, 0x32, 0x08, 0x24, 0x30, 0x48, 0x6C,
0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C, 0x18,
0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x3D, 0x00, 0xDD, 0x06, 0x00, 0xE0, 0x4C, 0x02,
0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* page 5 probe_resp */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};
void rtl92ee_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
struct sk_buff *skb = NULL;
u32 totalpacketlen;
bool rtstatus;
u8 u1RsvdPageLoc[5] = { 0 };
bool b_dlok = false;
u8 *beacon;
u8 *p_pspoll;
u8 *nullfunc;
u8 *p_probersp;
/*---------------------------------------------------------
(1) beacon
---------------------------------------------------------*/
beacon = &reserved_page_packet[BEACON_PG * 128];
SET_80211_HDR_ADDRESS2(beacon, mac->mac_addr);
SET_80211_HDR_ADDRESS3(beacon, mac->bssid);
/*-------------------------------------------------------
(2) ps-poll
--------------------------------------------------------*/
p_pspoll = &reserved_page_packet[PSPOLL_PG * 128];
SET_80211_PS_POLL_AID(p_pspoll, (mac->assoc_id | 0xc000));
SET_80211_PS_POLL_BSSID(p_pspoll, mac->bssid);
SET_80211_PS_POLL_TA(p_pspoll, mac->mac_addr);
SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1RsvdPageLoc, PSPOLL_PG);
/*--------------------------------------------------------
(3) null data
---------------------------------------------------------*/
nullfunc = &reserved_page_packet[NULL_PG * 128];
SET_80211_HDR_ADDRESS1(nullfunc, mac->bssid);
SET_80211_HDR_ADDRESS2(nullfunc, mac->mac_addr);
SET_80211_HDR_ADDRESS3(nullfunc, mac->bssid);
SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1RsvdPageLoc, NULL_PG);
/*---------------------------------------------------------
(4) probe response
----------------------------------------------------------*/
p_probersp = &reserved_page_packet[PROBERSP_PG * 128];
SET_80211_HDR_ADDRESS1(p_probersp, mac->bssid);
SET_80211_HDR_ADDRESS2(p_probersp, mac->mac_addr);
SET_80211_HDR_ADDRESS3(p_probersp, mac->bssid);
SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1RsvdPageLoc, PROBERSP_PG);
totalpacketlen = TOTAL_RESERVED_PKT_LEN;
RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD ,
"rtl92ee_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
&reserved_page_packet[0], totalpacketlen);
RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD ,
"rtl92ee_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
u1RsvdPageLoc, 3);
skb = dev_alloc_skb(totalpacketlen);
memcpy((u8 *) skb_put(skb, totalpacketlen),
&reserved_page_packet, totalpacketlen);
rtstatus = _rtl92ee_cmd_send_packet(hw, skb);
if (rtstatus)
b_dlok = true;
if (b_dlok) {
RT_TRACE(COMP_POWER, DBG_LOUD,
"Set RSVD page location to Fw\n");
RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD ,
"H2C_RSVDPAGE:\n", u1RsvdPageLoc, 3);
rtl92ee_fill_h2c_cmd(hw, H2C_92E_RSVDPAGE,
sizeof(u1RsvdPageLoc), u1RsvdPageLoc);
} else
RT_TRACE(COMP_ERR, DBG_WARNING,
"Set RSVD page location to Fw FAIL!!!!!!\n");
}
/*Shoud check FW support p2p or not.*/
static void rtl92ee_set_p2p_ctw_period_cmd(struct ieee80211_hw *hw, u8 ctwindow)
{
u8 u1_ctwindow_period[1] = {ctwindow};
rtl92ee_fill_h2c_cmd(hw, H2C_92E_P2P_PS_CTW_CMD, 1, u1_ctwindow_period);
}
void rtl92ee_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_ps_ctl *rtlps = rtl_psc(rtl_priv(hw));
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
struct rtl_p2p_ps_info *p2pinfo = &(rtlps->p2p_ps_info);
struct p2p_ps_offload_t *p2p_ps_offload = &rtlhal->p2p_ps_offload;
u8 i;
u16 ctwindow;
u32 start_time, tsf_low;
switch (p2p_ps_state) {
case P2P_PS_DISABLE:
RT_TRACE(COMP_FW, DBG_LOUD, "P2P_PS_DISABLE\n");
memset(p2p_ps_offload, 0, 1);
break;
case P2P_PS_ENABLE:
RT_TRACE(COMP_FW, DBG_LOUD, "P2P_PS_ENABLE\n");
/* update CTWindow value. */
if (p2pinfo->ctwindow > 0) {
p2p_ps_offload->CTWindow_En = 1;
ctwindow = p2pinfo->ctwindow;
rtl92ee_set_p2p_ctw_period_cmd(hw, ctwindow);
}
/* hw only support 2 set of NoA */
for (i = 0 ; i < p2pinfo->noa_num ; i++) {
/* To control the register setting for which NOA*/
rtl_write_byte(rtlpriv, 0x5cf, (i << 4));
if (i == 0)
p2p_ps_offload->NoA0_En = 1;
else
p2p_ps_offload->NoA1_En = 1;
/* config P2P NoA Descriptor Register */
rtl_write_dword(rtlpriv, 0x5E0,
p2pinfo->noa_duration[i]);
rtl_write_dword(rtlpriv, 0x5E4,
p2pinfo->noa_interval[i]);
/*Get Current TSF value */
tsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
start_time = p2pinfo->noa_start_time[i];
if (p2pinfo->noa_count_type[i] != 1) {
while (start_time <= (tsf_low + (50 * 1024))) {
start_time += p2pinfo->noa_interval[i];
if (p2pinfo->noa_count_type[i] != 255)
p2pinfo->noa_count_type[i]--;
}
}
rtl_write_dword(rtlpriv, 0x5E8, start_time);
rtl_write_dword(rtlpriv, 0x5EC,
p2pinfo->noa_count_type[i]);
}
if ((p2pinfo->opp_ps == 1) || (p2pinfo->noa_num > 0)) {
/* rst p2p circuit */
rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, BIT(4));
p2p_ps_offload->Offload_En = 1;
if (P2P_ROLE_GO == rtlpriv->mac80211.p2p) {
p2p_ps_offload->role = 1;
p2p_ps_offload->AllStaSleep = 0;
} else {
p2p_ps_offload->role = 0;
}
p2p_ps_offload->discovery = 0;
}
break;
case P2P_PS_SCAN:
RT_TRACE(COMP_FW, DBG_LOUD, "P2P_PS_SCAN\n");
p2p_ps_offload->discovery = 1;
break;
case P2P_PS_SCAN_DONE:
RT_TRACE(COMP_FW, DBG_LOUD, "P2P_PS_SCAN_DONE\n");
p2p_ps_offload->discovery = 0;
p2pinfo->p2p_ps_state = P2P_PS_ENABLE;
break;
default:
break;
}
rtl92ee_fill_h2c_cmd(hw, H2C_92E_P2P_PS_OFFLOAD, 1,
(u8 *)p2p_ps_offload);
}
static void _rtl92ee_c2h_ra_report_handler(struct ieee80211_hw *hw,
u8 *cmd_buf, u8 cmd_len)
{
u8 rate = cmd_buf[0] & 0x3F;
bool collision_state = cmd_buf[3] & BIT(0);
rtl92ee_dm_dynamic_arfb_select(hw, rate, collision_state);
}
static void _rtl92ee_c2h_content_parsing(struct ieee80211_hw *hw, u8 c2h_cmd_id,
u8 c2h_cmd_len, u8 *tmp_buf)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
switch (c2h_cmd_id) {
case C2H_8192E_DBG:
RT_TRACE(COMP_FW, DBG_TRACE, "[C2H], C2H_8723BE_DBG!!\n");
break;
case C2H_8192E_TXBF:
RT_TRACE(COMP_FW, DBG_TRACE, "[C2H], C2H_8192E_TXBF!!\n");
break;
case C2H_8192E_TX_REPORT:
RT_TRACE(COMP_FW, DBG_TRACE, "[C2H], C2H_8723BE_TX_REPORT!\n");
break;
case C2H_8192E_BT_INFO:
RT_TRACE(COMP_FW, DBG_TRACE, "[C2H], C2H_8723BE_BT_INFO!!\n");
rtlpriv->btcoexist.btc_ops->btc_btinfo_notify(rtlpriv, tmp_buf,
c2h_cmd_len);
break;
case C2H_8192E_BT_MP:
RT_TRACE(COMP_FW, DBG_TRACE, "[C2H], C2H_8723BE_BT_MP!!\n");
break;
case C2H_8192E_RA_RPT:
_rtl92ee_c2h_ra_report_handler(hw, tmp_buf, c2h_cmd_len);
break;
default:
RT_TRACE(COMP_FW, DBG_TRACE,
"[C2H], Unkown packet!! CmdId(%#X)!\n", c2h_cmd_id);
break;
}
}
void rtl92ee_c2h_packet_handler(struct ieee80211_hw *hw, u8 *buffer, u8 len)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u8 c2h_cmd_id = 0, c2h_cmd_seq = 0, c2h_cmd_len = 0;
u8 *tmp_buf = NULL;
c2h_cmd_id = buffer[0];
c2h_cmd_seq = buffer[1];
c2h_cmd_len = len - 2;
tmp_buf = buffer + 2;
RT_TRACE(COMP_FW, DBG_TRACE,
"[C2H packet], c2hCmdId = 0x%x, c2hCmdSeq = 0x%x, c2hCmdLen =%d\n",
c2h_cmd_id, c2h_cmd_seq, c2h_cmd_len);
RT_PRINT_DATA(rtlpriv, COMP_FW, DBG_TRACE,
"[C2H packet], Content Hex:\n", tmp_buf, c2h_cmd_len);
_rtl92ee_c2h_content_parsing(hw, c2h_cmd_id, c2h_cmd_len, tmp_buf);
}

213
drivers/staging/rtl8192ee/rtl8192ee/fw.h
View File

@ -1,213 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL92E__FW__H__
#define __RTL92E__FW__H__
#define FW_8192C_SIZE 0x8000
#define FW_8192C_START_ADDRESS 0x1000
#define FW_8192C_END_ADDRESS 0x5FFF
#define FW_8192C_PAGE_SIZE 4096
#define FW_8192C_POLLING_DELAY 5
#define FW_8192C_POLLING_TIMEOUT_COUNT 3000
#define IS_FW_HEADER_EXIST(_pfwhdr) \
((_pfwhdr->signature&0xFFF0) == 0x92E0)
#define USE_OLD_WOWLAN_DEBUG_FW 0
#define H2C_92E_RSVDPAGE_LOC_LEN 5
#define H2C_92E_PWEMODE_LENGTH 5
#define H2C_92E_JOINBSSRPT_LENGTH 1
#define H2C_92E_AP_OFFLOAD_LENGTH 3
#define H2C_92E_WOWLAN_LENGTH 3
#define H2C_92E_KEEP_ALIVE_CTRL_LENGTH 3
#if (USE_OLD_WOWLAN_DEBUG_FW == 0)
#define H2C_92E_REMOTE_WAKE_CTRL_LEN 1
#else
#define H2C_92E_REMOTE_WAKE_CTRL_LEN 3
#endif
#define H2C_92E_AOAC_GLOBAL_INFO_LEN 2
#define H2C_92E_AOAC_RSVDPAGE_LOC_LEN 7
/* Fw PS state for RPWM.
*BIT[2:0] = HW state
*BIT[3] = Protocol PS state, 1: register active state, 0: register sleep state
*BIT[4] = sub-state
*/
#define FW_PS_RF_ON BIT(2)
#define FW_PS_REGISTER_ACTIVE BIT(3)
#define FW_PS_ACK BIT(6)
#define FW_PS_TOGGLE BIT(7)
/* 92E RPWM value*/
/* BIT[0] = 1: 32k, 0: 40M*/
#define FW_PS_CLOCK_OFF BIT(0) /* 32k */
#define FW_PS_CLOCK_ON 0 /* 40M */
#define FW_PS_STATE_MASK (0x0F)
#define FW_PS_STATE_HW_MASK (0x07)
#define FW_PS_STATE_INT_MASK (0x3F)
#define FW_PS_STATE(x) (FW_PS_STATE_MASK & (x))
#define FW_PS_STATE_ALL_ON_92E (FW_PS_CLOCK_ON)
#define FW_PS_STATE_RF_ON_92E (FW_PS_CLOCK_ON)
#define FW_PS_STATE_RF_OFF_92E (FW_PS_CLOCK_ON)
#define FW_PS_STATE_RF_OFF_LOW_PWR (FW_PS_CLOCK_OFF)
/* For 92E H2C PwrMode Cmd ID 5.*/
#define FW_PWR_STATE_ACTIVE ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))
#define FW_PWR_STATE_RF_OFF 0
#define FW_PS_IS_ACK(x) ((x) & FW_PS_ACK)
#define IS_IN_LOW_POWER_STATE_92E(FwPSState) \
(FW_PS_STATE(FwPSState) == FW_PS_CLOCK_OFF)
#define FW_PWR_STATE_ACTIVE ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))
#define FW_PWR_STATE_RF_OFF 0
struct rtl92c_firmware_header {
u16 signature;
u8 category;
u8 function;
u16 version;
u8 subversion;
u8 rsvd1;
u8 month;
u8 date;
u8 hour;
u8 minute;
u16 ramcodeSize;
u16 rsvd2;
u32 svnindex;
u32 rsvd3;
u32 rsvd4;
u32 rsvd5;
};
enum rtl8192c_h2c_cmd {
H2C_92E_RSVDPAGE = 0,
H2C_92E_MSRRPT = 1,
H2C_92E_SCAN = 2,
H2C_92E_KEEP_ALIVE_CTRL = 3,
H2C_92E_DISCONNECT_DECISION = 4,
#if (USE_OLD_WOWLAN_DEBUG_FW == 1)
H2C_92E_WO_WLAN = 5,
#endif
H2C_92E_INIT_OFFLOAD = 6,
#if (USE_OLD_WOWLAN_DEBUG_FW == 1)
H2C_92E_REMOTE_WAKE_CTRL = 7,
#endif
H2C_92E_AP_OFFLOAD = 8,
H2C_92E_BCN_RSVDPAGE = 9,
H2C_92E_PROBERSP_RSVDPAGE = 10,
H2C_92E_SETPWRMODE = 0x20,
H2C_92E_PS_TUNING_PARA = 0x21,
H2C_92E_PS_TUNING_PARA2 = 0x22,
H2C_92E_PS_LPS_PARA = 0x23,
H2C_92E_P2P_PS_OFFLOAD = 024,
#if (USE_OLD_WOWLAN_DEBUG_FW == 0)
H2C_92E_WO_WLAN = 0x80,
H2C_92E_REMOTE_WAKE_CTRL = 0x81,
H2C_92E_AOAC_GLOBAL_INFO = 0x82,
H2C_92E_AOAC_RSVDPAGE = 0x83,
#endif
H2C_92E_RA_MASK = 0x40,
H2C_92E_RSSI_REPORT = 0x42,
H2C_92E_SELECTIVE_SUSPEND_ROF_CMD,
H2C_92E_P2P_PS_MODE,
H2C_92E_PSD_RESULT,
/*Not defined CTW CMD for P2P yet*/
H2C_92E_P2P_PS_CTW_CMD,
MAX_92E_H2CCMD
};
enum rtl8192e_c2h_evt {
C2H_8192E_DBG = 0,
C2H_8192E_LB = 1,
C2H_8192E_TXBF = 2,
C2H_8192E_TX_REPORT = 3,
C2H_8192E_BT_INFO = 9,
C2H_8192E_BT_MP = 11,
C2H_8192E_RA_RPT = 12,
MAX_8192E_C2HEVENT
};
#define pagenum_128(_len) \
(u32)(((_len) >> 7) + ((_len) & 0x7F ? 1 : 0))
#define SET_H2CCMD_PWRMODE_PARM_MODE(__ph2ccmd, __val) \
SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
#define SET_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __val) \
SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __val)
#define SET_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __val) \
SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __val)
#define SET_H2CCMD_PWRMODE_PARM_AWAKE_INTERVAL(__pH2CCmd, __val) \
SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __val)
#define SET_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __val) \
SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __val)
#define SET_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __val) \
SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __val)
#define GET_92E_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) \
LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
#define SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(__ph2ccmd, __val) \
SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__ph2ccmd, __val) \
SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__ph2ccmd, __val) \
SET_BITS_TO_LE_1BYTE((__ph2ccmd)+1, 0, 8, __val)
#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__ph2ccmd, __val) \
SET_BITS_TO_LE_1BYTE((__ph2ccmd)+2, 0, 8, __val)
/* _MEDIA_STATUS_RPT_PARM_CMD1 */
#define SET_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
#define SET_H2CCMD_MSRRPT_PARM_MACID_IND(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
#define SET_H2CCMD_MSRRPT_PARM_MACID(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
#define SET_H2CCMD_MSRRPT_PARM_MACID_END(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
int rtl92ee_download_fw(struct ieee80211_hw *hw, bool buse_wake_on_wlan_fw);
void rtl92ee_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id,
u32 cmd_len, u8 *p_cmdbuffer);
void rtl92ee_firmware_selfreset(struct ieee80211_hw *hw);
void rtl92ee_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode);
void rtl92ee_set_fw_media_status_rpt_cmd(struct ieee80211_hw *hw, u8 mstatus);
void rtl92ee_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished);
void rtl92ee_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state);
void rtl92ee_c2h_packet_handler(struct ieee80211_hw *hw, u8 *buffer, u8 len);
#endif

2534
drivers/staging/rtl8192ee/rtl8192ee/hw.c
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File diff suppressed because it is too large Load Diff

67
drivers/staging/rtl8192ee/rtl8192ee/hw.h
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@ -1,67 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL92E_HW_H__
#define __RTL92E_HW_H__
void rtl92ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
void rtl92ee_read_eeprom_info(struct ieee80211_hw *hw);
void rtl92ee_interrupt_recognized(struct ieee80211_hw *hw,
u32 *p_inta, u32 *p_intb);
int rtl92ee_hw_init(struct ieee80211_hw *hw);
void rtl92ee_card_disable(struct ieee80211_hw *hw);
void rtl92ee_enable_interrupt(struct ieee80211_hw *hw);
void rtl92ee_disable_interrupt(struct ieee80211_hw *hw);
int rtl92ee_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type);
void rtl92ee_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid);
void rtl92ee_set_qos(struct ieee80211_hw *hw, int aci);
void rtl92ee_set_beacon_related_registers(struct ieee80211_hw *hw);
void rtl92ee_set_beacon_interval(struct ieee80211_hw *hw);
void rtl92ee_update_interrupt_mask(struct ieee80211_hw *hw,
u32 add_msr, u32 rm_msr);
void rtl92ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
void rtl92ee_update_hal_rate_tbl(struct ieee80211_hw *hw,
struct ieee80211_sta *sta, u8 rssi_level);
void rtl92ee_update_channel_access_setting(struct ieee80211_hw *hw);
bool rtl92ee_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid);
void rtl92ee_enable_hw_security_config(struct ieee80211_hw *hw);
void rtl92ee_set_key(struct ieee80211_hw *hw, u32 key_index,
u8 *p_macaddr, bool is_group, u8 enc_algo,
bool is_wepkey, bool clear_all);
void rtl92ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
bool autoload_fail, u8 *hwinfo);
void rtl92ee_bt_reg_init(struct ieee80211_hw *hw);
void rtl92ee_bt_hw_init(struct ieee80211_hw *hw);
void rtl92ee_suspend(struct ieee80211_hw *hw);
void rtl92ee_resume(struct ieee80211_hw *hw);
void rtl92ee_allow_all_destaddr(struct ieee80211_hw *hw, bool allow_all_da,
bool write_into_reg);
void rtl92ee_fw_clk_off_timer_callback(unsigned long data);
#endif

132
drivers/staging/rtl8192ee/rtl8192ee/led.c
View File

@ -1,132 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../wifi.h"
#include "../pci.h"
#include "led.h"
#include "reg.h"
static void _rtl92ee_init_led(struct ieee80211_hw *hw,
struct rtl_led *pled, enum rtl_led_pin ledpin)
{
pled->hw = hw;
pled->ledpin = ledpin;
pled->b_ledon = false;
}
void rtl92ee_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
{
u32 ledcfg;
struct rtl_priv *rtlpriv = rtl_priv(hw);
RT_TRACE(COMP_LED, DBG_LOUD, "LedAddr:%X ledpin =%d\n",
REG_LEDCFG2, pled->ledpin);
switch (pled->ledpin) {
case LED_PIN_GPIO0:
break;
case LED_PIN_LED0:
ledcfg = rtl_read_dword(rtlpriv, REG_GPIO_PIN_CTRL) | BIT(21);
ledcfg &= ~BIT(13) & ~BIT(29);
rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, ledcfg);
break;
case LED_PIN_LED1:
break;
default:
RT_TRACE(COMP_ERR, DBG_EMERG, "switch case not processed\n");
break;
}
pled->b_ledon = true;
}
void rtl92ee_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 ledcfg;
RT_TRACE(COMP_LED, DBG_LOUD, "LedAddr:%X ledpin =%d\n",
REG_LEDCFG2, pled->ledpin);
switch (pled->ledpin) {
case LED_PIN_GPIO0:
break;
case LED_PIN_LED0:
ledcfg = rtl_read_dword(rtlpriv , REG_GPIO_PIN_CTRL) | ~BIT(21);
ledcfg &= ~BIT(29);
rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, ledcfg);
break;
case LED_PIN_LED1:
break;
default:
RT_TRACE(COMP_ERR, DBG_LOUD, "switch case not processed\n");
break;
}
pled->b_ledon = false;
}
void rtl92ee_init_sw_leds(struct ieee80211_hw *hw)
{
struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
_rtl92ee_init_led(hw, &(pcipriv->ledctl.sw_led0), LED_PIN_LED0);
_rtl92ee_init_led(hw, &(pcipriv->ledctl.sw_led1), LED_PIN_LED1);
}
static void _rtl92ee_sw_led_control(struct ieee80211_hw *hw,
enum led_ctl_mode ledaction)
{
struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
switch (ledaction) {
case LED_CTL_POWER_ON:
case LED_CTL_LINK:
case LED_CTL_NO_LINK:
rtl92ee_sw_led_on(hw, pLed0);
break;
case LED_CTL_POWER_OFF:
rtl92ee_sw_led_off(hw, pLed0);
break;
default:
break;
}
}
void rtl92ee_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
if ((ppsc->rfoff_reason > RF_CHANGE_BY_PS) &&
(ledaction == LED_CTL_TX ||
ledaction == LED_CTL_RX ||
ledaction == LED_CTL_SITE_SURVEY ||
ledaction == LED_CTL_LINK ||
ledaction == LED_CTL_NO_LINK ||
ledaction == LED_CTL_START_TO_LINK ||
ledaction == LED_CTL_POWER_ON)) {
return;
}
RT_TRACE(COMP_LED, DBG_TRACE, "ledaction %d\n", ledaction);
_rtl92ee_sw_led_control(hw, ledaction);
}

37
drivers/staging/rtl8192ee/rtl8192ee/led.h
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@ -1,37 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL92E_LED_H__
#define __RTL92E_LED_H__
void rtl92ee_init_sw_leds(struct ieee80211_hw *hw);
void rtl92ee_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
void rtl92ee_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
void rtl92ee_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction);
#endif

3263
drivers/staging/rtl8192ee/rtl8192ee/phy.c
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File diff suppressed because it is too large Load Diff

154
drivers/staging/rtl8192ee/rtl8192ee/phy.h
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@ -1,154 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL92E_PHY_H__
#define __RTL92E_PHY_H__
/*It must always set to 4, otherwise read efuse table secquence will be wrong.*/
#define MAX_TX_COUNT 4
#define TX_1S 0
#define TX_2S 1
#define TX_3S 2
#define TX_4S 3
#define MAX_POWER_INDEX 0x3f
#define MAX_PRECMD_CNT 16
#define MAX_RFDEPENDCMD_CNT 16
#define MAX_POSTCMD_CNT 16
#define MAX_DOZE_WAITING_TIMES_9x 64
#define RT_CANNOT_IO(hw) false
#define HIGHPOWER_RADIOA_ARRAYLEN 22
#define IQK_ADDA_REG_NUM 16
#define IQK_MAC_REG_NUM 4
#define IQK_BB_REG_NUM 9
#define MAX_TOLERANCE 5
#define IQK_DELAY_TIME 10
#define index_mapping_NUM 15
#define APK_BB_REG_NUM 5
#define APK_AFE_REG_NUM 16
#define APK_CURVE_REG_NUM 4
#define PATH_NUM 2
#define LOOP_LIMIT 5
#define MAX_STALL_TIME 50
#define AntennaDiversityValue 0x80
#define MAX_TXPWR_IDX_NMODE_92S 63
#define Reset_Cnt_Limit 3
#define RF6052_MAX_PATH 2
#define CT_OFFSET_MAC_ADDR 0X16
#define CT_OFFSET_CCK_TX_PWR_IDX 0x5A
#define CT_OFFSET_HT401S_TX_PWR_IDX 0x60
#define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF 0x66
#define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69
#define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C
#define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F
#define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72
#define CT_OFFSET_CHANNEL_PLAH 0x75
#define CT_OFFSET_THERMAL_METER 0x78
#define CT_OFFSET_RF_OPTION 0x79
#define CT_OFFSET_VERSION 0x7E
#define CT_OFFSET_CUSTOMER_ID 0x7F
#define RTL92C_MAX_PATH_NUM 2
enum swchnlcmd_id {
CMDID_END,
CMDID_SET_TXPOWEROWER_LEVEL,
CMDID_BBREGWRITE10,
CMDID_WRITEPORT_ULONG,
CMDID_WRITEPORT_USHORT,
CMDID_WRITEPORT_UCHAR,
CMDID_RF_WRITEREG,
};
struct swchnlcmd {
enum swchnlcmd_id cmdid;
u32 para1;
u32 para2;
u32 msdelay;
};
enum baseband_config_type {
BASEBAND_CONFIG_PHY_REG = 0,
BASEBAND_CONFIG_AGC_TAB = 1,
};
enum ant_div_type {
NO_ANTDIV = 0xFF,
CG_TRX_HW_ANTDIV = 0x01,
CGCS_RX_HW_ANTDIV = 0x02,
FIXED_HW_ANTDIV = 0x03,
CG_TRX_SMART_ANTDIV = 0x04,
CGCS_RX_SW_ANTDIV = 0x05,
};
extern u32 rtl92ee_phy_query_bb_reg(struct ieee80211_hw *hw,
u32 regaddr, u32 bitmask);
extern void rtl92ee_phy_set_bb_reg(struct ieee80211_hw *hw,
u32 regaddr, u32 bitmask, u32 data);
extern u32 rtl92ee_phy_query_rf_reg(struct ieee80211_hw *hw,
enum radio_path rfpath, u32 regaddr,
u32 bitmask);
extern void rtl92ee_phy_set_rf_reg(struct ieee80211_hw *hw,
enum radio_path rfpath, u32 regaddr,
u32 bitmask, u32 data);
extern bool rtl92ee_phy_mac_config(struct ieee80211_hw *hw);
extern bool rtl92ee_phy_bb_config(struct ieee80211_hw *hw);
extern bool rtl92ee_phy_rf_config(struct ieee80211_hw *hw);
extern void rtl92ee_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
extern void rtl92ee_phy_get_txpower_level(struct ieee80211_hw *hw,
long *powerlevel);
extern void rtl92ee_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
extern void rtl92ee_phy_scan_operation_backup(struct ieee80211_hw *hw,
u8 operation);
extern void rtl92ee_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
extern void rtl92ee_phy_set_bw_mode(struct ieee80211_hw *hw,
enum nl80211_channel_type ch_type);
extern void rtl92ee_phy_sw_chnl_callback(struct ieee80211_hw *hw);
extern u8 rtl92ee_phy_sw_chnl(struct ieee80211_hw *hw);
extern void rtl92ee_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
void rtl92ee_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
void rtl92ee_phy_lc_calibrate(struct ieee80211_hw *hw);
void rtl92ee_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
bool rtl92ee_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
enum radio_path rfpath);
bool rtl92ee_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
extern bool rtl92ee_phy_set_rf_power_state(struct ieee80211_hw *hw,
enum rf_pwrstate rfpwr_state);
#endif

108
drivers/staging/rtl8192ee/rtl8192ee/pwrseq.c
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@ -1,108 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "pwrseqcmd.h"
#include "pwrseq.h"
/*
drivers should parse below arrays and do the corresponding actions
*/
/*3 Power on Array*/
struct wlan_pwr_cfg rtl8192E_power_on_flow[RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS +
RTL8192E_TRANS_END_STEPS] = {
RTL8192E_TRANS_CARDEMU_TO_ACT
RTL8192E_TRANS_END
};
/*3Radio off GPIO Array */
struct wlan_pwr_cfg rtl8192E_radio_off_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS
+ RTL8192E_TRANS_END_STEPS] = {
RTL8192E_TRANS_ACT_TO_CARDEMU
RTL8192E_TRANS_END
};
/*3Card Disable Array*/
struct wlan_pwr_cfg rtl8192E_card_disable_flow
[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS +
RTL8192E_TRANS_END_STEPS] = {
RTL8192E_TRANS_ACT_TO_CARDEMU
RTL8192E_TRANS_CARDEMU_TO_CARDDIS
RTL8192E_TRANS_END
};
/*3 Card Enable Array*/
struct wlan_pwr_cfg rtl8192E_card_enable_flow
[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS +
RTL8192E_TRANS_END_STEPS] = {
RTL8192E_TRANS_CARDDIS_TO_CARDEMU
RTL8192E_TRANS_CARDEMU_TO_ACT
RTL8192E_TRANS_END
};
/*3Suspend Array*/
struct wlan_pwr_cfg rtl8192E_suspend_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS +
RTL8192E_TRANS_END_STEPS] = {
RTL8192E_TRANS_ACT_TO_CARDEMU
RTL8192E_TRANS_CARDEMU_TO_SUS
RTL8192E_TRANS_END
};
/*3 Resume Array*/
struct wlan_pwr_cfg rtl8192E_resume_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS +
RTL8192E_TRANS_END_STEPS] = {
RTL8192E_TRANS_SUS_TO_CARDEMU
RTL8192E_TRANS_CARDEMU_TO_ACT
RTL8192E_TRANS_END
};
/*3HWPDN Array*/
struct wlan_pwr_cfg rtl8192E_hwpdn_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS +
RTL8192E_TRANS_END_STEPS] = {
RTL8192E_TRANS_ACT_TO_CARDEMU
RTL8192E_TRANS_CARDEMU_TO_PDN
RTL8192E_TRANS_END
};
/*3 Enter LPS */
struct wlan_pwr_cfg rtl8192E_enter_lps_flow[RTL8192E_TRANS_ACT_TO_LPS_STEPS +
RTL8192E_TRANS_END_STEPS] = {
/*FW behavior*/
RTL8192E_TRANS_ACT_TO_LPS
RTL8192E_TRANS_END
};
/*3 Leave LPS */
struct wlan_pwr_cfg rtl8192E_leave_lps_flow[RTL8192E_TRANS_LPS_TO_ACT_STEPS +
RTL8192E_TRANS_END_STEPS] = {
/*FW behavior*/
RTL8192E_TRANS_LPS_TO_ACT
RTL8192E_TRANS_END
};

355
drivers/staging/rtl8192ee/rtl8192ee/pwrseq.h
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@ -1,355 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL92E_PWRSEQ_H__
#define __RTL92E_PWRSEQ_H__
#include "pwrseqcmd.h"
/*
Check document WM-20110607-Paul-RTL8192E_Power_Architecture-R02.vsd
There are 6 HW Power States:
0: POFF--Power Off
1: PDN--Power Down
2: CARDEMU--Card Emulation
3: ACT--Active Mode
4: LPS--Low Power State
5: SUS--Suspend
The transision from different states are defined below
TRANS_CARDEMU_TO_ACT
TRANS_ACT_TO_CARDEMU
TRANS_CARDEMU_TO_SUS
TRANS_SUS_TO_CARDEMU
TRANS_CARDEMU_TO_PDN
TRANS_ACT_TO_LPS
TRANS_LPS_TO_ACT
TRANS_END
PWR SEQ Version: rtl8192E_PwrSeq_V09.h
*/
#define RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS 18
#define RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS 18
#define RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS 18
#define RTL8192E_TRANS_SUS_TO_CARDEMU_STEPS 18
#define RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS 18
#define RTL8192E_TRANS_PDN_TO_CARDEMU_STEPS 18
#define RTL8192E_TRANS_ACT_TO_LPS_STEPS 23
#define RTL8192E_TRANS_LPS_TO_ACT_STEPS 23
#define RTL8192E_TRANS_END_STEPS 1
#define RTL8192E_TRANS_CARDEMU_TO_ACT \
/* format */ \
/* comments here */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
/* disable HWPDN 0x04[15]=0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0}, \
/* disable SW LPS 0x04[10]=0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), 0}, \
/* disable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0}, \
/* wait till 0x04[17] = 1 power ready*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(1), BIT(1)}, \
/* release WLON reset 0x04[16]=1*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
/* polling until return 0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
/**/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(0), 0},
#define RTL8192E_TRANS_ACT_TO_CARDEMU \
/* format */ \
/* comments here */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
/*0x1F[7:0] = 0 turn off RF*/ \
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0}, \
/*0x4C[23]=0x4E[7]=0, switch DPDT_SEL_P output from register 0x65[2] */\
{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0}, \
/*0x04[9] = 1 turn off MAC by HW state machine*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), BIT(1)}, \
/*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(1), 0},
#define RTL8192E_TRANS_CARDEMU_TO_SUS \
/* format */ \
/* comments here */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
/*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))},\
/*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
/*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},\
/*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
/*wait power state to suspend*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), 0},
#define RTL8192E_TRANS_SUS_TO_CARDEMU \
/* format */ \
/* comments here */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
/*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), 0}, \
/*wait power state to suspend*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), BIT(1)}, \
/*0x04[12:11] = 2b'01enable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
#define RTL8192E_TRANS_CARDEMU_TO_CARDDIS \
/* format */ \
/* comments here */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
/*0x07=0x20 , SOP option to disable BG/MB*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x20}, \
/*Unlock small LDO Register*/ \
{0x00CC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), BIT(2)}, \
/*Disable small LDO*/ \
{0x0011, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0}, \
/*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC, \
PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
/*0x04[10] = 1, enable SW LPS*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), BIT(2)}, \
/*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
/*wait power state to suspend*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), 0},
#define RTL8192E_TRANS_CARDDIS_TO_CARDEMU \
/* format */ \
/* comments here */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
/*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), 0}, \
/*wait power state to suspend*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), BIT(1)}, \
/*Enable small LDO*/ \
{0x0011, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
/*Lock small LDO Register*/ \
{0x00CC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), 0}, \
/*0x04[12:11] = 2b'01enable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
#define RTL8192E_TRANS_CARDEMU_TO_PDN \
/* format */ \
/* comments here */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
/* 0x04[16] = 0*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0}, \
/* 0x04[15] = 1*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), BIT(7)},
#define RTL8192E_TRANS_PDN_TO_CARDEMU \
/* format */ \
/* comments here */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
/* 0x04[15] = 0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0},
#define RTL8192E_TRANS_ACT_TO_LPS \
/* format */ \
/* comments here */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
/*PCIe DMA stop*/ \
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF}, \
/*Tx Pause*/ \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF}, \
/*Should be zero if no packet is transmitting*/ \
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0}, \
/*Should be zero if no packet is transmitting*/ \
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0}, \
/*Should be zero if no packet is transmitting*/ \
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0}, \
/*Should be zero if no packet is transmitting*/ \
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0}, \
/*CCK and OFDM are disabled,and clock are gated*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0}, \
/*Delay 1us*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, \
/*Whole BB is reset*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), 0}, \
/*Reset MAC TRX*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x03}, \
/*check if removed later*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), 0}, \
/*When driver enter Sus/ Disable, enable LOP for BT*/ \
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x00}, \
/*Respond TxOK to scheduler*/ \
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(5), BIT(5)},
#define RTL8192E_TRANS_LPS_TO_ACT \
/* format */ \
/* comments here */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
/*SDIO RPWM, For Repeatly In and out, Taggle bit should be changed*/\
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_SDIO , PWR_CMD_WRITE, 0xFF, 0x84}, \
/*USB RPWM*/ \
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x84}, \
/*PCIe RPWM*/ \
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x84}, \
/*Delay*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, \
/*0x08[4] = 0 switch TSF to 40M*/ \
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(4), 0}, \
/*Polling 0x109[7]=0 TSF in 40M*/ \
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(7), 0}, \
/*0x101[1] = 1*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), BIT(1)}, \
/*0x100[7:0] = 0xFF enable WMAC TRX*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF}, \
/* 0x02[1:0] = 2b'11 enable BB macro*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)},\
/*0x522 = 0*/ \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0}, \
/*Clear ISR*/ \
{0x013D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF},
#define RTL8192E_TRANS_END \
/* format */ \
/* comments here */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
0, PWR_CMD_END, 0, 0},
extern struct wlan_pwr_cfg rtl8192E_power_on_flow
[RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS +
RTL8192E_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8192E_radio_off_flow
[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8192E_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8192E_card_disable_flow
[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS +
RTL8192E_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8192E_card_enable_flow
[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS +
RTL8192E_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8192E_suspend_flow
[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS +
RTL8192E_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8192E_resume_flow
[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS +
RTL8192E_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8192E_hwpdn_flow
[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS +
RTL8192E_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8192E_enter_lps_flow
[RTL8192E_TRANS_ACT_TO_LPS_STEPS +
RTL8192E_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8192E_leave_lps_flow
[RTL8192E_TRANS_LPS_TO_ACT_STEPS +
RTL8192E_TRANS_END_STEPS];
/* RTL8192EE Power Configuration CMDs for PCIe interface */
#define Rtl8192E_NIC_PWR_ON_FLOW rtl8192E_power_on_flow
#define Rtl8192E_NIC_RF_OFF_FLOW rtl8192E_radio_off_flow
#define Rtl8192E_NIC_DISABLE_FLOW rtl8192E_card_disable_flow
#define Rtl8192E_NIC_ENABLE_FLOW rtl8192E_card_enable_flow
#define Rtl8192E_NIC_SUSPEND_FLOW rtl8192E_suspend_flow
#define Rtl8192E_NIC_RESUME_FLOW rtl8192E_resume_flow
#define Rtl8192E_NIC_PDN_FLOW rtl8192E_hwpdn_flow
#define Rtl8192E_NIC_LPS_ENTER_FLOW rtl8192E_enter_lps_flow
#define Rtl8192E_NIC_LPS_LEAVE_FLOW rtl8192E_leave_lps_flow
#endif

138
drivers/staging/rtl8192ee/rtl8192ee/pwrseqcmd.c
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@ -1,138 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "pwrseq.h"
/*
* Description:
* This routine deal with the Power Configuration CMDs
* parsing for RTL8723/RTL8188E Series IC.
* Assumption:
* We should follow specific format which was released from HW SD.
*
* 2011.07.07, added by Roger.
*/
bool rtl92e_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
u8 fab_version, u8 interface_type,
struct wlan_pwr_cfg pwrcfgcmd[])
{
struct wlan_pwr_cfg pwr_cfg_cmd = {0};
bool b_polling_bit = false;
u32 ary_idx = 0;
u8 value = 0;
u32 offset = 0;
u32 polling_count = 0;
u32 max_polling_cnt = 5000;
do {
pwr_cfg_cmd = pwrcfgcmd[ary_idx];
RT_TRACE(COMP_INIT, DBG_TRACE,
"offset(%#x), cut_msk(%#x), fab_msk(%#x), interface_msk(%#x), base(%#x), cmd(%#x), msk(%#x), value(%#x)\n",
GET_PWR_CFG_OFFSET(pwr_cfg_cmd),
GET_PWR_CFG_CUT_MASK(pwr_cfg_cmd),
GET_PWR_CFG_FAB_MASK(pwr_cfg_cmd),
GET_PWR_CFG_INTF_MASK(pwr_cfg_cmd),
GET_PWR_CFG_BASE(pwr_cfg_cmd),
GET_PWR_CFG_CMD(pwr_cfg_cmd),
GET_PWR_CFG_MASK(pwr_cfg_cmd),
GET_PWR_CFG_VALUE(pwr_cfg_cmd));
if ((GET_PWR_CFG_FAB_MASK(pwr_cfg_cmd)&fab_version) &&
(GET_PWR_CFG_CUT_MASK(pwr_cfg_cmd)&cut_version) &&
(GET_PWR_CFG_INTF_MASK(pwr_cfg_cmd)&interface_type)) {
switch (GET_PWR_CFG_CMD(pwr_cfg_cmd)) {
case PWR_CMD_READ:
RT_TRACE(COMP_INIT, DBG_TRACE,
"PWR_CMD_READ\n");
break;
case PWR_CMD_WRITE:
RT_TRACE(COMP_INIT, DBG_TRACE,
"PWR_CMD_WRITE\n");
offset = GET_PWR_CFG_OFFSET(pwr_cfg_cmd);
/*Read the value from system register*/
value = rtl_read_byte(rtlpriv, offset);
value &= (~(GET_PWR_CFG_MASK(pwr_cfg_cmd)));
value |= (GET_PWR_CFG_VALUE(pwr_cfg_cmd) &
GET_PWR_CFG_MASK(pwr_cfg_cmd));
/*Write value back to sytem register*/
rtl_write_byte(rtlpriv, offset, value);
break;
case PWR_CMD_POLLING:
RT_TRACE(COMP_INIT, DBG_TRACE,
"PWR_CMD_POLLING\n");
b_polling_bit = false;
offset = GET_PWR_CFG_OFFSET(pwr_cfg_cmd);
do {
value = rtl_read_byte(rtlpriv, offset);
value &= GET_PWR_CFG_MASK(pwr_cfg_cmd);
if (value ==
(GET_PWR_CFG_VALUE(pwr_cfg_cmd) &
GET_PWR_CFG_MASK(pwr_cfg_cmd)))
b_polling_bit = true;
else
udelay(10);
if (polling_count++ > max_polling_cnt) {
RT_TRACE(COMP_INIT, DBG_LOUD,
"polling fail\n");
return false;
}
} while (!b_polling_bit);
break;
case PWR_CMD_DELAY:
RT_TRACE(COMP_INIT, DBG_TRACE,
"PWR_CMD_DELAY\n");
if (GET_PWR_CFG_VALUE(pwr_cfg_cmd) ==
PWRSEQ_DELAY_US)
udelay(GET_PWR_CFG_OFFSET(pwr_cfg_cmd));
else
mdelay(GET_PWR_CFG_OFFSET(pwr_cfg_cmd));
break;
case PWR_CMD_END:
RT_TRACE(COMP_INIT, DBG_TRACE, "PWR_CMD_END\n");
return true;
break;
default:
RT_ASSERT(false, ("Unknown CMD!!\n"));
break;
}
}
ary_idx++;
} while (1);
return true;
}

69
drivers/staging/rtl8192ee/rtl8192ee/pwrseqcmd.h
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@ -1,69 +0,0 @@
#ifndef __RTL92E_PWRSEQCMD_H__
#define __RTL92E_PWRSEQCMD_H__
#include "../wifi.h"
/*---------------------------------------------*/
/* The value of cmd: 4 bits */
/*---------------------------------------------*/
#define PWR_CMD_READ 0x00
#define PWR_CMD_WRITE 0x01
#define PWR_CMD_POLLING 0x02
#define PWR_CMD_DELAY 0x03
#define PWR_CMD_END 0x04
/* define the base address of each block */
#define PWR_BASEADDR_MAC 0x00
#define PWR_BASEADDR_USB 0x01
#define PWR_BASEADDR_PCIE 0x02
#define PWR_BASEADDR_SDIO 0x03
#define PWR_INTF_SDIO_MSK BIT(0)
#define PWR_INTF_USB_MSK BIT(1)
#define PWR_INTF_PCI_MSK BIT(2)
#define PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
#define PWR_FAB_TSMC_MSK BIT(0)
#define PWR_FAB_UMC_MSK BIT(1)
#define PWR_FAB_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
#define PWR_CUT_TESTCHIP_MSK BIT(0)
#define PWR_CUT_A_MSK BIT(1)
#define PWR_CUT_B_MSK BIT(2)
#define PWR_CUT_C_MSK BIT(3)
#define PWR_CUT_D_MSK BIT(4)
#define PWR_CUT_E_MSK BIT(5)
#define PWR_CUT_F_MSK BIT(6)
#define PWR_CUT_G_MSK BIT(7)
#define PWR_CUT_ALL_MSK 0xFF
enum pwrseq_delay_unit {
PWRSEQ_DELAY_US,
PWRSEQ_DELAY_MS,
};
struct wlan_pwr_cfg {
u16 offset;
u8 cut_msk;
u8 fab_msk:4;
u8 interface_msk:4;
u8 base:4;
u8 cmd:4;
u8 msk;
u8 value;
};
#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset
#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk
#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk
#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk
#define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base
#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd
#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk
#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value
bool rtl92e_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
u8 fab_version, u8 interface_type,
struct wlan_pwr_cfg pwrcfgcmd[]);
#endif

2240
drivers/staging/rtl8192ee/rtl8192ee/reg.h
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150
drivers/staging/rtl8192ee/rtl8192ee/rf.c
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@ -1,150 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../wifi.h"
#include "reg.h"
#include "def.h"
#include "phy.h"
#include "rf.h"
#include "dm.h"
static bool _rtl92ee_phy_rf6052_config_parafile(struct ieee80211_hw *hw);
void rtl92ee_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
switch (bandwidth) {
case HT_CHANNEL_WIDTH_20:
rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
0xfffff3ff) | BIT(10) | BIT(11));
rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
rtlphy->rfreg_chnlval[0]);
rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, RFREG_OFFSET_MASK,
rtlphy->rfreg_chnlval[0]);
break;
case HT_CHANNEL_WIDTH_20_40:
rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
0xfffff3ff) | BIT(10));
rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
rtlphy->rfreg_chnlval[0]);
rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, RFREG_OFFSET_MASK,
rtlphy->rfreg_chnlval[0]);
break;
default:
RT_TRACE(COMP_ERR, DBG_EMERG, "unknown bandwidth: %#X\n",
bandwidth);
break;
}
}
bool rtl92ee_phy_rf6052_config(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
if (rtlphy->rf_type == RF_1T1R)
rtlphy->num_total_rfpath = 1;
else
rtlphy->num_total_rfpath = 2;
return _rtl92ee_phy_rf6052_config_parafile(hw);
}
static bool _rtl92ee_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
u32 u4_regvalue = 0;
u8 rfpath;
bool rtstatus = true;
struct bb_reg_def *pphyreg;
for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
pphyreg = &rtlphy->phyreg_def[rfpath];
switch (rfpath) {
case RF90_PATH_A:
case RF90_PATH_C:
u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
BRFSI_RFENV);
break;
case RF90_PATH_B:
case RF90_PATH_D:
u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
BRFSI_RFENV << 16);
break;
}
rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
udelay(1);
rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
udelay(1);
rtl_set_bbreg(hw, pphyreg->rfhssi_para2,
B3WIREADDREAALENGTH, 0x0);
udelay(1);
rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
udelay(1);
switch (rfpath) {
case RF90_PATH_A:
rtstatus = rtl92ee_phy_config_rf_with_headerfile(hw,
(enum radio_path)rfpath);
break;
case RF90_PATH_B:
rtstatus = rtl92ee_phy_config_rf_with_headerfile(hw,
(enum radio_path)rfpath);
break;
case RF90_PATH_C:
break;
case RF90_PATH_D:
break;
}
switch (rfpath) {
case RF90_PATH_A:
case RF90_PATH_C:
rtl_set_bbreg(hw, pphyreg->rfintfs,
BRFSI_RFENV, u4_regvalue);
break;
case RF90_PATH_B:
case RF90_PATH_D:
rtl_set_bbreg(hw, pphyreg->rfintfs,
BRFSI_RFENV << 16, u4_regvalue);
break;
}
if (!rtstatus) {
RT_TRACE(COMP_INIT, DBG_TRACE, "Radio[%d] Fail!!\n",
rfpath);
return false;
}
}
RT_TRACE(COMP_INIT, DBG_TRACE, "\n");
return rtstatus;
}

39
drivers/staging/rtl8192ee/rtl8192ee/rf.h
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@ -1,39 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL92E_RF_H__
#define __RTL92E_RF_H__
#define RF6052_MAX_TX_PWR 0x3F
#define RF6052_MAX_REG 0x3F
extern void rtl92ee_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw,
u8 bandwidth);
extern bool rtl92ee_phy_rf6052_config(struct ieee80211_hw *hw);
#endif

425
drivers/staging/rtl8192ee/rtl8192ee/sw.c
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@ -1,425 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include <linux/vmalloc.h>
#include <linux/module.h>
#include "../wifi.h"
#include "../core.h"
#include "../pci.h"
#include "reg.h"
#include "def.h"
#include "phy.h"
#include "dm.h"
#include "hw.h"
#include "sw.h"
#include "fw.h"
#include "trx.h"
#include "led.h"
#include "table.h"
#include "../btcoexist/rtl_btc.h"
static void rtl92ee_init_aspm_vars(struct ieee80211_hw *hw)
{
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
/*close ASPM for AMD defaultly */
rtlpci->const_amdpci_aspm = 0;
/*
* ASPM PS mode.
* 0 - Disable ASPM,
* 1 - Enable ASPM without Clock Req,
* 2 - Enable ASPM with Clock Req,
* 3 - Alwyas Enable ASPM with Clock Req,
* 4 - Always Enable ASPM without Clock Req.
* set defult to RTL8192CE:3 RTL8192E:2
* */
rtlpci->const_pci_aspm = 3;
/*Setting for PCI-E device */
rtlpci->const_devicepci_aspm_setting = 0x03;
/*Setting for PCI-E bridge */
rtlpci->const_hostpci_aspm_setting = 0x02;
/*
* In Hw/Sw Radio Off situation.
* 0 - Default,
* 1 - From ASPM setting without low Mac Pwr,
* 2 - From ASPM setting with low Mac Pwr,
* 3 - Bus D3
* set default to RTL8192CE:0 RTL8192SE:2
*/
rtlpci->const_hwsw_rfoff_d3 = 0;
/*
* This setting works for those device with
* backdoor ASPM setting such as EPHY setting.
* 0 - Not support ASPM,
* 1 - Support ASPM,
* 2 - According to chipset.
*/
rtlpci->const_support_pciaspm = 1;
}
int rtl92ee_init_sw_vars(struct ieee80211_hw *hw)
{
int err = 0;
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
const struct firmware *firmware;
char *fw_name = NULL;
rtl92ee_bt_reg_init(hw);
rtlpci->msi_support = true;
rtlpriv->btcoexist.btc_ops = stg_rtl_btc_get_ops_pointer();
rtlpriv->dm.b_dm_initialgain_enable = 1;
rtlpriv->dm.dm_flag = 0;
rtlpriv->dm.b_disable_framebursting = 0;
/*rtlpriv->dm.thermalvalue = 0;*/
rtlpci->transmit_config = CFENDFORM | BIT(15);
/*just 2.4G band*/
rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
rtlpci->receive_config = (RCR_APPFCS |
RCR_APP_MIC |
RCR_APP_ICV |
RCR_APP_PHYST_RXFF |
RCR_HTC_LOC_CTRL |
RCR_AMF |
RCR_ACF |
RCR_ADF |
RCR_AICV |
RCR_ACRC32 |
RCR_AB |
RCR_AM |
RCR_APM |
0);
rtlpci->irq_mask[0] = (u32) (IMR_PSTIMEOUT |
/* IMR_TBDER |
IMR_TBDOK |
IMR_BCNDMAINT0 |*/
IMR_C2HCMD |
IMR_HIGHDOK |
IMR_MGNTDOK |
IMR_BKDOK |
IMR_BEDOK |
IMR_VIDOK |
IMR_VODOK |
IMR_RDU |
IMR_ROK |
0);
rtlpci->irq_mask[1] = (u32) (IMR_RXFOVW | 0);
/* for debug level */
rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
/* for LPS & IPS */
rtlpriv->psc.b_inactiveps = rtlpriv->cfg->mod_params->b_inactiveps;
rtlpriv->psc.b_swctrl_lps = rtlpriv->cfg->mod_params->b_swctrl_lps;
rtlpriv->psc.b_fwctrl_lps = rtlpriv->cfg->mod_params->b_fwctrl_lps;
rtlpriv->psc.b_reg_fwctrl_lps = 3;
rtlpriv->psc.reg_max_lps_awakeintvl = 5;
/* for ASPM, you can close aspm through
* set const_support_pciaspm = 0 */
rtl92ee_init_aspm_vars(hw);
if (rtlpriv->psc.b_reg_fwctrl_lps == 1)
rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
else if (rtlpriv->psc.b_reg_fwctrl_lps == 2)
rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
else if (rtlpriv->psc.b_reg_fwctrl_lps == 3)
rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
/* for early mode */
rtlpriv->rtlhal.b_earlymode_enable = false;
/*low power */
rtlpriv->psc.b_low_power_enable = false;
/* for firmware buf */
rtlpriv->rtlhal.pfirmware = vmalloc(0x8000);
if (!rtlpriv->rtlhal.pfirmware) {
RT_TRACE(COMP_ERR, DBG_EMERG, "Can't alloc buffer for fw\n");
return 1;
}
fw_name = "rtlwifi/rtl8192eefw.bin";
err = request_firmware(&firmware, fw_name, rtlpriv->io.dev);
if (err) {
RT_TRACE(COMP_ERR, DBG_EMERG, "Failed to request firmware!\n");
return 1;
}
if (firmware->size > 0x8000) {
RT_TRACE(COMP_ERR, DBG_EMERG, "Firmware is too big!\n");
release_firmware(firmware);
return 1;
}
memcpy(rtlpriv->rtlhal.pfirmware, firmware->data, firmware->size);
rtlpriv->rtlhal.fwsize = firmware->size;
release_firmware(firmware);
return err;
}
void rtl92ee_deinit_sw_vars(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
if (rtlpriv->rtlhal.pfirmware) {
vfree(rtlpriv->rtlhal.pfirmware);
rtlpriv->rtlhal.pfirmware = NULL;
}
}
/* get bt coexist status */
bool rtl92ee_get_btc_status(void)
{
return true;
}
static struct rtl_hal_ops rtl8192ee_hal_ops = {
.init_sw_vars = rtl92ee_init_sw_vars,
.deinit_sw_vars = rtl92ee_deinit_sw_vars,
.read_eeprom_info = rtl92ee_read_eeprom_info,
.interrupt_recognized = rtl92ee_interrupt_recognized,/*need check*/
.hw_init = rtl92ee_hw_init,
.hw_disable = rtl92ee_card_disable,
.hw_suspend = rtl92ee_suspend,
.hw_resume = rtl92ee_resume,
.enable_interrupt = rtl92ee_enable_interrupt,
.disable_interrupt = rtl92ee_disable_interrupt,
.set_network_type = rtl92ee_set_network_type,
.set_chk_bssid = rtl92ee_set_check_bssid,
.set_qos = rtl92ee_set_qos,
.set_bcn_reg = rtl92ee_set_beacon_related_registers,
.set_bcn_intv = rtl92ee_set_beacon_interval,
.update_interrupt_mask = rtl92ee_update_interrupt_mask,
.get_hw_reg = rtl92ee_get_hw_reg,
.set_hw_reg = rtl92ee_set_hw_reg,
.update_rate_tbl = rtl92ee_update_hal_rate_tbl,
.pre_fill_tx_bd_desc = rtl92ee_pre_fill_tx_bd_desc,
.rx_desc_buff_remained_cnt = rtl92ee_rx_desc_buff_remained_cnt,
.rx_check_dma_ok = rtl92ee_rx_check_dma_ok,
.fill_tx_desc = rtl92ee_tx_fill_desc,
.fill_tx_cmddesc = rtl92ee_tx_fill_cmddesc,
.query_rx_desc = rtl92ee_rx_query_desc,
.set_channel_access = rtl92ee_update_channel_access_setting,
.radio_onoff_checking = rtl92ee_gpio_radio_on_off_checking,
.set_bw_mode = rtl92ee_phy_set_bw_mode,
.switch_channel = rtl92ee_phy_sw_chnl,
.dm_watchdog = rtl92ee_dm_watchdog,
.scan_operation_backup = rtl92ee_phy_scan_operation_backup,
.set_rf_power_state = rtl92ee_phy_set_rf_power_state,
.led_control = rtl92ee_led_control,
.set_desc = rtl92ee_set_desc,
.get_desc = rtl92ee_get_desc,
.is_tx_desc_closed = rtl92ee_is_tx_desc_closed,
.enable_hw_sec = rtl92ee_enable_hw_security_config,
.set_key = rtl92ee_set_key,
.init_sw_leds = rtl92ee_init_sw_leds,
.allow_all_destaddr = rtl92ee_allow_all_destaddr,
.get_bbreg = rtl92ee_phy_query_bb_reg,
.set_bbreg = rtl92ee_phy_set_bb_reg,
.get_rfreg = rtl92ee_phy_query_rf_reg,
.set_rfreg = rtl92ee_phy_set_rf_reg,
.fill_h2c_cmd = rtl92ee_fill_h2c_cmd,
.get_btc_status = rtl92ee_get_btc_status,
.rx_command_packet = rtl92ee_rx_command_packet,
};
static struct rtl_mod_params rtl92ee_mod_params = {
.sw_crypto = false,
.b_inactiveps = true,
.b_swctrl_lps = false,
.b_fwctrl_lps = true,
.debug = DBG_EMERG,
};
static struct rtl_hal_cfg rtl92ee_hal_cfg = {
.bar_id = 2,
.write_readback = true,
.name = "rtl92ee_pci",
.fw_name = "rtlwifi/rtl8192eefw.bin",
.ops = &rtl8192ee_hal_ops,
.mod_params = &rtl92ee_mod_params,
.maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
.maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
.maps[SYS_CLK] = REG_SYS_CLKR,
.maps[MAC_RCR_AM] = AM,
.maps[MAC_RCR_AB] = AB,
.maps[MAC_RCR_ACRC32] = ACRC32,
.maps[MAC_RCR_ACF] = ACF,
.maps[MAC_RCR_AAP] = AAP,
.maps[MAC_HIMR] = REG_HIMR,
.maps[MAC_HIMRE] = REG_HIMRE,
.maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS,
.maps[EFUSE_TEST] = REG_EFUSE_TEST,
.maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
.maps[EFUSE_CLK] = 0,
.maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
.maps[EFUSE_PWC_EV12V] = PWC_EV12V,
.maps[EFUSE_FEN_ELDR] = FEN_ELDR,
.maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
.maps[EFUSE_ANA8M] = ANA8M,
.maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
.maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
.maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
.maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
.maps[RWCAM] = REG_CAMCMD,
.maps[WCAMI] = REG_CAMWRITE,
.maps[RCAMO] = REG_CAMREAD,
.maps[CAMDBG] = REG_CAMDBG,
.maps[SECR] = REG_SECCFG,
.maps[SEC_CAM_NONE] = CAM_NONE,
.maps[SEC_CAM_WEP40] = CAM_WEP40,
.maps[SEC_CAM_TKIP] = CAM_TKIP,
.maps[SEC_CAM_AES] = CAM_AES,
.maps[SEC_CAM_WEP104] = CAM_WEP104,
.maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
.maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
.maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
.maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
.maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
.maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
/* .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8, */ /*need check*/
.maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
.maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
.maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
.maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
.maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
.maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
.maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
/* .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,*/
/* .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,*/
.maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
.maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
.maps[RTL_IMR_BcnInt] = IMR_BCNDMAINT0,
.maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
.maps[RTL_IMR_RDU] = IMR_RDU,
.maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
.maps[RTL_IMR_BDOK] = IMR_BCNDOK0,
.maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
.maps[RTL_IMR_TBDER] = IMR_TBDER,
.maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
.maps[RTL_IMR_TBDOK] = IMR_TBDOK,
.maps[RTL_IMR_BKDOK] = IMR_BKDOK,
.maps[RTL_IMR_BEDOK] = IMR_BEDOK,
.maps[RTL_IMR_VIDOK] = IMR_VIDOK,
.maps[RTL_IMR_VODOK] = IMR_VODOK,
.maps[RTL_IMR_ROK] = IMR_ROK,
.maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER),
.maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
.maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
.maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
.maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
.maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
.maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
.maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
.maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
.maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
.maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
.maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
.maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,
.maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
.maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
};
static struct pci_device_id rtl92ee_pci_ids[] = {
{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x818B, rtl92ee_hal_cfg)},
{},
};
MODULE_DEVICE_TABLE(pci, rtl92ee_pci_ids);
MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Realtek 8192E 802.11n PCI wireless");
MODULE_FIRMWARE("rtlwifi/rtl8192eefw.bin");
module_param_named(swenc, rtl92ee_mod_params.sw_crypto, bool, 0444);
module_param_named(debug, rtl92ee_mod_params.debug, int, 0444);
module_param_named(ips, rtl92ee_mod_params.b_inactiveps, bool, 0444);
module_param_named(swlps, rtl92ee_mod_params.b_swctrl_lps, bool, 0444);
module_param_named(fwlps, rtl92ee_mod_params.b_fwctrl_lps, bool, 0444);
MODULE_PARM_DESC(swenc, "using hardware crypto (default 0 [hardware])\n");
MODULE_PARM_DESC(ips, "using no link power save (default 1 is open)\n");
MODULE_PARM_DESC(fwlps, "using linked fw control power save (default 1 is open)\n");
MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, stg_rtl_pci_suspend,
stg_rtl_pci_resume);
static struct pci_driver rtl92ee_driver = {
.name = KBUILD_MODNAME,
.id_table = rtl92ee_pci_ids,
.probe = stg_rtl_pci_probe,
.remove = stg_rtl_pci_disconnect,
.driver.pm = &rtlwifi_pm_ops,
};
static int __init rtl92ee_module_init(void)
{
int ret;
ret = rtl_core_module_init();
if (ret)
return ret;
ret = pci_register_driver(&rtl92ee_driver);
if (ret)
RT_ASSERT(false, (": No device found\n"));
return ret;
}
static void __exit rtl92ee_module_exit(void)
{
pci_unregister_driver(&rtl92ee_driver);
rtl_core_module_exit();
}
module_init(rtl92ee_module_init);
module_exit(rtl92ee_module_exit);

39
drivers/staging/rtl8192ee/rtl8192ee/sw.h
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@ -1,39 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL92E_SW_H__
#define __RTL92E_SW_H__
int rtl92ee_init_sw_vars(struct ieee80211_hw *hw);
void rtl92ee_deinit_sw_vars(struct ieee80211_hw *hw);
bool rtl92ee_get_btc_status(void);
int rtl_core_module_init(void);
void rtl_core_module_exit(void);
#endif

882
drivers/staging/rtl8192ee/rtl8192ee/table.c
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@ -1,882 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Created on 2010/ 5/18, 1:41
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "table.h"
u32 RTL8192EE_PHY_REG_ARRAY[] = {
0x800, 0x80040000,
0x804, 0x00000003,
0x808, 0x0000FC00,
0x80C, 0x0000000A,
0x810, 0x10001331,
0x814, 0x020C3D10,
0x818, 0x02220385,
0x81C, 0x00000000,
0x820, 0x01000100,
0x824, 0x00390204,
0x828, 0x01000100,
0x82C, 0x00390204,
0x830, 0x32323232,
0x834, 0x30303030,
0x838, 0x30303030,
0x83C, 0x30303030,
0x840, 0x00010000,
0x844, 0x00010000,
0x848, 0x28282828,
0x84C, 0x28282828,
0x850, 0x00000000,
0x854, 0x00000000,
0x858, 0x009A009A,
0x85C, 0x01000014,
0x860, 0x66F60000,
0x864, 0x061F0000,
0x868, 0x30303030,
0x86C, 0x30303030,
0x870, 0x00000000,
0x874, 0x55004200,
0x878, 0x08080808,
0x87C, 0x00000000,
0x880, 0xB0000C1C,
0x884, 0x00000001,
0x888, 0x00000000,
0x88C, 0xCC0000C0,
0x890, 0x00000800,
0x894, 0xFFFFFFFE,
0x898, 0x40302010,
0x900, 0x00000000,
0x904, 0x00000023,
0x908, 0x00000000,
0x90C, 0x81121313,
0x910, 0x806C0001,
0x914, 0x00000001,
0x918, 0x00000000,
0x91C, 0x00010000,
0x924, 0x00000001,
0x928, 0x00000000,
0x92C, 0x00000000,
0x930, 0x00000000,
0x934, 0x00000000,
0x938, 0x00000000,
0x93C, 0x00000000,
0x940, 0x00000000,
0x944, 0x00000000,
0x94C, 0x00000008,
0xA00, 0x00D0C7C8,
0xA04, 0x81FF000C,
0xA08, 0x8C838300,
0xA0C, 0x2E68120F,
0xA10, 0x95009B78,
0xA14, 0x1114D028,
0xA18, 0x00881117,
0xA1C, 0x89140F00,
0xA20, 0x1A1B0000,
0xA24, 0x090E1317,
0xA28, 0x00000204,
0xA2C, 0x00D30000,
0xA70, 0x101FBF00,
0xA74, 0x00000007,
0xA78, 0x00000900,
0xA7C, 0x225B0606,
0xA80, 0x218075B1,
0xB38, 0x00000000,
0xC00, 0x48071D40,
0xC04, 0x03A05633,
0xC08, 0x000000E4,
0xC0C, 0x6C6C6C6C,
0xC10, 0x08800000,
0xC14, 0x40000100,
0xC18, 0x08800000,
0xC1C, 0x40000100,
0xC20, 0x00000000,
0xC24, 0x00000000,
0xC28, 0x00000000,
0xC2C, 0x00000000,
0xC30, 0x69E9AC47,
0xC34, 0x469652AF,
0xC38, 0x49795994,
0xC3C, 0x0A97971C,
0xC40, 0x1F7C403F,
0xC44, 0x000100B7,
0xC48, 0xEC020107,
0xC4C, 0x007F037F,
0xFF010718, 0xABCD,
0xC50, 0x00340220,
0xCDCDCDCD, 0xCDCD,
0xC50, 0x00340020,
0xFF010718, 0xDEAD,
0xC54, 0x0080801F,
0xFF010718, 0xABCD,
0xC58, 0x00000220,
0xCDCDCDCD, 0xCDCD,
0xC58, 0x00000020,
0xFF010718, 0xDEAD,
0xC5C, 0x00248492,
0xC60, 0x00000000,
0xC64, 0x7112848B,
0xC68, 0x47C00BFF,
0xC6C, 0x00000036,
0xC70, 0x00000600,
0xC74, 0x02013169,
0xC78, 0x0000001F,
0xC7C, 0x00B91612,
0xFF010718, 0xABCD,
0xC80, 0x2D4000B5,
0xCDCDCDCD, 0xCDCD,
0xC80, 0x40000100,
0xFF010718, 0xDEAD,
0xC84, 0x21F60000,
0xFF010718, 0xABCD,
0xC88, 0x2D4000B5,
0xCDCDCDCD, 0xCDCD,
0xC88, 0x40000100,
0xFF010718, 0xDEAD,
0xC8C, 0xA0E40000,
0xC90, 0x00121820,
0xC94, 0x00000000,
0xC98, 0x00121820,
0xC9C, 0x00007F7F,
0xCA0, 0x00000000,
0xCA4, 0x000300A0,
0xCA8, 0x00000000,
0xCAC, 0x00000000,
0xCB0, 0x00000000,
0xCB4, 0x00000000,
0xCB8, 0x00000000,
0xCBC, 0x28000000,
0xCC0, 0x00000000,
0xCC4, 0x00000000,
0xCC8, 0x00000000,
0xCCC, 0x00000000,
0xCD0, 0x00000000,
0xCD4, 0x00000000,
0xCD8, 0x64B22427,
0xCDC, 0x00766932,
0xCE0, 0x00222222,
0xCE4, 0x00040000,
0xCE8, 0x77644302,
0xCEC, 0x2F97D40C,
0xD00, 0x00080740,
0xD04, 0x00020403,
0xD08, 0x0000907F,
0xD0C, 0x20010201,
0xD10, 0xA0633333,
0xD14, 0x3333BC43,
0xD18, 0x7A8F5B6B,
0xD1C, 0x0000007F,
0xD2C, 0xCC979975,
0xD30, 0x00000000,
0xD34, 0x80608000,
0xD38, 0x00000000,
0xD3C, 0x00127353,
0xD40, 0x00000000,
0xD44, 0x00000000,
0xD48, 0x00000000,
0xD4C, 0x00000000,
0xD50, 0x6437140A,
0xD54, 0x00000000,
0xD58, 0x00000282,
0xD5C, 0x30032064,
0xD60, 0x4653DE68,
0xD64, 0x04518A3C,
0xD68, 0x00002101,
0xD6C, 0x2A201C16,
0xD70, 0x1812362E,
0xD74, 0x322C2220,
0xD78, 0x000E3C24,
0xD80, 0x01081008,
0xD84, 0x00000800,
0xD88, 0xF0B50000,
0xE00, 0x30303030,
0xE04, 0x30303030,
0xE08, 0x03903030,
0xE10, 0x30303030,
0xE14, 0x30303030,
0xE18, 0x30303030,
0xE1C, 0x30303030,
0xE28, 0x00000000,
0xE30, 0x1000DC1F,
0xE34, 0x10008C1F,
0xE38, 0x02140102,
0xE3C, 0x681604C2,
0xE40, 0x01007C00,
0xE44, 0x01004800,
0xE48, 0xFB000000,
0xE4C, 0x000028D1,
0xE50, 0x1000DC1F,
0xE54, 0x10008C1F,
0xE58, 0x02140102,
0xE5C, 0x28160D05,
0xE60, 0x00000008,
0xE68, 0x0FC05656,
0xE6C, 0x03C09696,
0xE70, 0x03C09696,
0xE74, 0x0C005656,
0xE78, 0x0C005656,
0xE7C, 0x0C005656,
0xE80, 0x0C005656,
0xE84, 0x03C09696,
0xE88, 0x0C005656,
0xE8C, 0x03C09696,
0xED0, 0x03C09696,
0xED4, 0x03C09696,
0xED8, 0x03C09696,
0xEDC, 0x0000D6D6,
0xEE0, 0x0000D6D6,
0xEEC, 0x0FC01616,
0xEE4, 0xB0000C1C,
0xEE8, 0x00000001,
0xF14, 0x00000003,
0xF4C, 0x00000000,
0xF00, 0x00000300,
};
u32 RTL8192EE_PHY_REG_ARRAY_PG[] = {
0, 0, 0, 0x00000e08, 0x0000ff00, 0x00003200,
0, 0, 1, 0x00000e08, 0x0000ff00, 0x00003200,
0, 0, 0, 0x0000086c, 0xffffff00, 0x32323200,
0, 0, 1, 0x0000086c, 0xffffff00, 0x32323200,
0, 0, 0, 0x00000e00, 0xffffffff, 0x34343636,
0, 0, 1, 0x00000e00, 0xffffffff, 0x34343636,
0, 0, 0, 0x00000e04, 0xffffffff, 0x28283032,
0, 0, 1, 0x00000e04, 0xffffffff, 0x28283032,
0, 0, 0, 0x00000e10, 0xffffffff, 0x34363840,
0, 0, 1, 0x00000e10, 0xffffffff, 0x34363840,
0, 0, 0, 0x00000e14, 0xffffffff, 0x26283032,
0, 0, 1, 0x00000e14, 0xffffffff, 0x26283032,
0, 0, 1, 0x00000e18, 0xffffffff, 0x36384040,
0, 0, 1, 0x00000e1c, 0xffffffff, 0x24262832,
0, 1, 0, 0x00000838, 0xffffff00, 0x32323200,
0, 1, 1, 0x00000838, 0xffffff00, 0x32323200,
0, 1, 0, 0x0000086c, 0x000000ff, 0x00000032,
0, 1, 1, 0x0000086c, 0x000000ff, 0x00000032,
0, 1, 0, 0x00000830, 0xffffffff, 0x34343636,
0, 1, 1, 0x00000830, 0xffffffff, 0x34343636,
0, 1, 0, 0x00000834, 0xffffffff, 0x28283032,
0, 1, 1, 0x00000834, 0xffffffff, 0x28283032,
0, 1, 0, 0x0000083c, 0xffffffff, 0x34363840,
0, 1, 1, 0x0000083c, 0xffffffff, 0x34363840,
0, 1, 0, 0x00000848, 0xffffffff, 0x26283032,
0, 1, 1, 0x00000848, 0xffffffff, 0x26283032,
0, 1, 1, 0x0000084c, 0xffffffff, 0x36384040,
0, 1, 1, 0x00000868, 0xffffffff, 0x24262832
};
u32 RTL8192EE_RADIOA_ARRAY[] = {
0x07F, 0x00000082,
0x081, 0x0003FC00,
0x000, 0x00030000,
0x008, 0x00008400,
0x018, 0x00000407,
0x019, 0x00000012,
0x01B, 0x00000064,
0x01E, 0x00080009,
0x01F, 0x00000880,
0x02F, 0x0001A060,
0x03F, 0x00000000,
0x042, 0x000060C0,
0x057, 0x000D0000,
0x058, 0x000BE180,
0x067, 0x00001552,
0x083, 0x00000000,
0x0B0, 0x000FF9F1,
0x0B1, 0x00055418,
0x0B2, 0x0008CC00,
0x0B4, 0x00043083,
0x0B5, 0x00008166,
0x0B6, 0x0000803E,
0x0B7, 0x0001C69F,
0x0B8, 0x0000407F,
0x0B9, 0x00080001,
0x0BA, 0x00040001,
0x0BB, 0x00000400,
0x0BF, 0x000C0000,
0x0C2, 0x00002400,
0x0C3, 0x00000009,
0x0C4, 0x00040C91,
0x0C5, 0x00099999,
0x0C6, 0x000000A3,
0x0C7, 0x00088820,
0x0C8, 0x00076C06,
0x0C9, 0x00000000,
0x0CA, 0x00080000,
0x0DF, 0x00000180,
0x0EF, 0x000001A0,
0x051, 0x00069545,
0x052, 0x0007E45E,
0x053, 0x00000071,
0x056, 0x00051FF3,
0x035, 0x000000A8,
0x035, 0x000001E2,
0x035, 0x000002A8,
0x036, 0x00001C24,
0x036, 0x00009C24,
0x036, 0x00011C24,
0x036, 0x00019C24,
0x018, 0x00000C07,
0x05A, 0x00048000,
0x019, 0x000739D0,
0xFF010718, 0xABCD,
0x034, 0x0000A093,
0x034, 0x0000908F,
0x034, 0x0000808C,
0x034, 0x0000704D,
0x034, 0x0000604A,
0x034, 0x00005047,
0x034, 0x0000400A,
0x034, 0x00003007,
0x034, 0x00002004,
0x034, 0x00001001,
0x034, 0x00000000,
0xCDCDCDCD, 0xCDCD,
0x034, 0x0000ADD7,
0x034, 0x00009DD4,
0x034, 0x00008DD1,
0x034, 0x00007DCE,
0x034, 0x00006DCB,
0x034, 0x00005DC8,
0x034, 0x00004DC5,
0x034, 0x000034CC,
0x034, 0x0000244F,
0x034, 0x0000144C,
0x034, 0x00000014,
0xFF010718, 0xDEAD,
0x000, 0x00030159,
0x084, 0x00068180,
0x086, 0x0000014E,
0x087, 0x00048E00,
0x08E, 0x00065540,
0x08F, 0x00088000,
0x0EF, 0x000020A0,
0xFF010718, 0xABCD,
0x03B, 0x000F07B0,
0xCDCDCDCD, 0xCDCD,
0x03B, 0x000F02B0,
0xFF010718, 0xDEAD,
0x03B, 0x000EF7B0,
0x03B, 0x000D4FB0,
0x03B, 0x000CF060,
0x03B, 0x000B0090,
0x03B, 0x000A0080,
0x03B, 0x00090080,
0x03B, 0x0008F780,
0xFF010718, 0xABCD,
0x03B, 0x000787B0,
0xCDCDCDCD, 0xCDCD,
0x03B, 0x00078730,
0xFF010718, 0xDEAD,
0x03B, 0x00060FB0,
0x03B, 0x0005FFA0,
0x03B, 0x00040620,
0x03B, 0x00037090,
0x03B, 0x00020080,
0x03B, 0x0001F060,
0x03B, 0x0000FFB0,
0x0EF, 0x000000A0,
0x0FE, 0x00000000,
0x018, 0x0000FC07,
0x0FE, 0x00000000,
0x0FE, 0x00000000,
0x0FE, 0x00000000,
0x0FE, 0x00000000,
0x01E, 0x00000001,
0x01F, 0x00080000,
0x000, 0x00033E70,
};
u32 RTL8192EE_RADIOB_ARRAY[] = {
0x07F, 0x00000082,
0x081, 0x0003FC00,
0x000, 0x00030000,
0x008, 0x00008400,
0x018, 0x00000407,
0x019, 0x00000012,
0x01B, 0x00000064,
0x01E, 0x00080009,
0x01F, 0x00000880,
0x02F, 0x0001A060,
0x03F, 0x00000000,
0x042, 0x000060C0,
0x057, 0x000D0000,
0x058, 0x000BE180,
0x067, 0x00001552,
0x07F, 0x00000082,
0x081, 0x0003F000,
0x083, 0x00000000,
0x0DF, 0x00000180,
0x0EF, 0x000001A0,
0x051, 0x00069545,
0x052, 0x0007E42E,
0x053, 0x00000071,
0x056, 0x00051FF3,
0x035, 0x000000A8,
0x035, 0x000001E0,
0x035, 0x000002A8,
0x036, 0x00001CA8,
0x036, 0x00009C24,
0x036, 0x00011C24,
0x036, 0x00019C24,
0x018, 0x00000C07,
0x05A, 0x00048000,
0x019, 0x000739D0,
0xFF010718, 0xABCD,
0x034, 0x0000A093,
0x034, 0x0000908F,
0x034, 0x0000808C,
0x034, 0x0000704D,
0x034, 0x0000604A,
0x034, 0x00005047,
0x034, 0x0000400A,
0x034, 0x00003007,
0x034, 0x00002004,
0x034, 0x00001001,
0x034, 0x00000000,
0xCDCDCDCD, 0xCDCD,
0x034, 0x0000ADD7,
0x034, 0x00009DD4,
0x034, 0x00008DD1,
0x034, 0x00007DCE,
0x034, 0x00006DCB,
0x034, 0x00005DC8,
0x034, 0x00004DC5,
0x034, 0x000034CC,
0x034, 0x0000244F,
0x034, 0x0000144C,
0x034, 0x00000014,
0xFF010718, 0xDEAD,
0x000, 0x00030159,
0x084, 0x00068180,
0x086, 0x000000CE,
0x087, 0x00048A00,
0x08E, 0x00065540,
0x08F, 0x00088000,
0x0EF, 0x000020A0,
0xFF010718, 0xABCD,
0x03B, 0x000F07B0,
0xCDCDCDCD, 0xCDCD,
0x03B, 0x000F02B0,
0xFF010718, 0xDEAD,
0x03B, 0x000EF7B0,
0x03B, 0x000D4FB0,
0x03B, 0x000CF060,
0x03B, 0x000B0090,
0x03B, 0x000A0080,
0x03B, 0x00090080,
0x03B, 0x0008F780,
0xFF010718, 0xABCD,
0x03B, 0x000787B0,
0xCDCDCDCD, 0xCDCD,
0x03B, 0x00078730,
0xFF010718, 0xDEAD,
0x03B, 0x00060FB0,
0x03B, 0x0005FFA0,
0x03B, 0x00040620,
0x03B, 0x00037090,
0x03B, 0x00020080,
0x03B, 0x0001F060,
0x03B, 0x0000FFB0,
0x0EF, 0x000000A0,
0x000, 0x00010159,
0x0FE, 0x00000000,
0x0FE, 0x00000000,
0x0FE, 0x00000000,
0x0FE, 0x00000000,
0x01E, 0x00000001,
0x01F, 0x00080000,
0x000, 0x00033E70,
};
u32 RTL8192EE_MAC_ARRAY[] = {
0x011, 0x000000EB,
0x012, 0x00000007,
0x014, 0x00000075,
0x303, 0x000000A7,
0x428, 0x0000000A,
0x429, 0x00000010,
0x430, 0x00000000,
0x431, 0x00000000,
0x432, 0x00000000,
0x433, 0x00000001,
0x434, 0x00000004,
0x435, 0x00000005,
0x436, 0x00000007,
0x437, 0x00000008,
0x43C, 0x00000004,
0x43D, 0x00000005,
0x43E, 0x00000007,
0x43F, 0x00000008,
0x440, 0x0000005D,
0x441, 0x00000001,
0x442, 0x00000000,
0x444, 0x00000010,
0x445, 0x00000000,
0x446, 0x00000000,
0x447, 0x00000000,
0x448, 0x00000000,
0x449, 0x000000F0,
0x44A, 0x0000000F,
0x44B, 0x0000003E,
0x44C, 0x00000010,
0x44D, 0x00000000,
0x44E, 0x00000000,
0x44F, 0x00000000,
0x450, 0x00000000,
0x451, 0x000000F0,
0x452, 0x0000000F,
0x453, 0x00000000,
0x456, 0x0000005E,
0x460, 0x00000066,
0x461, 0x00000066,
0x4C8, 0x000000FF,
0x4C9, 0x00000008,
0x4CC, 0x000000FF,
0x4CD, 0x000000FF,
0x4CE, 0x00000001,
0x500, 0x00000026,
0x501, 0x000000A2,
0x502, 0x0000002F,
0x503, 0x00000000,
0x504, 0x00000028,
0x505, 0x000000A3,
0x506, 0x0000005E,
0x507, 0x00000000,
0x508, 0x0000002B,
0x509, 0x000000A4,
0x50A, 0x0000005E,
0x50B, 0x00000000,
0x50C, 0x0000004F,
0x50D, 0x000000A4,
0x50E, 0x00000000,
0x50F, 0x00000000,
0x512, 0x0000001C,
0x514, 0x0000000A,
0x516, 0x0000000A,
0x525, 0x0000004F,
0x540, 0x00000012,
0x541, 0x00000064,
0x550, 0x00000010,
0x551, 0x00000010,
0x559, 0x00000002,
0x55C, 0x00000050,
0x55D, 0x000000FF,
0x605, 0x00000030,
0x608, 0x0000000E,
0x609, 0x0000002A,
0x620, 0x000000FF,
0x621, 0x000000FF,
0x622, 0x000000FF,
0x623, 0x000000FF,
0x624, 0x000000FF,
0x625, 0x000000FF,
0x626, 0x000000FF,
0x627, 0x000000FF,
0x638, 0x00000050,
0x63C, 0x0000000A,
0x63D, 0x0000000A,
0x63E, 0x0000000E,
0x63F, 0x0000000E,
0x640, 0x00000040,
0x642, 0x00000040,
0x643, 0x00000000,
0x652, 0x000000C8,
0x66E, 0x00000005,
0x700, 0x00000021,
0x701, 0x00000043,
0x702, 0x00000065,
0x703, 0x00000087,
0x708, 0x00000021,
0x709, 0x00000043,
0x70A, 0x00000065,
0x70B, 0x00000087,
};
u32 RTL8192EE_AGC_TAB_ARRAY[] = {
0xFF010718, 0xABCD,
0xC78, 0xFA000001,
0xC78, 0xF9010001,
0xC78, 0xF8020001,
0xC78, 0xF7030001,
0xC78, 0xF6040001,
0xC78, 0xF5050001,
0xC78, 0xF4060001,
0xC78, 0xF3070001,
0xC78, 0xF2080001,
0xC78, 0xF1090001,
0xC78, 0xF00A0001,
0xC78, 0xEF0B0001,
0xC78, 0xEE0C0001,
0xC78, 0xED0D0001,
0xC78, 0xEC0E0001,
0xC78, 0xEB0F0001,
0xC78, 0xEA100001,
0xC78, 0xE9110001,
0xC78, 0xE8120001,
0xC78, 0xE7130001,
0xC78, 0xE6140001,
0xC78, 0xE5150001,
0xC78, 0xE4160001,
0xC78, 0xE3170001,
0xC78, 0xE2180001,
0xC78, 0xE1190001,
0xC78, 0x8A1A0001,
0xC78, 0x891B0001,
0xC78, 0x881C0001,
0xC78, 0x871D0001,
0xC78, 0x861E0001,
0xC78, 0x851F0001,
0xC78, 0x84200001,
0xC78, 0x83210001,
0xC78, 0x82220001,
0xC78, 0x6A230001,
0xC78, 0x69240001,
0xC78, 0x68250001,
0xC78, 0x67260001,
0xC78, 0x66270001,
0xC78, 0x65280001,
0xC78, 0x64290001,
0xC78, 0x632A0001,
0xC78, 0x622B0001,
0xC78, 0x612C0001,
0xC78, 0x602D0001,
0xC78, 0x472E0001,
0xC78, 0x462F0001,
0xC78, 0x45300001,
0xC78, 0x44310001,
0xC78, 0x43320001,
0xC78, 0x42330001,
0xC78, 0x41340001,
0xC78, 0x40350001,
0xC78, 0x40360001,
0xC78, 0x40370001,
0xC78, 0x40380001,
0xC78, 0x40390001,
0xC78, 0x403A0001,
0xC78, 0x403B0001,
0xC78, 0x403C0001,
0xC78, 0x403D0001,
0xC78, 0x403E0001,
0xC78, 0x403F0001,
0xCDCDCDCD, 0xCDCD,
0xC78, 0xFB000001,
0xC78, 0xFB010001,
0xC78, 0xFB020001,
0xC78, 0xFB030001,
0xC78, 0xFB040001,
0xC78, 0xFB050001,
0xC78, 0xFA060001,
0xC78, 0xF9070001,
0xC78, 0xF8080001,
0xC78, 0xF7090001,
0xC78, 0xF60A0001,
0xC78, 0xF50B0001,
0xC78, 0xF40C0001,
0xC78, 0xF30D0001,
0xC78, 0xF20E0001,
0xC78, 0xF10F0001,
0xC78, 0xF0100001,
0xC78, 0xEF110001,
0xC78, 0xEE120001,
0xC78, 0xED130001,
0xC78, 0xEC140001,
0xC78, 0xEB150001,
0xC78, 0xEA160001,
0xC78, 0xE9170001,
0xC78, 0xE8180001,
0xC78, 0xE7190001,
0xC78, 0xC81A0001,
0xC78, 0xC71B0001,
0xC78, 0xC61C0001,
0xC78, 0x071D0001,
0xC78, 0x061E0001,
0xC78, 0x051F0001,
0xC78, 0x04200001,
0xC78, 0x03210001,
0xC78, 0xAA220001,
0xC78, 0xA9230001,
0xC78, 0xA8240001,
0xC78, 0xA7250001,
0xC78, 0xA6260001,
0xC78, 0x85270001,
0xC78, 0x84280001,
0xC78, 0x83290001,
0xC78, 0x252A0001,
0xC78, 0x242B0001,
0xC78, 0x232C0001,
0xC78, 0x222D0001,
0xC78, 0x672E0001,
0xC78, 0x662F0001,
0xC78, 0x65300001,
0xC78, 0x64310001,
0xC78, 0x63320001,
0xC78, 0x62330001,
0xC78, 0x61340001,
0xC78, 0x45350001,
0xC78, 0x44360001,
0xC78, 0x43370001,
0xC78, 0x42380001,
0xC78, 0x41390001,
0xC78, 0x403A0001,
0xC78, 0x403B0001,
0xC78, 0x403C0001,
0xC78, 0x403D0001,
0xC78, 0x403E0001,
0xC78, 0x403F0001,
0xFF010718, 0xDEAD,
0xFF010718, 0xABCD,
0xC78, 0xFA400001,
0xC78, 0xF9410001,
0xC78, 0xF8420001,
0xC78, 0xF7430001,
0xC78, 0xF6440001,
0xC78, 0xF5450001,
0xC78, 0xF4460001,
0xC78, 0xF3470001,
0xC78, 0xF2480001,
0xC78, 0xF1490001,
0xC78, 0xF04A0001,
0xC78, 0xEF4B0001,
0xC78, 0xEE4C0001,
0xC78, 0xED4D0001,
0xC78, 0xEC4E0001,
0xC78, 0xEB4F0001,
0xC78, 0xEA500001,
0xC78, 0xE9510001,
0xC78, 0xE8520001,
0xC78, 0xE7530001,
0xC78, 0xE6540001,
0xC78, 0xE5550001,
0xC78, 0xE4560001,
0xC78, 0xE3570001,
0xC78, 0xE2580001,
0xC78, 0xE1590001,
0xC78, 0x8A5A0001,
0xC78, 0x895B0001,
0xC78, 0x885C0001,
0xC78, 0x875D0001,
0xC78, 0x865E0001,
0xC78, 0x855F0001,
0xC78, 0x84600001,
0xC78, 0x83610001,
0xC78, 0x82620001,
0xC78, 0x6A630001,
0xC78, 0x69640001,
0xC78, 0x68650001,
0xC78, 0x67660001,
0xC78, 0x66670001,
0xC78, 0x65680001,
0xC78, 0x64690001,
0xC78, 0x636A0001,
0xC78, 0x626B0001,
0xC78, 0x616C0001,
0xC78, 0x606D0001,
0xC78, 0x476E0001,
0xC78, 0x466F0001,
0xC78, 0x45700001,
0xC78, 0x44710001,
0xC78, 0x43720001,
0xC78, 0x42730001,
0xC78, 0x41740001,
0xC78, 0x40750001,
0xC78, 0x40760001,
0xC78, 0x40770001,
0xC78, 0x40780001,
0xC78, 0x40790001,
0xC78, 0x407A0001,
0xC78, 0x407B0001,
0xC78, 0x407C0001,
0xC78, 0x407D0001,
0xC78, 0x407E0001,
0xC78, 0x407F0001,
0xC50, 0x00040222,
0xC50, 0x00040220,
0xCDCDCDCD, 0xCDCD,
0xC78, 0xFB400001,
0xC78, 0xFB410001,
0xC78, 0xFB420001,
0xC78, 0xFB430001,
0xC78, 0xFB440001,
0xC78, 0xFB450001,
0xC78, 0xFA460001,
0xC78, 0xF9470001,
0xC78, 0xF8480001,
0xC78, 0xF7490001,
0xC78, 0xF64A0001,
0xC78, 0xF54B0001,
0xC78, 0xF44C0001,
0xC78, 0xF34D0001,
0xC78, 0xF24E0001,
0xC78, 0xF14F0001,
0xC78, 0xF0500001,
0xC78, 0xEF510001,
0xC78, 0xEE520001,
0xC78, 0xED530001,
0xC78, 0xEC540001,
0xC78, 0xEB550001,
0xC78, 0xEA560001,
0xC78, 0xE9570001,
0xC78, 0xE8580001,
0xC78, 0xE7590001,
0xC78, 0xE65A0001,
0xC78, 0xE55B0001,
0xC78, 0xE45C0001,
0xC78, 0xE35D0001,
0xC78, 0xE25E0001,
0xC78, 0xE15F0001,
0xC78, 0x8A600001,
0xC78, 0x89610001,
0xC78, 0x88620001,
0xC78, 0x87630001,
0xC78, 0x86640001,
0xC78, 0x85650001,
0xC78, 0x84660001,
0xC78, 0x83670001,
0xC78, 0x82680001,
0xC78, 0x6B690001,
0xC78, 0x6A6A0001,
0xC78, 0x696B0001,
0xC78, 0x686C0001,
0xC78, 0x676D0001,
0xC78, 0x666E0001,
0xC78, 0x656F0001,
0xC78, 0x64700001,
0xC78, 0x63710001,
0xC78, 0x62720001,
0xC78, 0x61730001,
0xC78, 0x49740001,
0xC78, 0x48750001,
0xC78, 0x47760001,
0xC78, 0x46770001,
0xC78, 0x45780001,
0xC78, 0x44790001,
0xC78, 0x437A0001,
0xC78, 0x427B0001,
0xC78, 0x417C0001,
0xC78, 0x407D0001,
0xC78, 0x407E0001,
0xC78, 0x407F0001,
0xC50, 0x00040022,
0xC50, 0x00040020,
0xFF010718, 0xDEAD,
};

48
drivers/staging/rtl8192ee/rtl8192ee/table.h
View File

@ -1,48 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Created on 2010/ 5/18, 1:41
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL92E_TABLE__H_
#define __RTL92E_TABLE__H_
#include <linux/types.h>
#define RTL8192EE_PHY_REG_ARRAY_LEN 448
extern u32 RTL8192EE_PHY_REG_ARRAY[];
#define RTL8192EE_PHY_REG_ARRAY_PG_LEN 168
extern u32 RTL8192EE_PHY_REG_ARRAY_PG[];
#define RTL8192EE_RADIOA_ARRAY_LEN 238
extern u32 RTL8192EE_RADIOA_ARRAY[];
#define RTL8192EE_RADIOB_ARRAY_LEN 198
extern u32 RTL8192EE_RADIOB_ARRAY[];
#define RTL8192EE_MAC_ARRAY_LEN 202
extern u32 RTL8192EE_MAC_ARRAY[];
#define RTL8192EE_AGC_TAB_ARRAY_LEN 532
extern u32 RTL8192EE_AGC_TAB_ARRAY[];
#endif

1284
drivers/staging/rtl8192ee/rtl8192ee/trx.c
View File

File diff suppressed because it is too large Load Diff

877
drivers/staging/rtl8192ee/rtl8192ee/trx.h
View File

@ -1,877 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL92E_TRX_H__
#define __RTL92E_TRX_H__
#if (DMA_IS_64BIT == 1)
#if (RTL8192EE_SEG_NUM == 2)
#define TX_BD_DESC_SIZE 128
#elif (RTL8192EE_SEG_NUM == 1)
#define TX_BD_DESC_SIZE 64
#elif (RTL8192EE_SEG_NUM == 0)
#define TX_BD_DESC_SIZE 32
#endif
#else
#if (RTL8192EE_SEG_NUM == 2)
#define TX_BD_DESC_SIZE 64
#elif (RTL8192EE_SEG_NUM == 1)
#define TX_BD_DESC_SIZE 32
#elif (RTL8192EE_SEG_NUM == 0)
#define TX_BD_DESC_SIZE 16
#endif
#endif
#define TX_DESC_SIZE 64
#define RX_DRV_INFO_SIZE_UNIT 8
#define TX_DESC_NEXT_DESC_OFFSET 40
#define USB_HWDESC_HEADER_LEN 40
#define RX_DESC_SIZE 24
#define MAX_RECEIVE_BUFFER_SIZE 8192
#define SET_TX_DESC_PKT_SIZE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 0, 16, __val)
#define SET_TX_DESC_OFFSET(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 16, 8, __val)
#define SET_TX_DESC_BMC(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 24, 1, __val)
#define SET_TX_DESC_HTC(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 25, 1, __val)
#define SET_TX_DESC_LAST_SEG(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 26, 1, __val)
#define SET_TX_DESC_FIRST_SEG(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 27, 1, __val)
#define SET_TX_DESC_LINIP(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 28, 1, __val)
#define SET_TX_DESC_NO_ACM(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 29, 1, __val)
#define SET_TX_DESC_GF(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 30, 1, __val)
#define SET_TX_DESC_OWN(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val)
#define GET_TX_DESC_PKT_SIZE(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 0, 16)
#define GET_TX_DESC_OFFSET(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 16, 8)
#define GET_TX_DESC_BMC(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 24, 1)
#define GET_TX_DESC_HTC(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 25, 1)
#define GET_TX_DESC_LAST_SEG(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 26, 1)
#define GET_TX_DESC_FIRST_SEG(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 27, 1)
#define GET_TX_DESC_LINIP(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 28, 1)
#define GET_TX_DESC_NO_ACM(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 29, 1)
#define GET_TX_DESC_GF(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 30, 1)
#define GET_TX_DESC_OWN(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 31, 1)
#define SET_TX_DESC_MACID(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 0, 7, __val)
#define SET_TX_DESC_QUEUE_SEL(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 8, 5, __val)
#define SET_TX_DESC_RDG_NAV_EXT(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 13, 1, __val)
#define SET_TX_DESC_LSIG_TXOP_EN(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 14, 1, __val)
#define SET_TX_DESC_PIFS(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 15, 1, __val)
#define SET_TX_DESC_RATE_ID(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 16, 5, __val)
#define SET_TX_DESC_EN_DESC_ID(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 21, 1, __val)
#define SET_TX_DESC_SEC_TYPE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 22, 2, __val)
#define SET_TX_DESC_PKT_OFFSET(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 24, 5, __val)
#define SET_TX_DESC_MORE_DATA(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 29, 1, __val)
#define SET_TX_DESC_TXOP_PS_CAP(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 30, 1, __val)
#define SET_TX_DESC_TXOP_PS_MODE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 31, 1, __val)
#define GET_TX_DESC_MACID(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 0, 5)
#define GET_TX_DESC_AGG_ENABLE(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 5, 1)
#define GET_TX_DESC_AGG_BREAK(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 6, 1)
#define GET_TX_DESC_RDG_ENABLE(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 7, 1)
#define GET_TX_DESC_QUEUE_SEL(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 8, 5)
#define GET_TX_DESC_RDG_NAV_EXT(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 13, 1)
#define GET_TX_DESC_LSIG_TXOP_EN(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 14, 1)
#define GET_TX_DESC_PIFS(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 15, 1)
#define GET_TX_DESC_RATE_ID(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 16, 4)
#define GET_TX_DESC_NAV_USE_HDR(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 20, 1)
#define GET_TX_DESC_EN_DESC_ID(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 21, 1)
#define GET_TX_DESC_SEC_TYPE(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 22, 2)
#define GET_TX_DESC_PKT_OFFSET(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 24, 5)
#define SET_TX_DESC_PAID(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 0, 9, __val)
#define SET_TX_DESC_CCA_RTS(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 10, 2, __val)
#define SET_TX_DESC_AGG_ENABLE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 12, 1, __val)
#define SET_TX_DESC_RDG_ENABLE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 13, 1, __val)
#define SET_TX_DESC_NULL_0(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 14, 1, __val)
#define SET_TX_DESC_NULL_1(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 15, 1, __val)
#define SET_TX_DESC_BK(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 16, 1, __val)
#define SET_TX_DESC_MORE_FRAG(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 17, 1, __val)
#define SET_TX_DESC_RAW(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 18, 1, __val)
#define SET_TX_DESC_SPE_RPT(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 19, 1, __val)
#define SET_TX_DESC_AMPDU_DENSITY(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 20, 3, __val)
#define SET_TX_DESC_BT_NULL(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 23, 1, __val)
#define SET_TX_DESC_GID(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 24, 6, __val)
#define SET_TX_DESC_WHEADER_LEN(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 0, 4, __val)
#define SET_TX_DESC_CHK_EN(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 4, 1, __val)
#define SET_TX_DESC_EARLY_RATE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 5, 1, __val)
#define SET_TX_DESC_HWSEQ_SEL(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 6, 2, __val)
#define SET_TX_DESC_USE_RATE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 8, 1, __val)
#define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 9, 1, __val)
#define SET_TX_DESC_DISABLE_FB(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 10, 1, __val)
#define SET_TX_DESC_CTS2SELF(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 11, 1, __val)
#define SET_TX_DESC_RTS_ENABLE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 12, 1, __val)
#define SET_TX_DESC_HW_RTS_ENABLE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 13, 1, __val)
#define SET_TX_DESC_HW_PORT_ID(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 14, 1, __val)
#define SET_TX_DESC_NAV_USE_HDR(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 15, 1, __val)
#define SET_TX_DESC_USE_MAX_LEN(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 16, 1, __val)
#define SET_TX_DESC_MAX_AGG_NUM(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 17, 5, __val)
#define SET_TX_DESC_NDPA(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 22, 2, __val)
#define SET_TX_DESC_AMPDU_MAX_TIME(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 24, 8, __val)
/* Dword 4 */
#define SET_TX_DESC_TX_RATE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+16, 0, 7, __val)
#define SET_TX_DESC_TRY_RATE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+16, 7, 1, __val)
#define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+16, 8, 5, __val)
#define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+16, 13, 4, __val)
#define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+16, 17, 1, __val)
#define SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+16, 18, 6, __val)
#define SET_TX_DESC_RTS_RATE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+16, 24, 5, __val)
#define SET_TX_DESC_PCTS_ENABLE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+16, 29, 1, __val)
#define SET_TX_DESC_PCTS_MASK_IDX(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+16, 30, 2, __val)
/* Dword 5 */
#define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+20, 0, 4, __val)
#define SET_TX_DESC_DATA_SHORT(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+20, 4, 1, __val)
#define SET_TX_DESC_DATA_BW(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+20, 5, 2, __val)
#define SET_TX_DESC_DATA_LDPC(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+20, 7, 1, __val)
#define SET_TX_DESC_DATA_STBC(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+20, 8, 2, __val)
#define SET_TX_DESC_VCS_STBC(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+20, 10, 2, __val)
#define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+20, 12, 1, __val)
#define SET_TX_DESC_RTS_SC(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+20, 13, 4, __val)
#define SET_TX_DESC_TX_ANT(__pdesc , __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+20, 24, 4, __val)
#define SET_TX_DESC_TX_POWER_0_PSET(__pdesc , __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+20, 28, 3, __val)
/* Dword 6 */
#define SET_TX_DESC_SW_DEFINE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 12, __val)
#define SET_TX_DESC_ANTSEL_A(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+24, 16, 3, __val)
#define SET_TX_DESC_ANTSEL_B(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+24, 19, 3, __val)
#define SET_TX_DESC_ANTSEL_C(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+24, 22, 3, __val)
#define SET_TX_DESC_ANTSEL_D(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+24, 25, 3, __val)
/* Dword 7 */
#define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+28, 0, 16, __val)
#define SET_TX_DESC_USB_TXAGG_NUM(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+28, 24, 8, __val)
/* Dword 8 */
#define SET_TX_DESC_RTS_RC(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+32 , 0 , 6 , __val)
#define SET_TX_DESC_BAR_RTY_TH(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+32 , 6 , 2 , __val)
#define SET_TX_DESC_DATA_RC(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+32 , 8 , 6 , __val)
#define SET_TX_DESC_ENABLE_HW_SELECT(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+32 , 15 , 1 , __val)
#define SET_TX_DESC_NEXT_HEAD_PAGE(__pdesc , __val)(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+32 , 16 , 8 , __val)
#define SET_TX_DESC_TAIL_PAGE(__pdesc , __val)(__pdesc, __val)\
SET_BITS_TO_LE_4BYTE(__pdesc+32 , 24 , 8 , __val)
/* Dword 9 */
#define SET_TX_DESC_PADDING_LENGTH(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+36 , 0 , 11 , __val)
#define SET_TX_DESC_TXBF_PATH(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+36 , 11 , 1 , __val)
#define SET_TX_DESC_SEQ(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+36 , 12 , 12 , __val)
#define SET_TX_DESC_FINAL_DATA_RATE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+36 , 24 , 8 , __val)
/* Dword 10 */
#define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+40 , 0 , 32 , __val)
/* Dword 11*/
#define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+48 , 0 , 32 , __val)
#define SET_EARLYMODE_PKTNUM(__paddr , __val) \
SET_BITS_TO_LE_4BYTE(__paddr , 0 , 4 , __val)
#define SET_EARLYMODE_LEN0(__paddr , __val) \
SET_BITS_TO_LE_4BYTE(__paddr , 4 , 15 , __val)
#define SET_EARLYMODE_LEN1(__paddr , __val) \
SET_BITS_TO_LE_4BYTE(__paddr , 16 , 2 , __val)
#define SET_EARLYMODE_LEN1_1(__paddr , __val) \
SET_BITS_TO_LE_4BYTE(__paddr , 19 , 13 , __val)
#define SET_EARLYMODE_LEN1_2(__paddr , __val) \
SET_BITS_TO_LE_4BYTE(__paddr+4 , 0 , 2 , __val)
#define SET_EARLYMODE_LEN2(__paddr , __val) \
SET_BITS_TO_LE_4BYTE(__paddr+4 , 2 , 15 , __val)
#define SET_EARLYMODE_LEN2_1(__paddr , __val) \
SET_BITS_TO_LE_4BYTE(__paddr , 2 , 4 , __val)
#define SET_EARLYMODE_LEN2_2(__paddr , __val) \
SET_BITS_TO_LE_4BYTE(__paddr+4 , 0 , 8 , __val)
#define SET_EARLYMODE_LEN3(__paddr , __val) \
SET_BITS_TO_LE_4BYTE(__paddr+4 , 17 , 15, __val)
#define SET_EARLYMODE_LEN4(__paddr , __val) \
SET_BITS_TO_LE_4BYTE(__paddr+4 , 20 , 12 , __val)
/* TX/RX buffer descriptor */
#define SET_TX_EXTBUFF_DESC_LEN(__pdesc, __val, __set) \
SET_BITS_TO_LE_4BYTE(__pdesc+(__set*16) , 0 , 16 , __val)
#define SET_TX_EXTBUFF_DESC_ADDR_LOW(__pdesc, __val, __set)\
SET_BITS_TO_LE_4BYTE(__pdesc+(__set*16)+4 , 0 , 32 , __val)
#define SET_TX_EXTBUFF_DESC_ADDR_HIGH(__pdesc, __val , __set)\
SET_BITS_TO_LE_4BYTE(__pdesc+(__set*16)+8 , 0 , 32 , __val)
/* for Txfilldescroptor92ee, fill the desc content. */
#if (DMA_IS_64BIT == 1)
#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pdesc, __offset, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*16), 0, 16, __val)
#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pdesc, __offset, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*16), 31, 1, __val)
#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pdesc, __offset, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*16)+4, 0, 32, __val)
#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pdesc, __offset, __val)\
SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*16)+8, 0, 32, __val)
#define GET_TXBUFFER_DESC_ADDR_LOW(__pdesc, __offset) \
LE_BITS_TO_4BYTE(__pdesc+(__offset*16)+4, 0, 32)
#else
#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pdesc, __offset, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*8), 0, 16, __val)
#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pdesc, __offset, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*8), 31, 1, __val)
#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pdesc, __offset, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*8)+4, 0, 32, __val)
#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pdesc, __offset, __val)
#define GET_TXBUFFER_DESC_ADDR_LOW(__pdesc, __offset) \
LE_BITS_TO_4BYTE(__pdesc+(__offset*8)+4, 0, 32)
#endif
/* Dword 0 */
#define SET_TX_BUFF_DESC_LEN_0(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 0, 14, __val)
#define SET_TX_BUFF_DESC_PSB(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 16, 15, __val)
#define SET_TX_BUFF_DESC_OWN(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val)
/* Dword 1 */
#define SET_TX_BUFF_DESC_ADDR_LOW_0(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 0, 32, __val)
#if (DMA_IS_64BIT == 1)
/* Dword 2 */
#define SET_TX_BUFF_DESC_ADDR_HIGH_0(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 0, 32, __val)
/* Dword 3 / RESERVED 0 */
/* Dword 4 */
#define SET_TX_BUFF_DESC_LEN_1(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+16, 0, 16, __val)
#define SET_TX_BUFF_DESC_AMSDU_1(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+16, 31, 1, __val)
/* Dword 5 */
#define SET_TX_BUFF_DESC_ADDR_LOW_1(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+20, 0, 32, __val)
/* Dword 6 */
#define SET_TX_BUFF_DESC_ADDR_HIGH_1(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 32, __val)
/* Dword 7 / RESERVED 0 */
/* Dword 8 */
#define SET_TX_BUFF_DESC_LEN_2(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+32, 0, 16, __val)
#define SET_TX_BUFF_DESC_AMSDU_2(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+32, 31, 1, __val)
/* Dword 9 */
#define SET_TX_BUFF_DESC_ADDR_LOW_2(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+36, 0, 32, __val)
/* Dword 10 */
#define SET_TX_BUFF_DESC_ADDR_HIGH_2(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+40, 0, 32, __val)
/* Dword 11 / RESERVED 0 */
/* Dword 12 */
#define SET_TX_BUFF_DESC_LEN_3(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+48, 0, 16, __val)
#define SET_TX_BUFF_DESC_AMSDU_3(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+48, 31, 1, __val)
/* Dword 13 */
#define SET_TX_BUFF_DESC_ADDR_LOW_3(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+52, 0, 32, __val)
/* Dword 14 */
#define SET_TX_BUFF_DESC_ADDR_HIGH_3(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+56, 0, 32, __val)
/* Dword 15 / RESERVED 0 */
#else
#define SET_TX_BUFF_DESC_ADDR_HIGH_0(__pdesc, __val)
/* Dword 2 */
#define SET_TX_BUFF_DESC_LEN_1(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 0, 16, __val)
#define SET_TX_BUFF_DESC_AMSDU_1(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 31, 1, __val)
/* Dword 3 */
#define SET_TX_BUFF_DESC_ADDR_LOW_1(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 0, 32, __val)
#define SET_TX_BUFF_DESC_ADDR_HIGH_1(__pdesc, __val)
/* Dword 4 */
#define SET_TX_BUFF_DESC_LEN_2(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+16, 0, 16, __val)
#define SET_TX_BUFF_DESC_AMSDU_2(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+16, 31, 1, __val)
/* Dword 5 */
#define SET_TX_BUFF_DESC_ADDR_LOW_2(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+20, 0, 32, __val)
#define SET_TX_BUFF_DESC_ADDR_HIGH_2(__pdesc, __val)
/* Dword 6 */
#define SET_TX_BUFF_DESC_LEN_3(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 16, __val)
#define SET_TX_BUFF_DESC_AMSDU_3(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+24, 31, 1, __val)
/* Dword 7 */
#define SET_TX_BUFF_DESC_ADDR_LOW_3(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+28, 0, 32, __val)
#define SET_TX_BUFF_DESC_ADDR_HIGH_3(__pdesc, __val)
#endif
/* RX buffer */
/* DWORD 0 */
#define SET_RX_BUFFER_DESC_DATA_LENGTH(__pRxStatusDesc , __val) \
SET_BITS_TO_LE_4BYTE(__pRxStatusDesc , 0, 14, __val)
#define SET_RX_BUFFER_DESC_LS(__pRxStatusDesc , __val) \
SET_BITS_TO_LE_4BYTE(__pRxStatusDesc , 15, 1, __val)
#define SET_RX_BUFFER_DESC_FS(__pRxStatusDesc , __val) \
SET_BITS_TO_LE_4BYTE(__pRxStatusDesc , 16, 1, __val)
#define SET_RX_BUFFER_DESC_TOTAL_LENGTH(__pRxStatusDesc , __val) \
SET_BITS_TO_LE_4BYTE(__pRxStatusDesc , 16, 15, __val)
#define GET_RX_BUFFER_DESC_OWN(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc , 31, 1)
#define GET_RX_BUFFER_DESC_LS(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc , 15, 1)
#define GET_RX_BUFFER_DESC_FS(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc , 16, 1)
#define GET_RX_BUFFER_DESC_TOTAL_LENGTH(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc , 16, 15)
/* DWORD 1 */
#define SET_RX_BUFFER_PHYSICAL_LOW(__pRxStatusDesc , __val) \
SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+4, 0, 32, __val)
/* DWORD 2 */
#define SET_RX_BUFFER_PHYSICAL_HIGH(__pRxStatusDesc , __val) \
SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+8, 0, 32, __val)
#define GET_RX_DESC_PKT_LEN(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 0, 14)
#define GET_RX_DESC_CRC32(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 14, 1)
#define GET_RX_DESC_ICV(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 15, 1)
#define GET_RX_DESC_DRV_INFO_SIZE(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 16, 4)
#define GET_RX_DESC_SECURITY(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 20, 3)
#define GET_RX_DESC_QOS(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 23, 1)
#define GET_RX_DESC_SHIFT(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 24, 2)
#define GET_RX_DESC_PHYST(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 26, 1)
#define GET_RX_DESC_SWDEC(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 27, 1)
#define GET_RX_DESC_LS(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 28, 1)
#define GET_RX_DESC_FS(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 29, 1)
#define GET_RX_DESC_EOR(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 30, 1)
#define GET_RX_DESC_OWN(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 31, 1)
#define SET_RX_DESC_PKT_LEN(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 0, 14, __val)
#define SET_RX_DESC_EOR(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 30, 1, __val)
#define SET_RX_DESC_OWN(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val)
#define GET_RX_DESC_MACID(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 0, 7)
#define GET_RX_DESC_TID(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 8, 4)
#define GET_RX_DESC_MACID_VLD(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 12, 1)
#define GET_RX_DESC_AMSDU(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 13, 1)
#define GET_RX_DESC_RXID_MATCH(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 14, 1)
#define GET_RX_DESC_PAGGR(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 15, 1)
#define GET_RX_DESC_A1_FIT(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 16, 4)
#define GET_RX_DESC_TCPOFFLOAD_CHKERR(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 20, 1)
#define GET_RX_DESC_TCPOFFLOAD_IPVER(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 21, 1)
#define GET_RX_DESC_TCPOFFLOAD_IS_TCPUDP(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 22, 1)
#define GET_RX_DESC_TCPOFFLOAD_CHK_VLD(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 23, 1)
#define GET_RX_DESC_PAM(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 24, 1)
#define GET_RX_DESC_PWR(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 25, 1)
#define GET_RX_DESC_MD(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 26, 1)
#define GET_RX_DESC_MF(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 27, 1)
#define GET_RX_DESC_TYPE(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 28, 2)
#define GET_RX_DESC_MC(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 30, 1)
#define GET_RX_DESC_BC(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 31, 1)
#define GET_RX_DESC_SEQ(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+8, 0, 12)
#define GET_RX_DESC_FRAG(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+8, 12, 4)
#define GET_RX_DESC_RX_IS_QOS(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+8, 16, 1)
#define GET_RX_DESC_RXMCS(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+12, 0, 7)
#define GET_RX_DESC_HTC(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+12, 10, 1)
#define GET_RX_STATUS_DESC_EOSP(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+12, 11, 1)
#define GET_RX_STATUS_DESC_BSSID_FIT(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+12, 12, 2)
#define GET_RX_STATUS_DESC_DMA_AGG_NUM(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+12, 16, 8)
#define GET_RX_STATUS_DESC_PATTERN_MATCH(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+12, 29, 1)
#define GET_RX_STATUS_DESC_UNICAST_MATCH(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+12, 30, 1)
#define GET_RX_STATUS_DESC_MAGIC_MATCH(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+12, 31, 1)
#define GET_RX_DESC_TSFL(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+20, 0, 32)
#define GET_RX_DESC_BUFF_ADDR(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+24, 0, 32)
#define GET_RX_DESC_BUFF_ADDR64(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+28, 0, 32)
#define SET_RX_DESC_BUFF_ADDR(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 32, __val)
#define SET_RX_DESC_BUFF_ADDR64(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+28, 0, 32, __val)
/* TX report 2 format in Rx desc*/
#define GET_RX_RPT2_DESC_PKT_LEN(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc , 0, 9)
#define GET_RX_RPT2_DESC_MACID_VALID_1(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 0, 32)
#define GET_RX_RPT2_DESC_MACID_VALID_2(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
#define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \
do { \
if (_size > TX_DESC_NEXT_DESC_OFFSET) \
memset(__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET); \
else \
memset(__pdesc, 0, _size); \
} while (0)
#define RX_HAL_IS_CCK_RATE(rxmcs)\
(rxmcs == DESC92C_RATE1M ||\
rxmcs == DESC92C_RATE2M ||\
rxmcs == DESC92C_RATE5_5M ||\
rxmcs == DESC92C_RATE11M)
#define IS_LITTLE_ENDIAN 1
struct phy_rx_agc_info_t {
#if IS_LITTLE_ENDIAN
u8 gain:7 , trsw:1;
#else
u8 trsw:1 , gain:7;
#endif
};
struct phy_status_rpt {
struct phy_rx_agc_info_t path_agc[2];
u8 ch_corr[2];
u8 cck_sig_qual_ofdm_pwdb_all;
u8 cck_agc_rpt_ofdm_cfosho_a;
u8 cck_rpt_b_ofdm_cfosho_b;
u8 rsvd_1;
u8 noise_power_db_msb;
u8 path_cfotail[2];
u8 pcts_mask[2];
u8 stream_rxevm[2];
u8 path_rxsnr[2];
u8 noise_power_db_lsb;
u8 rsvd_2[3];
u8 stream_csi[2];
u8 stream_target_csi[2];
u8 sig_evm;
u8 rsvd_3;
#if IS_LITTLE_ENDIAN
u8 antsel_rx_keep_2:1; /*ex_intf_flg:1;*/
u8 sgi_en:1;
u8 rxsc:2;
u8 idle_long:1;
u8 r_ant_train_en:1;
u8 ant_sel_b:1;
u8 ant_sel:1;
#else /* _BIG_ENDIAN_ */
u8 ant_sel:1;
u8 ant_sel_b:1;
u8 r_ant_train_en:1;
u8 idle_long:1;
u8 rxsc:2;
u8 sgi_en:1;
u8 antsel_rx_keep_2:1; /*ex_intf_flg:1;*/
#endif
} __packed;
struct rx_fwinfo {
u8 gain_trsw[4];
u8 pwdb_all;
u8 cfosho[4];
u8 cfotail[4];
char rxevm[2];
char rxsnr[4];
u8 pdsnr[2];
u8 csi_current[2];
u8 csi_target[2];
u8 sigevm;
u8 max_ex_pwr;
u8 ex_intf_flag:1;
u8 sgi_en:1;
u8 rxsc:2;
u8 reserve:4;
} __packed;
struct tx_desc {
u32 pktsize:16;
u32 offset:8;
u32 bmc:1;
u32 htc:1;
u32 lastseg:1;
u32 firstseg:1;
u32 linip:1;
u32 noacm:1;
u32 gf:1;
u32 own:1;
u32 macid:6;
u32 rsvd0:2;
u32 queuesel:5;
u32 rd_nav_ext:1;
u32 lsig_txop_en:1;
u32 pifs:1;
u32 rateid:4;
u32 nav_usehdr:1;
u32 en_descid:1;
u32 sectype:2;
u32 pktoffset:8;
u32 rts_rc:6;
u32 data_rc:6;
u32 agg_en:1;
u32 rdg_en:1;
u32 bar_retryht:2;
u32 agg_break:1;
u32 morefrag:1;
u32 raw:1;
u32 ccx:1;
u32 ampdudensity:3;
u32 bt_int:1;
u32 ant_sela:1;
u32 ant_selb:1;
u32 txant_cck:2;
u32 txant_l:2;
u32 txant_ht:2;
u32 nextheadpage:8;
u32 tailpage:8;
u32 seq:12;
u32 cpu_handle:1;
u32 tag1:1;
u32 trigger_int:1;
u32 hwseq_en:1;
u32 rtsrate:5;
u32 apdcfe:1;
u32 qos:1;
u32 hwseq_ssn:1;
u32 userrate:1;
u32 dis_rtsfb:1;
u32 dis_datafb:1;
u32 cts2self:1;
u32 rts_en:1;
u32 hwrts_en:1;
u32 portid:1;
u32 pwr_status:3;
u32 waitdcts:1;
u32 cts2ap_en:1;
u32 txsc:2;
u32 stbc:2;
u32 txshort:1;
u32 txbw:1;
u32 rtsshort:1;
u32 rtsbw:1;
u32 rtssc:2;
u32 rtsstbc:2;
u32 txrate:6;
u32 shortgi:1;
u32 ccxt:1;
u32 txrate_fb_lmt:5;
u32 rtsrate_fb_lmt:4;
u32 retrylmt_en:1;
u32 txretrylmt:6;
u32 usb_txaggnum:8;
u32 txagca:5;
u32 txagcb:5;
u32 usemaxlen:1;
u32 maxaggnum:5;
u32 mcsg1maxlen:4;
u32 mcsg2maxlen:4;
u32 mcsg3maxlen:4;
u32 mcs7sgimaxlen:4;
u32 txbuffersize:16;
u32 sw_offset30:8;
u32 sw_offset31:4;
u32 rsvd1:1;
u32 antsel_c:1;
u32 null_0:1;
u32 null_1:1;
u32 txbuffaddr;
u32 txbufferaddr64;
u32 nextdescaddress;
u32 nextdescaddress64;
u32 reserve_pass_pcie_mm_limit[4];
} __packed;
struct rx_desc {
u32 length:14;
u32 crc32:1;
u32 icverror:1;
u32 drv_infosize:4;
u32 security:3;
u32 qos:1;
u32 shift:2;
u32 phystatus:1;
u32 swdec:1;
u32 lastseg:1;
u32 firstseg:1;
u32 eor:1;
u32 own:1;
u32 macid:6;
u32 tid:4;
u32 hwrsvd:5;
u32 paggr:1;
u32 faggr:1;
u32 a1_fit:4;
u32 a2_fit:4;
u32 pam:1;
u32 pwr:1;
u32 moredata:1;
u32 morefrag:1;
u32 type:2;
u32 mc:1;
u32 bc:1;
u32 seq:12;
u32 frag:4;
u32 nextpktlen:14;
u32 nextind:1;
u32 rsvd:1;
u32 rxmcs:6;
u32 rxht:1;
u32 amsdu:1;
u32 splcp:1;
u32 bandwidth:1;
u32 htc:1;
u32 tcpchk_rpt:1;
u32 ipcchk_rpt:1;
u32 tcpchk_valid:1;
u32 hwpcerr:1;
u32 hwpcind:1;
u32 iv0:16;
u32 iv1;
u32 tsfl;
u32 bufferaddress;
u32 bufferaddress64;
} __packed;
void rtl92ee_rx_check_dma_ok(struct ieee80211_hw *hw, u8 *header_desc,
u8 queue_index);
u16 rtl92ee_rx_desc_buff_remained_cnt(struct ieee80211_hw *hw,
u8 queue_index);
void rtl92ee_get_available_desc(struct ieee80211_hw *hw , u8 queue_index);
void rtl92ee_pre_fill_tx_bd_desc(struct ieee80211_hw *hw,
u8 *tx_bd_desc, u8 *desc, u8 queue_index,
struct sk_buff *skb, dma_addr_t addr);
void rtl92ee_tx_fill_desc(struct ieee80211_hw *hw,
struct ieee80211_hdr *hdr, u8 *pdesc_tx,
u8 *pbd_desc_tx,
struct ieee80211_tx_info *info,
struct ieee80211_sta *sta,
struct sk_buff *skb,
u8 hw_queue, struct rtl_tcb_desc *ptcb_desc);
bool rtl92ee_rx_query_desc(struct ieee80211_hw *hw,
struct rtl_stats *status,
struct ieee80211_rx_status *rx_status,
u8 *pdesc, struct sk_buff *skb);
void rtl92ee_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
u8 desc_name, u8 *val);
u32 rtl92ee_get_desc(u8 *pdesc, bool istx, u8 desc_name);
bool rtl92ee_is_tx_desc_closed(struct ieee80211_hw *hw, u8 hw_queue, u16 index);
void rtl92ee_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
bool b_firstseg, bool b_lastseg,
struct sk_buff *skb);
u32 rtl92ee_rx_command_packet(struct ieee80211_hw *hw,
const struct rtl_stats *status,
struct sk_buff *skb);
#endif

290
drivers/staging/rtl8192ee/stats.c
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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "wifi.h"
#include "stats.h"
u8 stg_rtl_query_rxpwrpercentage(char antpower)
{
if ((antpower <= -100) || (antpower >= 20))
return 0;
else if (antpower >= 0)
return 100;
else
return 100 + antpower;
}
EXPORT_SYMBOL(stg_rtl_query_rxpwrpercentage);
u8 stg_rtl_evm_db_to_percentage(char value)
{
char ret_val;
ret_val = value;
if (ret_val >= 0)
ret_val = 0;
if (ret_val <= -33)
ret_val = -33;
ret_val = 0 - ret_val;
ret_val *= 3;
if (ret_val == 99)
ret_val = 100;
return ret_val;
}
EXPORT_SYMBOL(stg_rtl_evm_db_to_percentage);
u8 rtl_evm_dbm_jaguar(char value)
{
char ret_val;
ret_val = value;
/* -33dB~0dB to 33dB ~ 0dB*/
if (ret_val == -128)
ret_val = 127;
else if (ret_val < 0)
ret_val = 0 - ret_val;
ret_val = ret_val >> 1;
return ret_val;
}
EXPORT_SYMBOL(rtl_evm_dbm_jaguar);
static long rtl_translate_todbm(struct ieee80211_hw *hw,
u8 signal_strength_index)
{
long signal_power;
signal_power = (long)((signal_strength_index + 1) >> 1);
signal_power -= 95;
return signal_power;
}
long stg_rtl_signal_scale_mapping(struct ieee80211_hw *hw, long currsig)
{
long retsig;
if (currsig >= 61 && currsig <= 100)
retsig = 90 + ((currsig - 60) / 4);
else if (currsig >= 41 && currsig <= 60)
retsig = 78 + ((currsig - 40) / 2);
else if (currsig >= 31 && currsig <= 40)
retsig = 66 + (currsig - 30);
else if (currsig >= 21 && currsig <= 30)
retsig = 54 + (currsig - 20);
else if (currsig >= 5 && currsig <= 20)
retsig = 42 + (((currsig - 5) * 2) / 3);
else if (currsig == 4)
retsig = 36;
else if (currsig == 3)
retsig = 27;
else if (currsig == 2)
retsig = 18;
else if (currsig == 1)
retsig = 9;
else
retsig = currsig;
return retsig;
}
EXPORT_SYMBOL(stg_rtl_signal_scale_mapping);
static void rtl_process_ui_rssi(struct ieee80211_hw *hw, struct rtl_stats *pstatus)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
u8 rfpath;
u32 last_rssi, tmpval;
if (!pstatus->b_packet_toself && !pstatus->b_packet_beacon)
return;
rtlpriv->stats.pwdb_all_cnt += pstatus->rx_pwdb_all;
rtlpriv->stats.rssi_calculate_cnt++;
if (rtlpriv->stats.ui_rssi.total_num++ >= PHY_RSSI_SLID_WIN_MAX) {
rtlpriv->stats.ui_rssi.total_num = PHY_RSSI_SLID_WIN_MAX;
last_rssi = rtlpriv->stats.ui_rssi.elements[
rtlpriv->stats.ui_rssi.index];
rtlpriv->stats.ui_rssi.total_val -= last_rssi;
}
rtlpriv->stats.ui_rssi.total_val += pstatus->signalstrength;
rtlpriv->stats.ui_rssi.elements[rtlpriv->stats.ui_rssi.index++] =
pstatus->signalstrength;
if (rtlpriv->stats.ui_rssi.index >= PHY_RSSI_SLID_WIN_MAX)
rtlpriv->stats.ui_rssi.index = 0;
tmpval = rtlpriv->stats.ui_rssi.total_val /
rtlpriv->stats.ui_rssi.total_num;
rtlpriv->stats.signal_strength = rtl_translate_todbm(hw,
(u8) tmpval);
pstatus->rssi = rtlpriv->stats.signal_strength;
if (pstatus->b_is_cck)
return;
for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
rfpath++) {
if (rtlpriv->stats.rx_rssi_percentage[rfpath] == 0) {
rtlpriv->stats.rx_rssi_percentage[rfpath] =
pstatus->rx_mimo_signalstrength[rfpath];
}
if (pstatus->rx_mimo_signalstrength[rfpath] >
rtlpriv->stats.rx_rssi_percentage[rfpath]) {
rtlpriv->stats.rx_rssi_percentage[rfpath] =
((rtlpriv->stats.rx_rssi_percentage[rfpath] *
(RX_SMOOTH_FACTOR - 1)) +
(pstatus->rx_mimo_signalstrength[rfpath])) /
(RX_SMOOTH_FACTOR);
rtlpriv->stats.rx_rssi_percentage[rfpath] =
rtlpriv->stats.rx_rssi_percentage[rfpath] + 1;
} else {
rtlpriv->stats.rx_rssi_percentage[rfpath] =
((rtlpriv->stats.rx_rssi_percentage[rfpath] *
(RX_SMOOTH_FACTOR - 1)) +
(pstatus->rx_mimo_signalstrength[rfpath])) /
(RX_SMOOTH_FACTOR);
}
rtlpriv->stats.rx_snr_db[rfpath] = pstatus->rx_snr[rfpath];
rtlpriv->stats.rx_evm_dbm[rfpath] =
pstatus->rx_mimo_evm_dbm[rfpath];
rtlpriv->stats.rx_cfo_short[rfpath] =
pstatus->cfo_short[rfpath];
rtlpriv->stats.rx_cfo_tail[rfpath] = pstatus->cfo_tail[rfpath];
}
}
static void rtl_update_rxsignalstatistics(struct ieee80211_hw *hw,
struct rtl_stats *pstatus)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
int weighting = 0;
if (rtlpriv->stats.recv_signal_power == 0)
rtlpriv->stats.recv_signal_power = pstatus->recvsignalpower;
if (pstatus->recvsignalpower > rtlpriv->stats.recv_signal_power)
weighting = 5;
else if (pstatus->recvsignalpower < rtlpriv->stats.recv_signal_power)
weighting = (-5);
rtlpriv->stats.recv_signal_power = (rtlpriv->stats.recv_signal_power *
5 + pstatus->recvsignalpower + weighting) / 6;
}
static void rtl_process_pwdb(struct ieee80211_hw *hw, struct rtl_stats *pstatus)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_sta_info *drv_priv = NULL;
struct ieee80211_sta *sta = NULL;
long undecorated_smoothed_pwdb;
rcu_read_lock();
if (rtlpriv->mac80211.opmode != NL80211_IFTYPE_STATION)
sta = rtl_find_sta(hw, pstatus->psaddr);
/* adhoc or ap mode */
if (sta) {
drv_priv = (struct rtl_sta_info *)sta->drv_priv;
undecorated_smoothed_pwdb =
drv_priv->rssi_stat.undecorated_smoothed_pwdb;
} else {
undecorated_smoothed_pwdb =
rtlpriv->dm.undecorated_smoothed_pwdb;
}
if (undecorated_smoothed_pwdb < 0)
undecorated_smoothed_pwdb = pstatus->rx_pwdb_all;
if (pstatus->rx_pwdb_all > (u32) undecorated_smoothed_pwdb) {
undecorated_smoothed_pwdb = (((undecorated_smoothed_pwdb) *
(RX_SMOOTH_FACTOR - 1)) +
(pstatus->rx_pwdb_all)) / (RX_SMOOTH_FACTOR);
undecorated_smoothed_pwdb = undecorated_smoothed_pwdb + 1;
} else {
undecorated_smoothed_pwdb = (((undecorated_smoothed_pwdb) *
(RX_SMOOTH_FACTOR - 1)) +
(pstatus->rx_pwdb_all)) / (RX_SMOOTH_FACTOR);
}
if (sta) {
drv_priv->rssi_stat.undecorated_smoothed_pwdb =
undecorated_smoothed_pwdb;
} else {
rtlpriv->dm.undecorated_smoothed_pwdb = undecorated_smoothed_pwdb;
}
rcu_read_unlock();
rtl_update_rxsignalstatistics(hw, pstatus);
}
static void rtl_process_ui_link_quality(struct ieee80211_hw *hw,
struct rtl_stats *pstatus)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 last_evm, n_stream, tmpval;
if (pstatus->signalquality == 0)
return;
if (rtlpriv->stats.ui_link_quality.total_num++ >=
PHY_LINKQUALITY_SLID_WIN_MAX) {
rtlpriv->stats.ui_link_quality.total_num =
PHY_LINKQUALITY_SLID_WIN_MAX;
last_evm = rtlpriv->stats.ui_link_quality.elements[
rtlpriv->stats.ui_link_quality.index];
rtlpriv->stats.ui_link_quality.total_val -= last_evm;
}
rtlpriv->stats.ui_link_quality.total_val += pstatus->signalquality;
rtlpriv->stats.ui_link_quality.elements[
rtlpriv->stats.ui_link_quality.index++] =
pstatus->signalquality;
if (rtlpriv->stats.ui_link_quality.index >=
PHY_LINKQUALITY_SLID_WIN_MAX)
rtlpriv->stats.ui_link_quality.index = 0;
tmpval = rtlpriv->stats.ui_link_quality.total_val /
rtlpriv->stats.ui_link_quality.total_num;
rtlpriv->stats.signal_quality = tmpval;
rtlpriv->stats.last_sigstrength_inpercent = tmpval;
for (n_stream = 0; n_stream < 2; n_stream++) {
if (pstatus->rx_mimo_signalquality[n_stream] != -1) {
if (rtlpriv->stats.rx_evm_percentage[n_stream] == 0) {
rtlpriv->stats.rx_evm_percentage[n_stream] =
pstatus->rx_mimo_signalquality[n_stream];
}
rtlpriv->stats.rx_evm_percentage[n_stream] =
((rtlpriv->stats.rx_evm_percentage[n_stream]
* (RX_SMOOTH_FACTOR - 1)) +
(pstatus->rx_mimo_signalquality[n_stream] * 1)) /
(RX_SMOOTH_FACTOR);
}
}
}
void stg_rtl_process_phyinfo(struct ieee80211_hw *hw, u8 *buffer,
struct rtl_stats *pstatus)
{
if (!pstatus->b_packet_matchbssid)
return;
rtl_process_ui_rssi(hw, pstatus);
rtl_process_pwdb(hw, pstatus);
rtl_process_ui_link_quality(hw, pstatus);
}
EXPORT_SYMBOL(stg_rtl_process_phyinfo);

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drivers/staging/rtl8192ee/stats.h
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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL_STATS_H__
#define __RTL_STATS_H__
#define PHY_RSSI_SLID_WIN_MAX 100
#define PHY_LINKQUALITY_SLID_WIN_MAX 20
#define PHY_BEACON_RSSI_SLID_WIN_MAX 10
/* Rx smooth factor */
#define RX_SMOOTH_FACTOR 20
u8 stg_rtl_query_rxpwrpercentage(char antpower);
u8 stg_rtl_evm_db_to_percentage(char value);
u8 rtl_evm_dbm_jaguar(char value);
long stg_rtl_signal_scale_mapping(struct ieee80211_hw *hw, long currsig);
void stg_rtl_process_phyinfo(struct ieee80211_hw *hw, u8 *buffer,
struct rtl_stats *pstatus);
#endif

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drivers/staging/rtl8192ee/wifi.h
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