Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm radeon fixes from Dave Airlie: "This is just radeon fixes and a bunch of new PCI ids. The fixes are for a deadlock, an audio regression, and a couple of audio fixes." * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm/radeon/kms: add new SI PCI ids drm/radeon/kms: add new BTC PCI ids drm/radeon/kms: add new Palm, Sumo PCI ids drm/radeon/kms: add new Trinity PCI ids drm/radeon: fix vm deadlocks on cayman drm/radeon: fix gpu_init on si drm/radeon/hdmi: don't set SEND_MAX_PACKETS bit drm/radeon/audio: don't hardcode CRTC id drm/radeon: make audio_init consistent across asics
This commit is contained in:
Linus Torvalds
commit
f80c43efb3
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@ -460,15 +460,28 @@ static void cayman_gpu_init(struct radeon_device *rdev)
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rdev->config.cayman.max_pipes_per_simd = 4;
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rdev->config.cayman.max_tile_pipes = 2;
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if ((rdev->pdev->device == 0x9900) ||
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(rdev->pdev->device == 0x9901)) {
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(rdev->pdev->device == 0x9901) ||
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(rdev->pdev->device == 0x9905) ||
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(rdev->pdev->device == 0x9906) ||
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(rdev->pdev->device == 0x9907) ||
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(rdev->pdev->device == 0x9908) ||
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(rdev->pdev->device == 0x9909) ||
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(rdev->pdev->device == 0x9910) ||
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(rdev->pdev->device == 0x9917)) {
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rdev->config.cayman.max_simds_per_se = 6;
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rdev->config.cayman.max_backends_per_se = 2;
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} else if ((rdev->pdev->device == 0x9903) ||
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(rdev->pdev->device == 0x9904)) {
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(rdev->pdev->device == 0x9904) ||
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(rdev->pdev->device == 0x990A) ||
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(rdev->pdev->device == 0x9913) ||
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(rdev->pdev->device == 0x9918)) {
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rdev->config.cayman.max_simds_per_se = 4;
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rdev->config.cayman.max_backends_per_se = 2;
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} else if ((rdev->pdev->device == 0x9990) ||
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(rdev->pdev->device == 0x9991)) {
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} else if ((rdev->pdev->device == 0x9919) ||
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(rdev->pdev->device == 0x9990) ||
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(rdev->pdev->device == 0x9991) ||
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(rdev->pdev->device == 0x9994) ||
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(rdev->pdev->device == 0x99A0)) {
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rdev->config.cayman.max_simds_per_se = 3;
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rdev->config.cayman.max_backends_per_se = 1;
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} else {
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@ -2426,6 +2426,12 @@ int r600_startup(struct radeon_device *rdev)
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if (r)
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return r;
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r = r600_audio_init(rdev);
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if (r) {
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DRM_ERROR("radeon: audio init failed\n");
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return r;
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}
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return 0;
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}
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@ -2462,12 +2468,6 @@ int r600_resume(struct radeon_device *rdev)
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return r;
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}
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r = r600_audio_init(rdev);
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if (r) {
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DRM_ERROR("radeon: audio resume failed\n");
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return r;
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}
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return r;
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}
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@ -2577,9 +2577,6 @@ int r600_init(struct radeon_device *rdev)
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rdev->accel_working = false;
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}
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r = r600_audio_init(rdev);
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if (r)
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return r; /* TODO error handling */
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return 0;
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}
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@ -192,6 +192,7 @@ void r600_audio_set_clock(struct drm_encoder *encoder, int clock)
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
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int base_rate = 48000;
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switch (radeon_encoder->encoder_id) {
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@ -217,8 +218,8 @@ void r600_audio_set_clock(struct drm_encoder *encoder, int clock)
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WREG32(EVERGREEN_AUDIO_PLL1_DIV, clock * 10);
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WREG32(EVERGREEN_AUDIO_PLL1_UNK, 0x00000071);
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/* Some magic trigger or src sel? */
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WREG32_P(0x5ac, 0x01, ~0x77);
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/* Select DTO source */
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WREG32(0x5ac, radeon_crtc->crtc_id);
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} else {
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switch (dig->dig_encoder) {
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case 0:
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@ -348,7 +348,6 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
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WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
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HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
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HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
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HDMI0_AUDIO_SEND_MAX_PACKETS | /* send NULL packets if no audio is available */
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HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
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HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
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}
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@ -1374,9 +1374,9 @@ struct cayman_asic {
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struct si_asic {
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unsigned max_shader_engines;
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unsigned max_pipes_per_simd;
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unsigned max_tile_pipes;
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unsigned max_simds_per_se;
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unsigned max_cu_per_sh;
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unsigned max_sh_per_se;
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unsigned max_backends_per_se;
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unsigned max_texture_channel_caches;
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unsigned max_gprs;
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@ -1387,7 +1387,6 @@ struct si_asic {
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unsigned sc_hiz_tile_fifo_size;
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unsigned sc_earlyz_tile_fifo_size;
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unsigned num_shader_engines;
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unsigned num_tile_pipes;
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unsigned num_backends_per_se;
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unsigned backend_disable_mask_per_asic;
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@ -476,12 +476,18 @@ int radeon_vm_bo_add(struct radeon_device *rdev,
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mutex_lock(&vm->mutex);
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if (last_pfn > vm->last_pfn) {
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/* grow va space 32M by 32M */
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unsigned align = ((32 << 20) >> 12) - 1;
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/* release mutex and lock in right order */
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mutex_unlock(&vm->mutex);
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radeon_mutex_lock(&rdev->cs_mutex);
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radeon_vm_unbind_locked(rdev, vm);
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mutex_lock(&vm->mutex);
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/* and check again */
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if (last_pfn > vm->last_pfn) {
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/* grow va space 32M by 32M */
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unsigned align = ((32 << 20) >> 12) - 1;
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radeon_vm_unbind_locked(rdev, vm);
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vm->last_pfn = (last_pfn + align) & ~align;
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}
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radeon_mutex_unlock(&rdev->cs_mutex);
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vm->last_pfn = (last_pfn + align) & ~align;
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}
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head = &vm->va;
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last_offset = 0;
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@ -595,8 +601,8 @@ int radeon_vm_bo_rmv(struct radeon_device *rdev,
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if (bo_va == NULL)
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return 0;
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mutex_lock(&vm->mutex);
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radeon_mutex_lock(&rdev->cs_mutex);
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mutex_lock(&vm->mutex);
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radeon_vm_bo_update_pte(rdev, vm, bo, NULL);
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radeon_mutex_unlock(&rdev->cs_mutex);
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list_del(&bo_va->vm_list);
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@ -641,9 +647,8 @@ void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm)
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struct radeon_bo_va *bo_va, *tmp;
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int r;
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mutex_lock(&vm->mutex);
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radeon_mutex_lock(&rdev->cs_mutex);
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mutex_lock(&vm->mutex);
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radeon_vm_unbind_locked(rdev, vm);
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radeon_mutex_unlock(&rdev->cs_mutex);
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@ -273,7 +273,7 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
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break;
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case RADEON_INFO_MAX_PIPES:
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if (rdev->family >= CHIP_TAHITI)
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value = rdev->config.si.max_pipes_per_simd;
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value = rdev->config.si.max_cu_per_sh;
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else if (rdev->family >= CHIP_CAYMAN)
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value = rdev->config.cayman.max_pipes_per_simd;
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else if (rdev->family >= CHIP_CEDAR)
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@ -908,12 +908,6 @@ static int rs600_startup(struct radeon_device *rdev)
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return r;
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}
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r = r600_audio_init(rdev);
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if (r) {
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dev_err(rdev->dev, "failed initializing audio\n");
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return r;
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}
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r = radeon_ib_pool_start(rdev);
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if (r)
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return r;
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@ -922,6 +916,12 @@ static int rs600_startup(struct radeon_device *rdev)
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if (r)
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return r;
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r = r600_audio_init(rdev);
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if (r) {
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dev_err(rdev->dev, "failed initializing audio\n");
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return r;
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}
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return 0;
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}
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@ -637,12 +637,6 @@ static int rs690_startup(struct radeon_device *rdev)
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return r;
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}
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r = r600_audio_init(rdev);
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if (r) {
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dev_err(rdev->dev, "failed initializing audio\n");
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return r;
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}
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r = radeon_ib_pool_start(rdev);
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if (r)
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return r;
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@ -651,6 +645,12 @@ static int rs690_startup(struct radeon_device *rdev)
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if (r)
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return r;
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r = r600_audio_init(rdev);
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if (r) {
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dev_err(rdev->dev, "failed initializing audio\n");
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return r;
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}
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return 0;
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}
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@ -956,6 +956,12 @@ static int rv770_startup(struct radeon_device *rdev)
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if (r)
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return r;
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r = r600_audio_init(rdev);
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if (r) {
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DRM_ERROR("radeon: audio init failed\n");
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return r;
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}
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return 0;
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}
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@ -978,12 +984,6 @@ int rv770_resume(struct radeon_device *rdev)
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return r;
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}
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r = r600_audio_init(rdev);
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if (r) {
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dev_err(rdev->dev, "radeon: audio init failed\n");
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return r;
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}
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return r;
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}
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@ -1092,12 +1092,6 @@ int rv770_init(struct radeon_device *rdev)
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rdev->accel_working = false;
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}
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r = r600_audio_init(rdev);
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if (r) {
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dev_err(rdev->dev, "radeon: audio init failed\n");
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return r;
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}
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return 0;
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}
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@ -867,200 +867,6 @@ void dce6_bandwidth_update(struct radeon_device *rdev)
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/*
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* Core functions
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*/
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static u32 si_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
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u32 num_tile_pipes,
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u32 num_backends_per_asic,
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u32 *backend_disable_mask_per_asic,
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u32 num_shader_engines)
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{
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u32 backend_map = 0;
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u32 enabled_backends_mask = 0;
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u32 enabled_backends_count = 0;
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u32 num_backends_per_se;
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u32 cur_pipe;
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u32 swizzle_pipe[SI_MAX_PIPES];
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u32 cur_backend = 0;
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u32 i;
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bool force_no_swizzle;
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/* force legal values */
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if (num_tile_pipes < 1)
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num_tile_pipes = 1;
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if (num_tile_pipes > rdev->config.si.max_tile_pipes)
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num_tile_pipes = rdev->config.si.max_tile_pipes;
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if (num_shader_engines < 1)
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num_shader_engines = 1;
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if (num_shader_engines > rdev->config.si.max_shader_engines)
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num_shader_engines = rdev->config.si.max_shader_engines;
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if (num_backends_per_asic < num_shader_engines)
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num_backends_per_asic = num_shader_engines;
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if (num_backends_per_asic > (rdev->config.si.max_backends_per_se * num_shader_engines))
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num_backends_per_asic = rdev->config.si.max_backends_per_se * num_shader_engines;
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|
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/* make sure we have the same number of backends per se */
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num_backends_per_asic = ALIGN(num_backends_per_asic, num_shader_engines);
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/* set up the number of backends per se */
|
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num_backends_per_se = num_backends_per_asic / num_shader_engines;
|
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if (num_backends_per_se > rdev->config.si.max_backends_per_se) {
|
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num_backends_per_se = rdev->config.si.max_backends_per_se;
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num_backends_per_asic = num_backends_per_se * num_shader_engines;
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}
|
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|
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/* create enable mask and count for enabled backends */
|
||||
for (i = 0; i < SI_MAX_BACKENDS; ++i) {
|
||||
if (((*backend_disable_mask_per_asic >> i) & 1) == 0) {
|
||||
enabled_backends_mask |= (1 << i);
|
||||
++enabled_backends_count;
|
||||
}
|
||||
if (enabled_backends_count == num_backends_per_asic)
|
||||
break;
|
||||
}
|
||||
|
||||
/* force the backends mask to match the current number of backends */
|
||||
if (enabled_backends_count != num_backends_per_asic) {
|
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u32 this_backend_enabled;
|
||||
u32 shader_engine;
|
||||
u32 backend_per_se;
|
||||
|
||||
enabled_backends_mask = 0;
|
||||
enabled_backends_count = 0;
|
||||
*backend_disable_mask_per_asic = SI_MAX_BACKENDS_MASK;
|
||||
for (i = 0; i < SI_MAX_BACKENDS; ++i) {
|
||||
/* calc the current se */
|
||||
shader_engine = i / rdev->config.si.max_backends_per_se;
|
||||
/* calc the backend per se */
|
||||
backend_per_se = i % rdev->config.si.max_backends_per_se;
|
||||
/* default to not enabled */
|
||||
this_backend_enabled = 0;
|
||||
if ((shader_engine < num_shader_engines) &&
|
||||
(backend_per_se < num_backends_per_se))
|
||||
this_backend_enabled = 1;
|
||||
if (this_backend_enabled) {
|
||||
enabled_backends_mask |= (1 << i);
|
||||
*backend_disable_mask_per_asic &= ~(1 << i);
|
||||
++enabled_backends_count;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * SI_MAX_PIPES);
|
||||
switch (rdev->family) {
|
||||
case CHIP_TAHITI:
|
||||
case CHIP_PITCAIRN:
|
||||
case CHIP_VERDE:
|
||||
force_no_swizzle = true;
|
||||
break;
|
||||
default:
|
||||
force_no_swizzle = false;
|
||||
break;
|
||||
}
|
||||
if (force_no_swizzle) {
|
||||
bool last_backend_enabled = false;
|
||||
|
||||
force_no_swizzle = false;
|
||||
for (i = 0; i < SI_MAX_BACKENDS; ++i) {
|
||||
if (((enabled_backends_mask >> i) & 1) == 1) {
|
||||
if (last_backend_enabled)
|
||||
force_no_swizzle = true;
|
||||
last_backend_enabled = true;
|
||||
} else
|
||||
last_backend_enabled = false;
|
||||
}
|
||||
}
|
||||
|
||||
switch (num_tile_pipes) {
|
||||
case 1:
|
||||
case 3:
|
||||
case 5:
|
||||
case 7:
|
||||
DRM_ERROR("odd number of pipes!\n");
|
||||
break;
|
||||
case 2:
|
||||
swizzle_pipe[0] = 0;
|
||||
swizzle_pipe[1] = 1;
|
||||
break;
|
||||
case 4:
|
||||
if (force_no_swizzle) {
|
||||
swizzle_pipe[0] = 0;
|
||||
swizzle_pipe[1] = 1;
|
||||
swizzle_pipe[2] = 2;
|
||||
swizzle_pipe[3] = 3;
|
||||
} else {
|
||||
swizzle_pipe[0] = 0;
|
||||
swizzle_pipe[1] = 2;
|
||||
swizzle_pipe[2] = 1;
|
||||
swizzle_pipe[3] = 3;
|
||||
}
|
||||
break;
|
||||
case 6:
|
||||
if (force_no_swizzle) {
|
||||
swizzle_pipe[0] = 0;
|
||||
swizzle_pipe[1] = 1;
|
||||
swizzle_pipe[2] = 2;
|
||||
swizzle_pipe[3] = 3;
|
||||
swizzle_pipe[4] = 4;
|
||||
swizzle_pipe[5] = 5;
|
||||
} else {
|
||||
swizzle_pipe[0] = 0;
|
||||
swizzle_pipe[1] = 2;
|
||||
swizzle_pipe[2] = 4;
|
||||
swizzle_pipe[3] = 1;
|
||||
swizzle_pipe[4] = 3;
|
||||
swizzle_pipe[5] = 5;
|
||||
}
|
||||
break;
|
||||
case 8:
|
||||
if (force_no_swizzle) {
|
||||
swizzle_pipe[0] = 0;
|
||||
swizzle_pipe[1] = 1;
|
||||
swizzle_pipe[2] = 2;
|
||||
swizzle_pipe[3] = 3;
|
||||
swizzle_pipe[4] = 4;
|
||||
swizzle_pipe[5] = 5;
|
||||
swizzle_pipe[6] = 6;
|
||||
swizzle_pipe[7] = 7;
|
||||
} else {
|
||||
swizzle_pipe[0] = 0;
|
||||
swizzle_pipe[1] = 2;
|
||||
swizzle_pipe[2] = 4;
|
||||
swizzle_pipe[3] = 6;
|
||||
swizzle_pipe[4] = 1;
|
||||
swizzle_pipe[5] = 3;
|
||||
swizzle_pipe[6] = 5;
|
||||
swizzle_pipe[7] = 7;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
|
||||
while (((1 << cur_backend) & enabled_backends_mask) == 0)
|
||||
cur_backend = (cur_backend + 1) % SI_MAX_BACKENDS;
|
||||
|
||||
backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
|
||||
|
||||
cur_backend = (cur_backend + 1) % SI_MAX_BACKENDS;
|
||||
}
|
||||
|
||||
return backend_map;
|
||||
}
|
||||
|
||||
static u32 si_get_disable_mask_per_asic(struct radeon_device *rdev,
|
||||
u32 disable_mask_per_se,
|
||||
u32 max_disable_mask_per_se,
|
||||
u32 num_shader_engines)
|
||||
{
|
||||
u32 disable_field_width_per_se = r600_count_pipe_bits(disable_mask_per_se);
|
||||
u32 disable_mask_per_asic = disable_mask_per_se & max_disable_mask_per_se;
|
||||
|
||||
if (num_shader_engines == 1)
|
||||
return disable_mask_per_asic;
|
||||
else if (num_shader_engines == 2)
|
||||
return disable_mask_per_asic | (disable_mask_per_asic << disable_field_width_per_se);
|
||||
else
|
||||
return 0xffffffff;
|
||||
}
|
||||
|
||||
static void si_tiling_mode_table_init(struct radeon_device *rdev)
|
||||
{
|
||||
const u32 num_tile_mode_states = 32;
|
||||
|
|
@ -1562,18 +1368,151 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
|
|||
DRM_ERROR("unknown asic: 0x%x\n", rdev->family);
|
||||
}
|
||||
|
||||
static void si_select_se_sh(struct radeon_device *rdev,
|
||||
u32 se_num, u32 sh_num)
|
||||
{
|
||||
u32 data = INSTANCE_BROADCAST_WRITES;
|
||||
|
||||
if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
|
||||
data = SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
|
||||
else if (se_num == 0xffffffff)
|
||||
data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
|
||||
else if (sh_num == 0xffffffff)
|
||||
data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
|
||||
else
|
||||
data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
|
||||
WREG32(GRBM_GFX_INDEX, data);
|
||||
}
|
||||
|
||||
static u32 si_create_bitmask(u32 bit_width)
|
||||
{
|
||||
u32 i, mask = 0;
|
||||
|
||||
for (i = 0; i < bit_width; i++) {
|
||||
mask <<= 1;
|
||||
mask |= 1;
|
||||
}
|
||||
return mask;
|
||||
}
|
||||
|
||||
static u32 si_get_cu_enabled(struct radeon_device *rdev, u32 cu_per_sh)
|
||||
{
|
||||
u32 data, mask;
|
||||
|
||||
data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
|
||||
if (data & 1)
|
||||
data &= INACTIVE_CUS_MASK;
|
||||
else
|
||||
data = 0;
|
||||
data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);
|
||||
|
||||
data >>= INACTIVE_CUS_SHIFT;
|
||||
|
||||
mask = si_create_bitmask(cu_per_sh);
|
||||
|
||||
return ~data & mask;
|
||||
}
|
||||
|
||||
static void si_setup_spi(struct radeon_device *rdev,
|
||||
u32 se_num, u32 sh_per_se,
|
||||
u32 cu_per_sh)
|
||||
{
|
||||
int i, j, k;
|
||||
u32 data, mask, active_cu;
|
||||
|
||||
for (i = 0; i < se_num; i++) {
|
||||
for (j = 0; j < sh_per_se; j++) {
|
||||
si_select_se_sh(rdev, i, j);
|
||||
data = RREG32(SPI_STATIC_THREAD_MGMT_3);
|
||||
active_cu = si_get_cu_enabled(rdev, cu_per_sh);
|
||||
|
||||
mask = 1;
|
||||
for (k = 0; k < 16; k++) {
|
||||
mask <<= k;
|
||||
if (active_cu & mask) {
|
||||
data &= ~mask;
|
||||
WREG32(SPI_STATIC_THREAD_MGMT_3, data);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
|
||||
}
|
||||
|
||||
static u32 si_get_rb_disabled(struct radeon_device *rdev,
|
||||
u32 max_rb_num, u32 se_num,
|
||||
u32 sh_per_se)
|
||||
{
|
||||
u32 data, mask;
|
||||
|
||||
data = RREG32(CC_RB_BACKEND_DISABLE);
|
||||
if (data & 1)
|
||||
data &= BACKEND_DISABLE_MASK;
|
||||
else
|
||||
data = 0;
|
||||
data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
|
||||
|
||||
data >>= BACKEND_DISABLE_SHIFT;
|
||||
|
||||
mask = si_create_bitmask(max_rb_num / se_num / sh_per_se);
|
||||
|
||||
return data & mask;
|
||||
}
|
||||
|
||||
static void si_setup_rb(struct radeon_device *rdev,
|
||||
u32 se_num, u32 sh_per_se,
|
||||
u32 max_rb_num)
|
||||
{
|
||||
int i, j;
|
||||
u32 data, mask;
|
||||
u32 disabled_rbs = 0;
|
||||
u32 enabled_rbs = 0;
|
||||
|
||||
for (i = 0; i < se_num; i++) {
|
||||
for (j = 0; j < sh_per_se; j++) {
|
||||
si_select_se_sh(rdev, i, j);
|
||||
data = si_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se);
|
||||
disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
|
||||
}
|
||||
}
|
||||
si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
|
||||
|
||||
mask = 1;
|
||||
for (i = 0; i < max_rb_num; i++) {
|
||||
if (!(disabled_rbs & mask))
|
||||
enabled_rbs |= mask;
|
||||
mask <<= 1;
|
||||
}
|
||||
|
||||
for (i = 0; i < se_num; i++) {
|
||||
si_select_se_sh(rdev, i, 0xffffffff);
|
||||
data = 0;
|
||||
for (j = 0; j < sh_per_se; j++) {
|
||||
switch (enabled_rbs & 3) {
|
||||
case 1:
|
||||
data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
|
||||
break;
|
||||
case 2:
|
||||
data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
|
||||
break;
|
||||
case 3:
|
||||
default:
|
||||
data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
|
||||
break;
|
||||
}
|
||||
enabled_rbs >>= 2;
|
||||
}
|
||||
WREG32(PA_SC_RASTER_CONFIG, data);
|
||||
}
|
||||
si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
|
||||
}
|
||||
|
||||
static void si_gpu_init(struct radeon_device *rdev)
|
||||
{
|
||||
u32 cc_rb_backend_disable = 0;
|
||||
u32 cc_gc_shader_array_config;
|
||||
u32 gb_addr_config = 0;
|
||||
u32 mc_shared_chmap, mc_arb_ramcfg;
|
||||
u32 gb_backend_map;
|
||||
u32 cgts_tcc_disable;
|
||||
u32 sx_debug_1;
|
||||
u32 gc_user_shader_array_config;
|
||||
u32 gc_user_rb_backend_disable;
|
||||
u32 cgts_user_tcc_disable;
|
||||
u32 hdp_host_path_cntl;
|
||||
u32 tmp;
|
||||
int i, j;
|
||||
|
|
@ -1581,9 +1520,9 @@ static void si_gpu_init(struct radeon_device *rdev)
|
|||
switch (rdev->family) {
|
||||
case CHIP_TAHITI:
|
||||
rdev->config.si.max_shader_engines = 2;
|
||||
rdev->config.si.max_pipes_per_simd = 4;
|
||||
rdev->config.si.max_tile_pipes = 12;
|
||||
rdev->config.si.max_simds_per_se = 8;
|
||||
rdev->config.si.max_cu_per_sh = 8;
|
||||
rdev->config.si.max_sh_per_se = 2;
|
||||
rdev->config.si.max_backends_per_se = 4;
|
||||
rdev->config.si.max_texture_channel_caches = 12;
|
||||
rdev->config.si.max_gprs = 256;
|
||||
|
|
@ -1594,12 +1533,13 @@ static void si_gpu_init(struct radeon_device *rdev)
|
|||
rdev->config.si.sc_prim_fifo_size_backend = 0x100;
|
||||
rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
|
||||
rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
|
||||
gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
|
||||
break;
|
||||
case CHIP_PITCAIRN:
|
||||
rdev->config.si.max_shader_engines = 2;
|
||||
rdev->config.si.max_pipes_per_simd = 4;
|
||||
rdev->config.si.max_tile_pipes = 8;
|
||||
rdev->config.si.max_simds_per_se = 5;
|
||||
rdev->config.si.max_cu_per_sh = 5;
|
||||
rdev->config.si.max_sh_per_se = 2;
|
||||
rdev->config.si.max_backends_per_se = 4;
|
||||
rdev->config.si.max_texture_channel_caches = 8;
|
||||
rdev->config.si.max_gprs = 256;
|
||||
|
|
@ -1610,13 +1550,14 @@ static void si_gpu_init(struct radeon_device *rdev)
|
|||
rdev->config.si.sc_prim_fifo_size_backend = 0x100;
|
||||
rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
|
||||
rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
|
||||
gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
|
||||
break;
|
||||
case CHIP_VERDE:
|
||||
default:
|
||||
rdev->config.si.max_shader_engines = 1;
|
||||
rdev->config.si.max_pipes_per_simd = 4;
|
||||
rdev->config.si.max_tile_pipes = 4;
|
||||
rdev->config.si.max_simds_per_se = 2;
|
||||
rdev->config.si.max_cu_per_sh = 2;
|
||||
rdev->config.si.max_sh_per_se = 2;
|
||||
rdev->config.si.max_backends_per_se = 4;
|
||||
rdev->config.si.max_texture_channel_caches = 4;
|
||||
rdev->config.si.max_gprs = 256;
|
||||
|
|
@ -1627,6 +1568,7 @@ static void si_gpu_init(struct radeon_device *rdev)
|
|||
rdev->config.si.sc_prim_fifo_size_backend = 0x40;
|
||||
rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
|
||||
rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
|
||||
gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -1648,31 +1590,7 @@ static void si_gpu_init(struct radeon_device *rdev)
|
|||
mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
|
||||
mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
|
||||
|
||||
cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE);
|
||||
cc_gc_shader_array_config = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
|
||||
cgts_tcc_disable = 0xffff0000;
|
||||
for (i = 0; i < rdev->config.si.max_texture_channel_caches; i++)
|
||||
cgts_tcc_disable &= ~(1 << (16 + i));
|
||||
gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE);
|
||||
gc_user_shader_array_config = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
|
||||
cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE);
|
||||
|
||||
rdev->config.si.num_shader_engines = rdev->config.si.max_shader_engines;
|
||||
rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes;
|
||||
tmp = ((~gc_user_rb_backend_disable) & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
|
||||
rdev->config.si.num_backends_per_se = r600_count_pipe_bits(tmp);
|
||||
tmp = (gc_user_rb_backend_disable & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
|
||||
rdev->config.si.backend_disable_mask_per_asic =
|
||||
si_get_disable_mask_per_asic(rdev, tmp, SI_MAX_BACKENDS_PER_SE_MASK,
|
||||
rdev->config.si.num_shader_engines);
|
||||
rdev->config.si.backend_map =
|
||||
si_get_tile_pipe_to_backend_map(rdev, rdev->config.si.num_tile_pipes,
|
||||
rdev->config.si.num_backends_per_se *
|
||||
rdev->config.si.num_shader_engines,
|
||||
&rdev->config.si.backend_disable_mask_per_asic,
|
||||
rdev->config.si.num_shader_engines);
|
||||
tmp = ((~cgts_user_tcc_disable) & TCC_DISABLE_MASK) >> TCC_DISABLE_SHIFT;
|
||||
rdev->config.si.num_texture_channel_caches = r600_count_pipe_bits(tmp);
|
||||
rdev->config.si.mem_max_burst_length_bytes = 256;
|
||||
tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
|
||||
rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
|
||||
|
|
@ -1683,55 +1601,8 @@ static void si_gpu_init(struct radeon_device *rdev)
|
|||
rdev->config.si.num_gpus = 1;
|
||||
rdev->config.si.multi_gpu_tile_size = 64;
|
||||
|
||||
gb_addr_config = 0;
|
||||
switch (rdev->config.si.num_tile_pipes) {
|
||||
case 1:
|
||||
gb_addr_config |= NUM_PIPES(0);
|
||||
break;
|
||||
case 2:
|
||||
gb_addr_config |= NUM_PIPES(1);
|
||||
break;
|
||||
case 4:
|
||||
gb_addr_config |= NUM_PIPES(2);
|
||||
break;
|
||||
case 8:
|
||||
default:
|
||||
gb_addr_config |= NUM_PIPES(3);
|
||||
break;
|
||||
}
|
||||
|
||||
tmp = (rdev->config.si.mem_max_burst_length_bytes / 256) - 1;
|
||||
gb_addr_config |= PIPE_INTERLEAVE_SIZE(tmp);
|
||||
gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.si.num_shader_engines - 1);
|
||||
tmp = (rdev->config.si.shader_engine_tile_size / 16) - 1;
|
||||
gb_addr_config |= SHADER_ENGINE_TILE_SIZE(tmp);
|
||||
switch (rdev->config.si.num_gpus) {
|
||||
case 1:
|
||||
default:
|
||||
gb_addr_config |= NUM_GPUS(0);
|
||||
break;
|
||||
case 2:
|
||||
gb_addr_config |= NUM_GPUS(1);
|
||||
break;
|
||||
case 4:
|
||||
gb_addr_config |= NUM_GPUS(2);
|
||||
break;
|
||||
}
|
||||
switch (rdev->config.si.multi_gpu_tile_size) {
|
||||
case 16:
|
||||
gb_addr_config |= MULTI_GPU_TILE_SIZE(0);
|
||||
break;
|
||||
case 32:
|
||||
default:
|
||||
gb_addr_config |= MULTI_GPU_TILE_SIZE(1);
|
||||
break;
|
||||
case 64:
|
||||
gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
|
||||
break;
|
||||
case 128:
|
||||
gb_addr_config |= MULTI_GPU_TILE_SIZE(3);
|
||||
break;
|
||||
}
|
||||
/* fix up row size */
|
||||
gb_addr_config &= ~ROW_SIZE_MASK;
|
||||
switch (rdev->config.si.mem_row_size_in_kb) {
|
||||
case 1:
|
||||
default:
|
||||
|
|
@ -1745,26 +1616,6 @@ static void si_gpu_init(struct radeon_device *rdev)
|
|||
break;
|
||||
}
|
||||
|
||||
tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
|
||||
rdev->config.si.num_tile_pipes = (1 << tmp);
|
||||
tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
|
||||
rdev->config.si.mem_max_burst_length_bytes = (tmp + 1) * 256;
|
||||
tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
|
||||
rdev->config.si.num_shader_engines = tmp + 1;
|
||||
tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
|
||||
rdev->config.si.num_gpus = tmp + 1;
|
||||
tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
|
||||
rdev->config.si.multi_gpu_tile_size = 1 << tmp;
|
||||
tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
|
||||
rdev->config.si.mem_row_size_in_kb = 1 << tmp;
|
||||
|
||||
gb_backend_map =
|
||||
si_get_tile_pipe_to_backend_map(rdev, rdev->config.si.num_tile_pipes,
|
||||
rdev->config.si.num_backends_per_se *
|
||||
rdev->config.si.num_shader_engines,
|
||||
&rdev->config.si.backend_disable_mask_per_asic,
|
||||
rdev->config.si.num_shader_engines);
|
||||
|
||||
/* setup tiling info dword. gb_addr_config is not adequate since it does
|
||||
* not have bank info, so create a custom tiling dword.
|
||||
* bits 3:0 num_pipes
|
||||
|
|
@ -1789,34 +1640,30 @@ static void si_gpu_init(struct radeon_device *rdev)
|
|||
rdev->config.si.tile_config |= (3 << 0);
|
||||
break;
|
||||
}
|
||||
rdev->config.si.tile_config |=
|
||||
((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
|
||||
if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
|
||||
rdev->config.si.tile_config |= 1 << 4;
|
||||
else
|
||||
rdev->config.si.tile_config |= 0 << 4;
|
||||
rdev->config.si.tile_config |=
|
||||
((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
|
||||
rdev->config.si.tile_config |=
|
||||
((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
|
||||
|
||||
rdev->config.si.backend_map = gb_backend_map;
|
||||
WREG32(GB_ADDR_CONFIG, gb_addr_config);
|
||||
WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
|
||||
WREG32(HDP_ADDR_CONFIG, gb_addr_config);
|
||||
|
||||
/* primary versions */
|
||||
WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
|
||||
WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
|
||||
WREG32(CC_GC_SHADER_ARRAY_CONFIG, cc_gc_shader_array_config);
|
||||
|
||||
WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
|
||||
|
||||
/* user versions */
|
||||
WREG32(GC_USER_RB_BACKEND_DISABLE, cc_rb_backend_disable);
|
||||
WREG32(GC_USER_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
|
||||
WREG32(GC_USER_SHADER_ARRAY_CONFIG, cc_gc_shader_array_config);
|
||||
|
||||
WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
|
||||
|
||||
si_tiling_mode_table_init(rdev);
|
||||
|
||||
si_setup_rb(rdev, rdev->config.si.max_shader_engines,
|
||||
rdev->config.si.max_sh_per_se,
|
||||
rdev->config.si.max_backends_per_se);
|
||||
|
||||
si_setup_spi(rdev, rdev->config.si.max_shader_engines,
|
||||
rdev->config.si.max_sh_per_se,
|
||||
rdev->config.si.max_cu_per_sh);
|
||||
|
||||
|
||||
/* set HW defaults for 3D engine */
|
||||
WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
|
||||
ROQ_IB2_START(0x2b)));
|
||||
|
|
|
|||
|
|
@ -24,6 +24,11 @@
|
|||
#ifndef SI_H
|
||||
#define SI_H
|
||||
|
||||
#define TAHITI_RB_BITMAP_WIDTH_PER_SH 2
|
||||
|
||||
#define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003
|
||||
#define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002
|
||||
|
||||
#define CG_MULT_THERMAL_STATUS 0x714
|
||||
#define ASIC_MAX_TEMP(x) ((x) << 0)
|
||||
#define ASIC_MAX_TEMP_MASK 0x000001ff
|
||||
|
|
@ -408,6 +413,12 @@
|
|||
#define SOFT_RESET_IA (1 << 15)
|
||||
|
||||
#define GRBM_GFX_INDEX 0x802C
|
||||
#define INSTANCE_INDEX(x) ((x) << 0)
|
||||
#define SH_INDEX(x) ((x) << 8)
|
||||
#define SE_INDEX(x) ((x) << 16)
|
||||
#define SH_BROADCAST_WRITES (1 << 29)
|
||||
#define INSTANCE_BROADCAST_WRITES (1 << 30)
|
||||
#define SE_BROADCAST_WRITES (1 << 31)
|
||||
|
||||
#define GRBM_INT_CNTL 0x8060
|
||||
# define RDERR_INT_ENABLE (1 << 0)
|
||||
|
|
@ -480,6 +491,8 @@
|
|||
#define VGT_TF_MEMORY_BASE 0x89B8
|
||||
|
||||
#define CC_GC_SHADER_ARRAY_CONFIG 0x89bc
|
||||
#define INACTIVE_CUS_MASK 0xFFFF0000
|
||||
#define INACTIVE_CUS_SHIFT 16
|
||||
#define GC_USER_SHADER_ARRAY_CONFIG 0x89c0
|
||||
|
||||
#define PA_CL_ENHANCE 0x8A14
|
||||
|
|
@ -688,6 +701,12 @@
|
|||
#define RLC_MC_CNTL 0xC344
|
||||
#define RLC_UCODE_CNTL 0xC348
|
||||
|
||||
#define PA_SC_RASTER_CONFIG 0x28350
|
||||
# define RASTER_CONFIG_RB_MAP_0 0
|
||||
# define RASTER_CONFIG_RB_MAP_1 1
|
||||
# define RASTER_CONFIG_RB_MAP_2 2
|
||||
# define RASTER_CONFIG_RB_MAP_3 3
|
||||
|
||||
#define VGT_EVENT_INITIATOR 0x28a90
|
||||
# define SAMPLE_STREAMOUTSTATS1 (1 << 0)
|
||||
# define SAMPLE_STREAMOUTSTATS2 (2 << 0)
|
||||
|
|
|
|||
|
|
@ -181,6 +181,7 @@
|
|||
{0x1002, 0x6747, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6748, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6749, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x674A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6750, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6751, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6758, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \
|
||||
|
|
@ -198,6 +199,7 @@
|
|||
{0x1002, 0x6767, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6768, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6770, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6771, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6772, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6778, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6779, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
|
||||
|
|
@ -229,10 +231,11 @@
|
|||
{0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
|
||||
|
|
@ -531,6 +534,7 @@
|
|||
{0x1002, 0x9645, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO2|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x9647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP},\
|
||||
{0x1002, 0x9648, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP},\
|
||||
{0x1002, 0x9649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP},\
|
||||
{0x1002, 0x964a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x964b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x964c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
|
|
@ -550,6 +554,7 @@
|
|||
{0x1002, 0x9807, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PALM|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x9808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PALM|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x9809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PALM|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x980A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PALM|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x9900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x9901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x9903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
|
|
@ -561,11 +566,19 @@
|
|||
{0x1002, 0x9909, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x990A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x990F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x9910, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x9913, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x9917, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x9918, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x9919, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x9990, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x9991, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x9992, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x9993, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x9994, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x99A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x99A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0x1002, 0x99A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
|
||||
{0, 0, 0}
|
||||
|
||||
#define r128_PCI_IDS \
|
||||
|
|
|
|||
Loading…
Reference in New Issue