pinctrl: sh-pfc: Updates for v4.10
- I2C and DRIF pin groups for R-Car M3-W, - Bug fixes for SDHI2/3 on R-Car M3-W. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJYIJkdAAoJEEgEtLw/Ve77l68P/RuHNpYQY3L2MDp9f/4MMbQI bgJqd0iH56Pbv13Nn1pKYabNKAMymRepCNCMa2xivXvW7fqDfiy8pT/pZWMoXaA+ sgDTgBvf2ezzvcyrHH6qZFnTCFwBKS+PCtgiRUCXvK98eYezfHg0J99goykEbcje rKPtJ1yaDTPIGUNSsjP8AqKMcNA3vLWnXNfYZWFqY7SyJTfnG/wyj7vD8YAaEqxD Odh6kPWm6jChqMnaNovyF1TAYI3wn5eJhN8oMLWQV0NwVRTMmEzEmah+ML/Dux/Z veHRuU5y7gmhYrCkrZvyXO5nZ8Gh5+1izdSL1aFtzyzhEAOopYf8k7t5ZotiL386 mDh3iPlO5HPdchPv58rDH1GnYwOOx2IZzZTOYs8NhrIETis3trv3nWGqF2J0xEOD 0yNrzUJaDbZxC4tN1lck/j/44xnmIUn+5B0TlwBDiDQBUjXtXyOgePSySK3b6VIs X/SQtdraP33MqAXXYXv9JYduHwlrBlKSNz5/xoMqxjfqfUNtYLAhHXNToXm+M5QF PrxFfdq3zzPRSIAPZ7xemW8xX4xc2hhpFjTThJT6AlxfRBr9+p1puhnT9esFGYaA sdJX1ud5SvYSDcY4mxA4gU134DvhrHyWZnZ0VLLnwpOm6yHVi1n9GS3Yn9G6z4CO 7GSrTBSlvqN88Dt1XRil =PEV2 -----END PGP SIGNATURE----- Merge tag 'sh-pfc-for-v4.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.10 - I2C and DRIF pin groups for R-Car M3-W, - Bug fixes for SDHI2/3 on R-Car M3-W.
This commit is contained in:
Linus Walleij
commit
f7cf78b953
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@ -122,22 +122,22 @@
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#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
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/* GPSR4 */
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#define GPSR4_17 F_(SD3_DS, IP11_11_8)
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#define GPSR4_16 F_(SD3_DAT7, IP10_7_4)
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#define GPSR4_15 F_(SD3_DAT6, IP10_3_0)
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#define GPSR4_14 F_(SD3_DAT5, IP9_31_28)
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#define GPSR4_13 F_(SD3_DAT4, IP9_27_24)
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#define GPSR4_17 F_(SD3_DS, IP11_7_4)
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#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
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#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
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#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
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#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
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#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
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#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
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#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
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#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
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#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
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#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
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#define GPSR4_6 F_(SD2_DS, IP9_23_20)
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#define GPSR4_5 F_(SD2_DAT3, IP9_19_16)
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#define GPSR4_4 F_(SD2_DAT2, IP9_15_12)
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#define GPSR4_3 F_(SD2_DAT1, IP9_11_8)
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#define GPSR4_2 F_(SD2_DAT0, IP9_7_4)
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#define GPSR4_6 F_(SD2_DS, IP9_27_24)
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#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
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#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
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#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
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#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
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#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
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#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
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@ -1490,6 +1490,272 @@ static const struct sh_pfc_pin pinmux_pins[] = {
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PINMUX_GPIO_GP_ALL(),
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};
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/* - DRIF0 --------------------------------------------------------------- */
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static const unsigned int drif0_ctrl_a_pins[] = {
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/* CLK, SYNC */
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RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
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};
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static const unsigned int drif0_ctrl_a_mux[] = {
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RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
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};
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static const unsigned int drif0_data0_a_pins[] = {
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/* D0 */
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RCAR_GP_PIN(6, 10),
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};
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static const unsigned int drif0_data0_a_mux[] = {
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RIF0_D0_A_MARK,
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};
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static const unsigned int drif0_data1_a_pins[] = {
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/* D1 */
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RCAR_GP_PIN(6, 7),
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};
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static const unsigned int drif0_data1_a_mux[] = {
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RIF0_D1_A_MARK,
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};
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static const unsigned int drif0_ctrl_b_pins[] = {
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/* CLK, SYNC */
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RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
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};
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static const unsigned int drif0_ctrl_b_mux[] = {
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RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
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};
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static const unsigned int drif0_data0_b_pins[] = {
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/* D0 */
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RCAR_GP_PIN(5, 1),
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};
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static const unsigned int drif0_data0_b_mux[] = {
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RIF0_D0_B_MARK,
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};
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static const unsigned int drif0_data1_b_pins[] = {
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/* D1 */
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RCAR_GP_PIN(5, 2),
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};
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static const unsigned int drif0_data1_b_mux[] = {
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RIF0_D1_B_MARK,
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};
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static const unsigned int drif0_ctrl_c_pins[] = {
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/* CLK, SYNC */
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RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
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};
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static const unsigned int drif0_ctrl_c_mux[] = {
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RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
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};
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static const unsigned int drif0_data0_c_pins[] = {
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/* D0 */
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RCAR_GP_PIN(5, 13),
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};
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static const unsigned int drif0_data0_c_mux[] = {
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RIF0_D0_C_MARK,
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};
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static const unsigned int drif0_data1_c_pins[] = {
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/* D1 */
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RCAR_GP_PIN(5, 14),
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};
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static const unsigned int drif0_data1_c_mux[] = {
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RIF0_D1_C_MARK,
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};
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/* - DRIF1 --------------------------------------------------------------- */
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static const unsigned int drif1_ctrl_a_pins[] = {
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/* CLK, SYNC */
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RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
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};
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static const unsigned int drif1_ctrl_a_mux[] = {
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RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
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};
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static const unsigned int drif1_data0_a_pins[] = {
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/* D0 */
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RCAR_GP_PIN(6, 19),
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};
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static const unsigned int drif1_data0_a_mux[] = {
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RIF1_D0_A_MARK,
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};
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static const unsigned int drif1_data1_a_pins[] = {
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/* D1 */
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RCAR_GP_PIN(6, 20),
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};
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static const unsigned int drif1_data1_a_mux[] = {
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RIF1_D1_A_MARK,
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};
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static const unsigned int drif1_ctrl_b_pins[] = {
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/* CLK, SYNC */
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RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
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};
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static const unsigned int drif1_ctrl_b_mux[] = {
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RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
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};
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static const unsigned int drif1_data0_b_pins[] = {
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/* D0 */
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RCAR_GP_PIN(5, 7),
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};
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static const unsigned int drif1_data0_b_mux[] = {
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RIF1_D0_B_MARK,
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};
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static const unsigned int drif1_data1_b_pins[] = {
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/* D1 */
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RCAR_GP_PIN(5, 8),
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};
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static const unsigned int drif1_data1_b_mux[] = {
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RIF1_D1_B_MARK,
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};
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static const unsigned int drif1_ctrl_c_pins[] = {
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/* CLK, SYNC */
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RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
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};
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static const unsigned int drif1_ctrl_c_mux[] = {
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RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
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};
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static const unsigned int drif1_data0_c_pins[] = {
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/* D0 */
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RCAR_GP_PIN(5, 6),
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};
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static const unsigned int drif1_data0_c_mux[] = {
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RIF1_D0_C_MARK,
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};
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static const unsigned int drif1_data1_c_pins[] = {
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/* D1 */
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RCAR_GP_PIN(5, 10),
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};
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static const unsigned int drif1_data1_c_mux[] = {
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RIF1_D1_C_MARK,
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};
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/* - DRIF2 --------------------------------------------------------------- */
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static const unsigned int drif2_ctrl_a_pins[] = {
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/* CLK, SYNC */
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RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
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};
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static const unsigned int drif2_ctrl_a_mux[] = {
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RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
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};
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static const unsigned int drif2_data0_a_pins[] = {
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/* D0 */
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RCAR_GP_PIN(6, 7),
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};
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static const unsigned int drif2_data0_a_mux[] = {
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RIF2_D0_A_MARK,
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};
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static const unsigned int drif2_data1_a_pins[] = {
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/* D1 */
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RCAR_GP_PIN(6, 10),
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};
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static const unsigned int drif2_data1_a_mux[] = {
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RIF2_D1_A_MARK,
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};
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static const unsigned int drif2_ctrl_b_pins[] = {
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/* CLK, SYNC */
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RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
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};
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static const unsigned int drif2_ctrl_b_mux[] = {
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RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
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};
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static const unsigned int drif2_data0_b_pins[] = {
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/* D0 */
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RCAR_GP_PIN(6, 30),
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};
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static const unsigned int drif2_data0_b_mux[] = {
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RIF2_D0_B_MARK,
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};
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static const unsigned int drif2_data1_b_pins[] = {
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/* D1 */
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RCAR_GP_PIN(6, 31),
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};
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static const unsigned int drif2_data1_b_mux[] = {
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RIF2_D1_B_MARK,
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};
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/* - DRIF3 --------------------------------------------------------------- */
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static const unsigned int drif3_ctrl_a_pins[] = {
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/* CLK, SYNC */
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RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
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};
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static const unsigned int drif3_ctrl_a_mux[] = {
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RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
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};
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static const unsigned int drif3_data0_a_pins[] = {
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/* D0 */
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RCAR_GP_PIN(6, 19),
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};
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static const unsigned int drif3_data0_a_mux[] = {
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RIF3_D0_A_MARK,
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};
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static const unsigned int drif3_data1_a_pins[] = {
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/* D1 */
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RCAR_GP_PIN(6, 20),
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};
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static const unsigned int drif3_data1_a_mux[] = {
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RIF3_D1_A_MARK,
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};
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static const unsigned int drif3_ctrl_b_pins[] = {
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/* CLK, SYNC */
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RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
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};
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static const unsigned int drif3_ctrl_b_mux[] = {
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RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
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};
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static const unsigned int drif3_data0_b_pins[] = {
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/* D0 */
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RCAR_GP_PIN(6, 28),
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};
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static const unsigned int drif3_data0_b_mux[] = {
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RIF3_D0_B_MARK,
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};
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static const unsigned int drif3_data1_b_pins[] = {
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/* D1 */
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RCAR_GP_PIN(6, 29),
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};
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static const unsigned int drif3_data1_b_mux[] = {
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RIF3_D1_B_MARK,
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};
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/* - I2C -------------------------------------------------------------------- */
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static const unsigned int i2c1_a_pins[] = {
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/* SDA, SCL */
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RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
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};
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static const unsigned int i2c1_a_mux[] = {
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SDA1_A_MARK, SCL1_A_MARK,
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};
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static const unsigned int i2c1_b_pins[] = {
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/* SDA, SCL */
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RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
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};
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static const unsigned int i2c1_b_mux[] = {
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SDA1_B_MARK, SCL1_B_MARK,
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};
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static const unsigned int i2c2_a_pins[] = {
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/* SDA, SCL */
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RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
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};
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static const unsigned int i2c2_a_mux[] = {
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SDA2_A_MARK, SCL2_A_MARK,
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};
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static const unsigned int i2c2_b_pins[] = {
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/* SDA, SCL */
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RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
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};
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static const unsigned int i2c2_b_mux[] = {
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SDA2_B_MARK, SCL2_B_MARK,
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};
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static const unsigned int i2c6_a_pins[] = {
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/* SDA, SCL */
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RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
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};
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static const unsigned int i2c6_a_mux[] = {
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SDA6_A_MARK, SCL6_A_MARK,
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};
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static const unsigned int i2c6_b_pins[] = {
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/* SDA, SCL */
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RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
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};
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static const unsigned int i2c6_b_mux[] = {
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SDA6_B_MARK, SCL6_B_MARK,
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};
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static const unsigned int i2c6_c_pins[] = {
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/* SDA, SCL */
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RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
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};
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static const unsigned int i2c6_c_mux[] = {
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SDA6_C_MARK, SCL6_C_MARK,
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};
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/* - SCIF0 ------------------------------------------------------------------ */
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static const unsigned int scif0_data_pins[] = {
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/* RX, TX */
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@ -1912,6 +2178,43 @@ static const unsigned int sdhi3_ds_mux[] = {
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};
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static const struct sh_pfc_pin_group pinmux_groups[] = {
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SH_PFC_PIN_GROUP(drif0_ctrl_a),
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SH_PFC_PIN_GROUP(drif0_data0_a),
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SH_PFC_PIN_GROUP(drif0_data1_a),
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SH_PFC_PIN_GROUP(drif0_ctrl_b),
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SH_PFC_PIN_GROUP(drif0_data0_b),
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SH_PFC_PIN_GROUP(drif0_data1_b),
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SH_PFC_PIN_GROUP(drif0_ctrl_c),
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SH_PFC_PIN_GROUP(drif0_data0_c),
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SH_PFC_PIN_GROUP(drif0_data1_c),
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SH_PFC_PIN_GROUP(drif1_ctrl_a),
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SH_PFC_PIN_GROUP(drif1_data0_a),
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SH_PFC_PIN_GROUP(drif1_data1_a),
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SH_PFC_PIN_GROUP(drif1_ctrl_b),
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SH_PFC_PIN_GROUP(drif1_data0_b),
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SH_PFC_PIN_GROUP(drif1_data1_b),
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SH_PFC_PIN_GROUP(drif1_ctrl_c),
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SH_PFC_PIN_GROUP(drif1_data0_c),
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SH_PFC_PIN_GROUP(drif1_data1_c),
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SH_PFC_PIN_GROUP(drif2_ctrl_a),
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SH_PFC_PIN_GROUP(drif2_data0_a),
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SH_PFC_PIN_GROUP(drif2_data1_a),
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SH_PFC_PIN_GROUP(drif2_ctrl_b),
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SH_PFC_PIN_GROUP(drif2_data0_b),
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SH_PFC_PIN_GROUP(drif2_data1_b),
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SH_PFC_PIN_GROUP(drif3_ctrl_a),
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SH_PFC_PIN_GROUP(drif3_data0_a),
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SH_PFC_PIN_GROUP(drif3_data1_a),
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SH_PFC_PIN_GROUP(drif3_ctrl_b),
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SH_PFC_PIN_GROUP(drif3_data0_b),
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SH_PFC_PIN_GROUP(drif3_data1_b),
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SH_PFC_PIN_GROUP(i2c1_a),
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SH_PFC_PIN_GROUP(i2c1_b),
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SH_PFC_PIN_GROUP(i2c2_a),
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SH_PFC_PIN_GROUP(i2c2_b),
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SH_PFC_PIN_GROUP(i2c6_a),
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SH_PFC_PIN_GROUP(i2c6_b),
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SH_PFC_PIN_GROUP(i2c6_c),
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SH_PFC_PIN_GROUP(scif0_data),
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SH_PFC_PIN_GROUP(scif0_clk),
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SH_PFC_PIN_GROUP(scif0_ctrl),
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|
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@ -1969,6 +2272,64 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
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SH_PFC_PIN_GROUP(sdhi3_ds),
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};
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static const char * const drif0_groups[] = {
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"drif0_ctrl_a",
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"drif0_data0_a",
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"drif0_data1_a",
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||||
"drif0_ctrl_b",
|
||||
"drif0_data0_b",
|
||||
"drif0_data1_b",
|
||||
"drif0_ctrl_c",
|
||||
"drif0_data0_c",
|
||||
"drif0_data1_c",
|
||||
};
|
||||
|
||||
static const char * const drif1_groups[] = {
|
||||
"drif1_ctrl_a",
|
||||
"drif1_data0_a",
|
||||
"drif1_data1_a",
|
||||
"drif1_ctrl_b",
|
||||
"drif1_data0_b",
|
||||
"drif1_data1_b",
|
||||
"drif1_ctrl_c",
|
||||
"drif1_data0_c",
|
||||
"drif1_data1_c",
|
||||
};
|
||||
|
||||
static const char * const drif2_groups[] = {
|
||||
"drif2_ctrl_a",
|
||||
"drif2_data0_a",
|
||||
"drif2_data1_a",
|
||||
"drif2_ctrl_b",
|
||||
"drif2_data0_b",
|
||||
"drif2_data1_b",
|
||||
};
|
||||
|
||||
static const char * const drif3_groups[] = {
|
||||
"drif3_ctrl_a",
|
||||
"drif3_data0_a",
|
||||
"drif3_data1_a",
|
||||
"drif3_ctrl_b",
|
||||
"drif3_data0_b",
|
||||
"drif3_data1_b",
|
||||
};
|
||||
|
||||
static const char * const i2c1_groups[] = {
|
||||
"i2c1_a",
|
||||
"i2c1_b",
|
||||
};
|
||||
|
||||
static const char * const i2c2_groups[] = {
|
||||
"i2c2_a",
|
||||
"i2c2_b",
|
||||
};
|
||||
|
||||
static const char * const i2c6_groups[] = {
|
||||
"i2c6_a",
|
||||
"i2c6_b",
|
||||
"i2c6_c",
|
||||
};
|
||||
|
||||
static const char * const scif0_groups[] = {
|
||||
"scif0_data",
|
||||
"scif0_clk",
|
||||
|
|
@ -2058,6 +2419,13 @@ static const char * const sdhi3_groups[] = {
|
|||
};
|
||||
|
||||
static const struct sh_pfc_function pinmux_functions[] = {
|
||||
SH_PFC_FUNCTION(drif0),
|
||||
SH_PFC_FUNCTION(drif1),
|
||||
SH_PFC_FUNCTION(drif2),
|
||||
SH_PFC_FUNCTION(drif3),
|
||||
SH_PFC_FUNCTION(i2c1),
|
||||
SH_PFC_FUNCTION(i2c2),
|
||||
SH_PFC_FUNCTION(i2c6),
|
||||
SH_PFC_FUNCTION(scif0),
|
||||
SH_PFC_FUNCTION(scif1),
|
||||
SH_PFC_FUNCTION(scif2),
|
||||
|
|
|
|||
Loading…
Reference in New Issue