alinux: arm64: adjust tk_core memory layout
to #29722367 On some specific hardware with 128 bytes LLC cacheline, tk_core may cause false sharing problem. We can align it to 128 bytes so that it won't be affected by other global variables. This change will make a bit waste on cache utilization but get good number of performance improvement. So for both 64 and 128 bytes aligned LLC cacheline, we adjust tk_core memory layout to avoid potential cacheline contention. Signed-off-by: Peng Wang <rocking@linux.alibaba.com> Acked-by: Shanpei Chen <shanpeic@linux.alibaba.com> Reviewed-by: Shile Zhang <shile.zhang@linux.alibaba.com> Signed-off-by: caelli <caelli@tencent.com> Reviewed-by: yilingjin <yilingjin@tencent.com> Reviewed-by: yuehongwu <yuehongwu@tencent.com> Signed-off-by: Jianping Liu <frankjpliu@tencent.com>
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@ -1101,6 +1101,16 @@ config ARCH_HAS_CACHE_LINE_SIZE
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config ARCH_ENABLE_SPLIT_PMD_PTLOCK
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def_bool y if PGTABLE_LEVELS > 2
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config ARCH_LLC_128_WORKAROUND
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bool "Workaround for 128 bytes LLC cacheline"
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depends on ARM64
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default n
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help
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LLC cacheline size may be up to 128 bytes, and this
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is useful if you want to do workaround on such
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case. It can be used to align memory address to get
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good cache utilization et al.
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config SECCOMP
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bool "Enable seccomp to safely compute untrusted bytecode"
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---help---
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@ -666,6 +666,7 @@ CONFIG_SCSI_AIC7XXX=m
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CONFIG_SCSI_AIC79XX=m
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CONFIG_AIC79XX_CMDS_PER_DEVICE=4
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CONFIG_AIC79XX_RESET_DELAY_MS=15000
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CONFIG_ARCH_LLC_128_WORKAROUND=y
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# CONFIG_AIC79XX_DEBUG_ENABLE is not set
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# CONFIG_AIC79XX_REG_PRETTY_PRINT is not set
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CONFIG_SCSI_AIC94XX=m
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@ -46,9 +46,24 @@ enum timekeeping_adv_mode {
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* cache line.
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*/
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static struct {
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#ifdef CONFIG_ARCH_LLC_128_WORKAROUND
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/* Start seq on the middle of 128 bytes aligned address to
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* keep some members of tk_core in the same 64 bytes for
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* principle of locality while pushing others to another LLC
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* cacheline to avoid false sharing.
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*/
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u8 padding1[64];
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seqcount_t seq;
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/* Push some timekeeper memebers to another LLC cacheline */
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u8 padding2[16];
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struct timekeeper timekeeper;
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/* For 128 bytes LLC cacheline */
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} tk_core __aligned(128) = {
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#else
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seqcount_t seq;
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struct timekeeper timekeeper;
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} tk_core ____cacheline_aligned = {
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#endif
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.seq = SEQCNT_ZERO(tk_core.seq),
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};
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