drm/amd/display: Add DCN2 MPC
Add support to program the DCN2 MPC (Multiple pipe and plane combine)
HW Blocks:
+--------+
| MPC |
+--------+
|
v
+-------+
| OPP |
+-------+
|
v
+--------+
| OPTC |
+--------+
|
v
+--------+ +--------+
| DIO | | DCCG |
+--------+ +--------+
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Harry Wentland
Alex Deucher
parent
eb7a74a36c
commit
f789b0b82b
|
|
@ -194,6 +194,12 @@ enum surface_pixel_format {
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/*swaped & float*/
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SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F,
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/*grow graphics here if necessary */
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#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
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SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX,
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SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX,
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SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT,
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SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT,
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#endif
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SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
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SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr =
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SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
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@ -201,6 +207,10 @@ enum surface_pixel_format {
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SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr,
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SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb,
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SURFACE_PIXEL_FORMAT_SUBSAMPLE_END,
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#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
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SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010,
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SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102,
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#endif
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SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888,
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SURFACE_PIXEL_FORMAT_INVALID
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@ -239,6 +249,13 @@ enum tile_split_values {
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DC_ROTATED_MICRO_TILING = 0x3,
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};
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#ifdef CONFIG_DRM_AMD_DC_DCN2_0
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enum tripleBuffer_enable {
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DC_TRIPLEBUFFER_DISABLE = 0x0,
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DC_TRIPLEBUFFER_ENABLE = 0x1,
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};
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#endif
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/* TODO: These values come from hardware spec. We need to readdress this
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* if they ever change.
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*/
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@ -437,6 +454,14 @@ struct dc_csc_transform {
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bool enable_adjustment;
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};
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#ifdef CONFIG_DRM_AMD_DC_DCN2_0
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struct dc_rgb_fixed {
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struct fixed31_32 red;
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struct fixed31_32 green;
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struct fixed31_32 blue;
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};
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#endif
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struct dc_gamma {
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struct kref refcount;
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enum dc_gamma_type type;
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@ -470,7 +495,11 @@ enum dc_cursor_color_format {
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CURSOR_MODE_MONO,
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CURSOR_MODE_COLOR_1BIT_AND,
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CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA,
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CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA
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CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA,
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#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
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CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED,
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CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED
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#endif
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};
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/*
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@ -616,6 +645,10 @@ enum dc_color_depth {
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COLOR_DEPTH_121212,
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COLOR_DEPTH_141414,
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COLOR_DEPTH_161616,
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#ifdef CONFIG_DRM_AMD_DC_DCN2_0
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COLOR_DEPTH_999,
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COLOR_DEPTH_111111,
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#endif
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COLOR_DEPTH_COUNT
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};
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@ -750,6 +783,58 @@ struct dc_crtc_timing {
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struct dc_crtc_timing_flags flags;
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};
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/* Passed on init */
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enum vram_type {
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VIDEO_MEMORY_TYPE_GDDR5 = 2,
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VIDEO_MEMORY_TYPE_DDR3 = 3,
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VIDEO_MEMORY_TYPE_DDR4 = 4,
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VIDEO_MEMORY_TYPE_HBM = 5,
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VIDEO_MEMORY_TYPE_GDDR6 = 6,
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};
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#ifdef CONFIG_DRM_AMD_DC_DCN2_0
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enum dwb_cnv_out_bpc {
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DWB_CNV_OUT_BPC_8BPC = 0,
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DWB_CNV_OUT_BPC_10BPC = 1,
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};
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enum dwb_output_depth {
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DWB_OUTPUT_PIXEL_DEPTH_8BPC = 0,
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DWB_OUTPUT_PIXEL_DEPTH_10BPC = 1,
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};
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enum dwb_capture_rate {
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dwb_capture_rate_0 = 0, /* Every frame is captured. */
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dwb_capture_rate_1 = 1, /* Every other frame is captured. */
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dwb_capture_rate_2 = 2, /* Every 3rd frame is captured. */
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dwb_capture_rate_3 = 3, /* Every 4th frame is captured. */
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};
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enum dwb_scaler_mode {
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dwb_scaler_mode_bypass444 = 0,
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dwb_scaler_mode_rgb444 = 1,
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dwb_scaler_mode_yuv444 = 2,
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dwb_scaler_mode_yuv420 = 3
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};
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enum dwb_subsample_position {
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DWB_INTERSTITIAL_SUBSAMPLING = 0,
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DWB_COSITED_SUBSAMPLING = 1
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};
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#define MCIF_BUF_COUNT 4
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struct mcif_buf_params {
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unsigned long long luma_address[MCIF_BUF_COUNT];
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unsigned long long chroma_address[MCIF_BUF_COUNT];
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unsigned int luma_pitch;
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unsigned int chroma_pitch;
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unsigned int warmup_pitch;
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unsigned int swlock;
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};
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#endif
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#define MAX_TG_COLOR_VALUE 0x3FF
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struct tg_color {
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/* Maximum 10 bits color value */
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@ -438,6 +438,12 @@ static const struct mpc_funcs dcn10_mpc_funcs = {
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.assert_mpcc_idle_before_connect = mpc1_assert_mpcc_idle_before_connect,
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.init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw,
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.update_blending = mpc1_update_blending,
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#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
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.set_denorm = NULL,
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.set_denorm_clamp = NULL,
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.set_output_csc = NULL,
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.set_output_gamma = NULL,
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#endif
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};
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void dcn10_mpc_construct(struct dcn10_mpc *mpc10,
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@ -0,0 +1,526 @@
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/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dcn20_mpc.h"
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#include "reg_helper.h"
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#include "dc.h"
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#include "mem_input.h"
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#include "dcn10/dcn10_cm_common.h"
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#define REG(reg)\
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mpc20->mpc_regs->reg
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#define CTX \
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mpc20->base.ctx
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#undef FN
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#define FN(reg_name, field_name) \
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mpc20->mpc_shift->field_name, mpc20->mpc_mask->field_name
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#define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
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void mpc2_update_blending(
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struct mpc *mpc,
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struct mpcc_blnd_cfg *blnd_cfg,
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int mpcc_id)
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{
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struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
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struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id);
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REG_UPDATE_7(MPCC_CONTROL[mpcc_id],
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MPCC_ALPHA_BLND_MODE, blnd_cfg->alpha_mode,
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MPCC_ALPHA_MULTIPLIED_MODE, blnd_cfg->pre_multiplied_alpha,
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MPCC_BLND_ACTIVE_OVERLAP_ONLY, blnd_cfg->overlap_only,
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MPCC_GLOBAL_ALPHA, blnd_cfg->global_alpha,
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MPCC_GLOBAL_GAIN, blnd_cfg->global_gain,
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MPCC_BG_BPC, blnd_cfg->background_color_bpc,
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MPCC_BOT_GAIN_MODE, blnd_cfg->bottom_gain_mode);
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REG_SET(MPCC_TOP_GAIN[mpcc_id], 0, MPCC_TOP_GAIN, blnd_cfg->top_gain);
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REG_SET(MPCC_BOT_GAIN_INSIDE[mpcc_id], 0, MPCC_BOT_GAIN_INSIDE, blnd_cfg->bottom_inside_gain);
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REG_SET(MPCC_BOT_GAIN_OUTSIDE[mpcc_id], 0, MPCC_BOT_GAIN_OUTSIDE, blnd_cfg->bottom_outside_gain);
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mpc1_set_bg_color(mpc, &blnd_cfg->black_color, mpcc_id);
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mpcc->blnd_cfg = *blnd_cfg;
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}
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void mpc2_set_denorm(
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struct mpc *mpc,
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int opp_id,
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enum dc_color_depth output_depth)
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{
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struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
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int denorm_mode = 0;
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switch (output_depth) {
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case COLOR_DEPTH_666:
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denorm_mode = 1;
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break;
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case COLOR_DEPTH_888:
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denorm_mode = 2;
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break;
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case COLOR_DEPTH_999:
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denorm_mode = 3;
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break;
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case COLOR_DEPTH_101010:
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denorm_mode = 4;
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break;
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case COLOR_DEPTH_111111:
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denorm_mode = 5;
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break;
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case COLOR_DEPTH_121212:
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denorm_mode = 6;
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break;
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case COLOR_DEPTH_141414:
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case COLOR_DEPTH_161616:
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default:
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/* not valid used case! */
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break;
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}
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REG_UPDATE(DENORM_CONTROL[opp_id],
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MPC_OUT_DENORM_MODE, denorm_mode);
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}
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void mpc2_set_denorm_clamp(
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struct mpc *mpc,
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int opp_id,
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struct mpc_denorm_clamp denorm_clamp)
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{
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struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
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REG_UPDATE_2(DENORM_CONTROL[opp_id],
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MPC_OUT_DENORM_CLAMP_MAX_R_CR, denorm_clamp.clamp_max_r_cr,
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MPC_OUT_DENORM_CLAMP_MIN_R_CR, denorm_clamp.clamp_min_r_cr);
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REG_UPDATE_2(DENORM_CLAMP_G_Y[opp_id],
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MPC_OUT_DENORM_CLAMP_MAX_G_Y, denorm_clamp.clamp_max_g_y,
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MPC_OUT_DENORM_CLAMP_MIN_G_Y, denorm_clamp.clamp_min_g_y);
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REG_UPDATE_2(DENORM_CLAMP_B_CB[opp_id],
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MPC_OUT_DENORM_CLAMP_MAX_B_CB, denorm_clamp.clamp_max_b_cb,
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MPC_OUT_DENORM_CLAMP_MIN_B_CB, denorm_clamp.clamp_min_b_cb);
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}
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void mpc2_set_output_csc(
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struct mpc *mpc,
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int opp_id,
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const uint16_t *regval,
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enum mpc_output_csc_mode ocsc_mode)
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{
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struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
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struct color_matrices_reg ocsc_regs;
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REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode);
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if (ocsc_mode == MPC_OUTPUT_CSC_DISABLE)
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return;
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if (regval == NULL) {
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BREAK_TO_DEBUGGER();
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return;
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}
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ocsc_regs.shifts.csc_c11 = mpc20->mpc_shift->MPC_OCSC_C11_A;
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ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A;
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ocsc_regs.shifts.csc_c12 = mpc20->mpc_shift->MPC_OCSC_C12_A;
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ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A;
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if (ocsc_mode == MPC_OUTPUT_CSC_COEF_A) {
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ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]);
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ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]);
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} else {
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ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id]);
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ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]);
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}
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cm_helper_program_color_matrices(
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mpc20->base.ctx,
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regval,
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&ocsc_regs);
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}
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void mpc2_set_ocsc_default(
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struct mpc *mpc,
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int opp_id,
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enum dc_color_space color_space,
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enum mpc_output_csc_mode ocsc_mode)
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{
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struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
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uint32_t arr_size;
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struct color_matrices_reg ocsc_regs;
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const uint16_t *regval = NULL;
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REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode);
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if (ocsc_mode == MPC_OUTPUT_CSC_DISABLE)
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return;
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regval = find_color_matrix(color_space, &arr_size);
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if (regval == NULL) {
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BREAK_TO_DEBUGGER();
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return;
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}
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ocsc_regs.shifts.csc_c11 = mpc20->mpc_shift->MPC_OCSC_C11_A;
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ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A;
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ocsc_regs.shifts.csc_c12 = mpc20->mpc_shift->MPC_OCSC_C12_A;
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ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A;
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if (ocsc_mode == MPC_OUTPUT_CSC_COEF_A) {
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ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]);
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ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]);
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} else {
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ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id]);
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ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]);
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}
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cm_helper_program_color_matrices(
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mpc20->base.ctx,
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regval,
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&ocsc_regs);
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}
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static void mpc2_ogam_get_reg_field(
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struct mpc *mpc,
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struct xfer_func_reg *reg)
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{
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struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
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reg->shifts.exp_region0_lut_offset = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;
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reg->masks.exp_region0_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;
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reg->shifts.exp_region0_num_segments = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
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reg->masks.exp_region0_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
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reg->shifts.exp_region1_lut_offset = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;
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reg->masks.exp_region1_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;
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reg->shifts.exp_region1_num_segments = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
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reg->masks.exp_region1_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
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reg->shifts.field_region_end = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_B;
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reg->masks.field_region_end = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_B;
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reg->shifts.field_region_end_slope = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B;
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reg->masks.field_region_end_slope = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B;
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reg->shifts.field_region_end_base = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B;
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reg->masks.field_region_end_base = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B;
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reg->shifts.field_region_linear_slope = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B;
|
||||
reg->masks.field_region_linear_slope = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B;
|
||||
reg->shifts.exp_region_start = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_B;
|
||||
reg->masks.exp_region_start = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_B;
|
||||
reg->shifts.exp_resion_start_segment = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;
|
||||
reg->masks.exp_resion_start_segment = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;
|
||||
}
|
||||
|
||||
static void mpc20_power_on_ogam_lut(
|
||||
struct mpc *mpc, int mpcc_id,
|
||||
bool power_on)
|
||||
{
|
||||
struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
|
||||
|
||||
REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0,
|
||||
MPCC_OGAM_MEM_PWR_FORCE, power_on == true ? 0:1);
|
||||
|
||||
}
|
||||
|
||||
static void mpc20_configure_ogam_lut(
|
||||
struct mpc *mpc, int mpcc_id,
|
||||
bool is_ram_a)
|
||||
{
|
||||
struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
|
||||
|
||||
REG_UPDATE_2(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_id],
|
||||
MPCC_OGAM_LUT_WRITE_EN_MASK, 7,
|
||||
MPCC_OGAM_LUT_RAM_SEL, is_ram_a == true ? 0:1);
|
||||
|
||||
REG_SET(MPCC_OGAM_LUT_INDEX[mpcc_id], 0, MPCC_OGAM_LUT_INDEX, 0);
|
||||
}
|
||||
|
||||
static enum dc_lut_mode mpc20_get_ogam_current(struct mpc *mpc, int mpcc_id)
|
||||
{
|
||||
enum dc_lut_mode mode;
|
||||
uint32_t state_mode;
|
||||
struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
|
||||
|
||||
REG_GET(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_id],
|
||||
MPCC_OGAM_CONFIG_STATUS, &state_mode);
|
||||
|
||||
switch (state_mode) {
|
||||
case 0:
|
||||
mode = LUT_BYPASS;
|
||||
break;
|
||||
case 1:
|
||||
mode = LUT_RAM_A;
|
||||
break;
|
||||
case 2:
|
||||
mode = LUT_RAM_B;
|
||||
break;
|
||||
default:
|
||||
mode = LUT_BYPASS;
|
||||
break;
|
||||
}
|
||||
return mode;
|
||||
}
|
||||
|
||||
static void mpc2_program_lutb(struct mpc *mpc, int mpcc_id,
|
||||
const struct pwl_params *params)
|
||||
{
|
||||
struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
|
||||
struct xfer_func_reg gam_regs;
|
||||
|
||||
mpc2_ogam_get_reg_field(mpc, &gam_regs);
|
||||
|
||||
gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMB_START_CNTL_B[mpcc_id]);
|
||||
gam_regs.start_cntl_g = REG(MPCC_OGAM_RAMB_START_CNTL_G[mpcc_id]);
|
||||
gam_regs.start_cntl_r = REG(MPCC_OGAM_RAMB_START_CNTL_R[mpcc_id]);
|
||||
gam_regs.start_slope_cntl_b = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_B[mpcc_id]);
|
||||
gam_regs.start_slope_cntl_g = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_G[mpcc_id]);
|
||||
gam_regs.start_slope_cntl_r = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_R[mpcc_id]);
|
||||
gam_regs.start_end_cntl1_b = REG(MPCC_OGAM_RAMB_END_CNTL1_B[mpcc_id]);
|
||||
gam_regs.start_end_cntl2_b = REG(MPCC_OGAM_RAMB_END_CNTL2_B[mpcc_id]);
|
||||
gam_regs.start_end_cntl1_g = REG(MPCC_OGAM_RAMB_END_CNTL1_G[mpcc_id]);
|
||||
gam_regs.start_end_cntl2_g = REG(MPCC_OGAM_RAMB_END_CNTL2_G[mpcc_id]);
|
||||
gam_regs.start_end_cntl1_r = REG(MPCC_OGAM_RAMB_END_CNTL1_R[mpcc_id]);
|
||||
gam_regs.start_end_cntl2_r = REG(MPCC_OGAM_RAMB_END_CNTL2_R[mpcc_id]);
|
||||
gam_regs.region_start = REG(MPCC_OGAM_RAMB_REGION_0_1[mpcc_id]);
|
||||
gam_regs.region_end = REG(MPCC_OGAM_RAMB_REGION_32_33[mpcc_id]);
|
||||
|
||||
cm_helper_program_xfer_func(mpc20->base.ctx, params, &gam_regs);
|
||||
|
||||
}
|
||||
|
||||
static void mpc2_program_luta(struct mpc *mpc, int mpcc_id,
|
||||
const struct pwl_params *params)
|
||||
{
|
||||
struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
|
||||
struct xfer_func_reg gam_regs;
|
||||
|
||||
mpc2_ogam_get_reg_field(mpc, &gam_regs);
|
||||
|
||||
gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMA_START_CNTL_B[mpcc_id]);
|
||||
gam_regs.start_cntl_g = REG(MPCC_OGAM_RAMA_START_CNTL_G[mpcc_id]);
|
||||
gam_regs.start_cntl_r = REG(MPCC_OGAM_RAMA_START_CNTL_R[mpcc_id]);
|
||||
gam_regs.start_slope_cntl_b = REG(MPCC_OGAM_RAMA_SLOPE_CNTL_B[mpcc_id]);
|
||||
gam_regs.start_slope_cntl_g = REG(MPCC_OGAM_RAMA_SLOPE_CNTL_G[mpcc_id]);
|
||||
gam_regs.start_slope_cntl_r = REG(MPCC_OGAM_RAMA_SLOPE_CNTL_R[mpcc_id]);
|
||||
gam_regs.start_end_cntl1_b = REG(MPCC_OGAM_RAMA_END_CNTL1_B[mpcc_id]);
|
||||
gam_regs.start_end_cntl2_b = REG(MPCC_OGAM_RAMA_END_CNTL2_B[mpcc_id]);
|
||||
gam_regs.start_end_cntl1_g = REG(MPCC_OGAM_RAMA_END_CNTL1_G[mpcc_id]);
|
||||
gam_regs.start_end_cntl2_g = REG(MPCC_OGAM_RAMA_END_CNTL2_G[mpcc_id]);
|
||||
gam_regs.start_end_cntl1_r = REG(MPCC_OGAM_RAMA_END_CNTL1_R[mpcc_id]);
|
||||
gam_regs.start_end_cntl2_r = REG(MPCC_OGAM_RAMA_END_CNTL2_R[mpcc_id]);
|
||||
gam_regs.region_start = REG(MPCC_OGAM_RAMA_REGION_0_1[mpcc_id]);
|
||||
gam_regs.region_end = REG(MPCC_OGAM_RAMA_REGION_32_33[mpcc_id]);
|
||||
|
||||
cm_helper_program_xfer_func(mpc20->base.ctx, params, &gam_regs);
|
||||
|
||||
}
|
||||
|
||||
static void mpc20_program_ogam_pwl(
|
||||
struct mpc *mpc, int mpcc_id,
|
||||
const struct pwl_result_data *rgb,
|
||||
uint32_t num)
|
||||
{
|
||||
uint32_t i;
|
||||
struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
|
||||
|
||||
for (i = 0 ; i < num; i++) {
|
||||
REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].red_reg);
|
||||
REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].green_reg);
|
||||
REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].blue_reg);
|
||||
|
||||
REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0,
|
||||
MPCC_OGAM_LUT_DATA, rgb[i].delta_red_reg);
|
||||
REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0,
|
||||
MPCC_OGAM_LUT_DATA, rgb[i].delta_green_reg);
|
||||
REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0,
|
||||
MPCC_OGAM_LUT_DATA, rgb[i].delta_blue_reg);
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void apply_DEDCN20_305_wa(
|
||||
struct mpc *mpc,
|
||||
int mpcc_id, enum dc_lut_mode current_mode,
|
||||
enum dc_lut_mode next_mode)
|
||||
{
|
||||
struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
|
||||
|
||||
if (mpc->ctx->dc->work_arounds.dedcn20_305_wa == false) {
|
||||
/*hw fixed in new review*/
|
||||
return;
|
||||
}
|
||||
if (current_mode == LUT_BYPASS)
|
||||
/*this will only work if OTG is locked.
|
||||
*if we were to support OTG unlock case,
|
||||
*the workaround will be more complex
|
||||
*/
|
||||
REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE,
|
||||
next_mode == LUT_RAM_A ? 1:2);
|
||||
}
|
||||
|
||||
void mpc2_set_output_gamma(
|
||||
struct mpc *mpc,
|
||||
int mpcc_id,
|
||||
const struct pwl_params *params)
|
||||
{
|
||||
enum dc_lut_mode current_mode;
|
||||
enum dc_lut_mode next_mode;
|
||||
struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
|
||||
|
||||
if (params == NULL) {
|
||||
REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0);
|
||||
return;
|
||||
}
|
||||
current_mode = mpc20_get_ogam_current(mpc, mpcc_id);
|
||||
if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
|
||||
next_mode = LUT_RAM_B;
|
||||
else
|
||||
next_mode = LUT_RAM_A;
|
||||
|
||||
mpc20_power_on_ogam_lut(mpc, mpcc_id, true);
|
||||
mpc20_configure_ogam_lut(mpc, mpcc_id, next_mode == LUT_RAM_A ? true:false);
|
||||
|
||||
if (next_mode == LUT_RAM_A)
|
||||
mpc2_program_luta(mpc, mpcc_id, params);
|
||||
else
|
||||
mpc2_program_lutb(mpc, mpcc_id, params);
|
||||
|
||||
apply_DEDCN20_305_wa(mpc, mpcc_id, current_mode, next_mode);
|
||||
|
||||
mpc20_program_ogam_pwl(
|
||||
mpc, mpcc_id, params->rgb_resulted, params->hw_points_num);
|
||||
|
||||
REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE,
|
||||
next_mode == LUT_RAM_A ? 1:2);
|
||||
}
|
||||
void mpc2_assert_idle_mpcc(struct mpc *mpc, int id)
|
||||
{
|
||||
struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
|
||||
unsigned int mpc_disabled;
|
||||
|
||||
ASSERT(!(mpc20->mpcc_in_use_mask & 1 << id));
|
||||
REG_GET(MPCC_STATUS[id], MPCC_DISABLED, &mpc_disabled);
|
||||
if (mpc_disabled)
|
||||
return;
|
||||
|
||||
REG_WAIT(MPCC_STATUS[id],
|
||||
MPCC_IDLE, 1,
|
||||
1, 100000);
|
||||
}
|
||||
|
||||
void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id)
|
||||
{
|
||||
struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
|
||||
unsigned int top_sel, mpc_busy, mpc_idle, mpc_disabled;
|
||||
REG_GET(MPCC_STATUS[mpcc_id], MPCC_DISABLED, &mpc_disabled);
|
||||
|
||||
if (mpc_disabled) {
|
||||
ASSERT(0);
|
||||
return;
|
||||
}
|
||||
|
||||
REG_GET(MPCC_TOP_SEL[mpcc_id],
|
||||
MPCC_TOP_SEL, &top_sel);
|
||||
|
||||
if (top_sel == 0xf) {
|
||||
REG_GET_2(MPCC_STATUS[mpcc_id],
|
||||
MPCC_BUSY, &mpc_busy,
|
||||
MPCC_IDLE, &mpc_idle);
|
||||
|
||||
ASSERT(mpc_busy == 0);
|
||||
ASSERT(mpc_idle == 1);
|
||||
}
|
||||
}
|
||||
|
||||
static void mpc2_init_mpcc(struct mpcc *mpcc, int mpcc_inst)
|
||||
{
|
||||
mpcc->mpcc_id = mpcc_inst;
|
||||
mpcc->dpp_id = 0xf;
|
||||
mpcc->mpcc_bot = NULL;
|
||||
mpcc->blnd_cfg.overlap_only = false;
|
||||
mpcc->blnd_cfg.global_alpha = 0xff;
|
||||
mpcc->blnd_cfg.global_gain = 0xff;
|
||||
mpcc->blnd_cfg.background_color_bpc = 4;
|
||||
mpcc->blnd_cfg.bottom_gain_mode = 0;
|
||||
mpcc->blnd_cfg.top_gain = 0x1f000;
|
||||
mpcc->blnd_cfg.bottom_inside_gain = 0x1f000;
|
||||
mpcc->blnd_cfg.bottom_outside_gain = 0x1f000;
|
||||
mpcc->sm_cfg.enable = false;
|
||||
}
|
||||
|
||||
struct mpcc *mpc2_get_mpcc_for_dpp(struct mpc_tree *tree, int dpp_id)
|
||||
{
|
||||
struct mpcc *tmp_mpcc = tree->opp_list;
|
||||
|
||||
while (tmp_mpcc != NULL) {
|
||||
if (tmp_mpcc->dpp_id == 0xf || tmp_mpcc->dpp_id == dpp_id)
|
||||
return tmp_mpcc;
|
||||
tmp_mpcc = tmp_mpcc->mpcc_bot;
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
const struct mpc_funcs dcn20_mpc_funcs = {
|
||||
.read_mpcc_state = mpc1_read_mpcc_state,
|
||||
.insert_plane = mpc1_insert_plane,
|
||||
.remove_mpcc = mpc1_remove_mpcc,
|
||||
.mpc_init = mpc1_mpc_init,
|
||||
.update_blending = mpc2_update_blending,
|
||||
.get_mpcc_for_dpp = mpc2_get_mpcc_for_dpp,
|
||||
.wait_for_idle = mpc2_assert_idle_mpcc,
|
||||
.assert_mpcc_idle_before_connect = mpc2_assert_mpcc_idle_before_connect,
|
||||
.init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw,
|
||||
.set_denorm = mpc2_set_denorm,
|
||||
.set_denorm_clamp = mpc2_set_denorm_clamp,
|
||||
.set_output_csc = mpc2_set_output_csc,
|
||||
.set_ocsc_default = mpc2_set_ocsc_default,
|
||||
.set_output_gamma = mpc2_set_output_gamma,
|
||||
};
|
||||
|
||||
void dcn20_mpc_construct(struct dcn20_mpc *mpc20,
|
||||
struct dc_context *ctx,
|
||||
const struct dcn20_mpc_registers *mpc_regs,
|
||||
const struct dcn20_mpc_shift *mpc_shift,
|
||||
const struct dcn20_mpc_mask *mpc_mask,
|
||||
int num_mpcc)
|
||||
{
|
||||
int i;
|
||||
|
||||
mpc20->base.ctx = ctx;
|
||||
|
||||
mpc20->base.funcs = &dcn20_mpc_funcs;
|
||||
|
||||
mpc20->mpc_regs = mpc_regs;
|
||||
mpc20->mpc_shift = mpc_shift;
|
||||
mpc20->mpc_mask = mpc_mask;
|
||||
|
||||
mpc20->mpcc_in_use_mask = 0;
|
||||
mpc20->num_mpcc = num_mpcc;
|
||||
|
||||
for (i = 0; i < MAX_MPCC; i++)
|
||||
mpc2_init_mpcc(&mpc20->base.mpcc_array[i], i);
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,285 @@
|
|||
/* Copyright 2012-15 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: AMD
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DC_MPCC_DCN20_H__
|
||||
#define __DC_MPCC_DCN20_H__
|
||||
|
||||
#include "dcn10/dcn10_mpc.h"
|
||||
|
||||
#define TO_DCN20_MPC(mpc_base) \
|
||||
container_of(mpc_base, struct dcn20_mpc, base)
|
||||
|
||||
#define MPC_REG_LIST_DCN2_0(inst)\
|
||||
MPC_COMMON_REG_LIST_DCN1_0(inst),\
|
||||
SRII(MPCC_TOP_GAIN, MPCC, inst),\
|
||||
SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\
|
||||
SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst),\
|
||||
SRII(MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM, inst),\
|
||||
SRII(MPCC_OGAM_RAMA_START_CNTL_G, MPCC_OGAM, inst),\
|
||||
SRII(MPCC_OGAM_RAMA_START_CNTL_R, MPCC_OGAM, inst),\
|
||||
SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_B, MPCC_OGAM, inst),\
|
||||
SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_G, MPCC_OGAM, inst),\
|
||||
SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_R, MPCC_OGAM, inst),\
|
||||
SRII(MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM, inst),\
|
||||
SRII(MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM, inst),\
|
||||
SRII(MPCC_OGAM_RAMA_END_CNTL1_G, MPCC_OGAM, inst),\
|
||||
SRII(MPCC_OGAM_RAMA_END_CNTL2_G, MPCC_OGAM, inst),\
|
||||
SRII(MPCC_OGAM_RAMA_END_CNTL1_R, MPCC_OGAM, inst),\
|
||||
SRII(MPCC_OGAM_RAMA_END_CNTL2_R, MPCC_OGAM, inst),\
|
||||
SRII(MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM, inst),\
|
||||
SRII(MPCC_OGAM_RAMA_REGION_32_33, MPCC_OGAM, inst),\
|
||||
SRII(MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM, inst),\
|
||||
SRII(MPCC_OGAM_RAMB_START_CNTL_G, MPCC_OGAM, inst),\
|
||||
SRII(MPCC_OGAM_RAMB_START_CNTL_R, MPCC_OGAM, inst),\
|
||||
SRII(MPCC_OGAM_RAMB_SLOPE_CNTL_B, MPCC_OGAM, inst),\
|
||||
SRII(MPCC_OGAM_RAMB_SLOPE_CNTL_G, MPCC_OGAM, inst),\
|
||||
SRII(MPCC_OGAM_RAMB_SLOPE_CNTL_R, MPCC_OGAM, inst),\
|
||||
SRII(MPCC_OGAM_RAMB_END_CNTL1_B, MPCC_OGAM, inst),\
|
||||
SRII(MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM, inst),\
|
||||
SRII(MPCC_OGAM_RAMB_END_CNTL1_G, MPCC_OGAM, inst),\
|
||||
SRII(MPCC_OGAM_RAMB_END_CNTL2_G, MPCC_OGAM, inst),\
|
||||
SRII(MPCC_OGAM_RAMB_END_CNTL1_R, MPCC_OGAM, inst),\
|
||||
SRII(MPCC_OGAM_RAMB_END_CNTL2_R, MPCC_OGAM, inst),\
|
||||
SRII(MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM, inst),\
|
||||
SRII(MPCC_OGAM_RAMB_REGION_32_33, MPCC_OGAM, inst),\
|
||||
SRII(MPCC_MEM_PWR_CTRL, MPCC, inst),\
|
||||
SRII(MPCC_OGAM_LUT_INDEX, MPCC_OGAM, inst),\
|
||||
SRII(MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM, inst),\
|
||||
SRII(MPCC_OGAM_LUT_DATA, MPCC_OGAM, inst),\
|
||||
SRII(MPCC_OGAM_MODE, MPCC_OGAM, inst)
|
||||
|
||||
#define MPC_OUT_MUX_REG_LIST_DCN2_0(inst) \
|
||||
MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(inst),\
|
||||
SRII(CSC_MODE, MPC_OUT, inst),\
|
||||
SRII(CSC_C11_C12_A, MPC_OUT, inst),\
|
||||
SRII(CSC_C33_C34_A, MPC_OUT, inst),\
|
||||
SRII(CSC_C11_C12_B, MPC_OUT, inst),\
|
||||
SRII(CSC_C33_C34_B, MPC_OUT, inst),\
|
||||
SRII(DENORM_CONTROL, MPC_OUT, inst),\
|
||||
SRII(DENORM_CLAMP_G_Y, MPC_OUT, inst),\
|
||||
SRII(DENORM_CLAMP_B_CB, MPC_OUT, inst)
|
||||
|
||||
#define MPC_REG_VARIABLE_LIST_DCN2_0 \
|
||||
MPC_COMMON_REG_VARIABLE_LIST \
|
||||
uint32_t MPCC_TOP_GAIN[MAX_MPCC]; \
|
||||
uint32_t MPCC_BOT_GAIN_INSIDE[MAX_MPCC]; \
|
||||
uint32_t MPCC_BOT_GAIN_OUTSIDE[MAX_MPCC]; \
|
||||
uint32_t MPCC_OGAM_RAMA_START_CNTL_B[MAX_MPCC]; \
|
||||
uint32_t MPCC_OGAM_RAMA_START_CNTL_G[MAX_MPCC]; \
|
||||
uint32_t MPCC_OGAM_RAMA_START_CNTL_R[MAX_MPCC]; \
|
||||
uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_B[MAX_MPCC]; \
|
||||
uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_G[MAX_MPCC]; \
|
||||
uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_R[MAX_MPCC]; \
|
||||
uint32_t MPCC_OGAM_RAMA_END_CNTL1_B[MAX_MPCC]; \
|
||||
uint32_t MPCC_OGAM_RAMA_END_CNTL2_B[MAX_MPCC]; \
|
||||
uint32_t MPCC_OGAM_RAMA_END_CNTL1_G[MAX_MPCC]; \
|
||||
uint32_t MPCC_OGAM_RAMA_END_CNTL2_G[MAX_MPCC]; \
|
||||
uint32_t MPCC_OGAM_RAMA_END_CNTL1_R[MAX_MPCC]; \
|
||||
uint32_t MPCC_OGAM_RAMA_END_CNTL2_R[MAX_MPCC]; \
|
||||
uint32_t MPCC_OGAM_RAMA_REGION_0_1[MAX_MPCC]; \
|
||||
uint32_t MPCC_OGAM_RAMA_REGION_32_33[MAX_MPCC]; \
|
||||
uint32_t MPCC_OGAM_RAMB_START_CNTL_B[MAX_MPCC]; \
|
||||
uint32_t MPCC_OGAM_RAMB_START_CNTL_G[MAX_MPCC]; \
|
||||
uint32_t MPCC_OGAM_RAMB_START_CNTL_R[MAX_MPCC]; \
|
||||
uint32_t MPCC_OGAM_RAMB_SLOPE_CNTL_B[MAX_MPCC]; \
|
||||
uint32_t MPCC_OGAM_RAMB_SLOPE_CNTL_G[MAX_MPCC]; \
|
||||
uint32_t MPCC_OGAM_RAMB_SLOPE_CNTL_R[MAX_MPCC]; \
|
||||
uint32_t MPCC_OGAM_RAMB_END_CNTL1_B[MAX_MPCC]; \
|
||||
uint32_t MPCC_OGAM_RAMB_END_CNTL2_B[MAX_MPCC]; \
|
||||
uint32_t MPCC_OGAM_RAMB_END_CNTL1_G[MAX_MPCC]; \
|
||||
uint32_t MPCC_OGAM_RAMB_END_CNTL2_G[MAX_MPCC]; \
|
||||
uint32_t MPCC_OGAM_RAMB_END_CNTL1_R[MAX_MPCC]; \
|
||||
uint32_t MPCC_OGAM_RAMB_END_CNTL2_R[MAX_MPCC]; \
|
||||
uint32_t MPCC_OGAM_RAMB_REGION_0_1[MAX_MPCC]; \
|
||||
uint32_t MPCC_OGAM_RAMB_REGION_32_33[MAX_MPCC];\
|
||||
uint32_t MPCC_MEM_PWR_CTRL[MAX_MPCC];\
|
||||
uint32_t MPCC_OGAM_LUT_INDEX[MAX_MPCC];\
|
||||
uint32_t MPCC_OGAM_LUT_RAM_CONTROL[MAX_MPCC];\
|
||||
uint32_t MPCC_OGAM_LUT_DATA[MAX_MPCC];\
|
||||
uint32_t MPCC_OGAM_MODE[MAX_MPCC];\
|
||||
uint32_t CSC_MODE[MAX_OPP]; \
|
||||
uint32_t CSC_C11_C12_A[MAX_OPP]; \
|
||||
uint32_t CSC_C33_C34_A[MAX_OPP]; \
|
||||
uint32_t CSC_C11_C12_B[MAX_OPP]; \
|
||||
uint32_t CSC_C33_C34_B[MAX_OPP]; \
|
||||
uint32_t DENORM_CONTROL[MAX_OPP]; \
|
||||
uint32_t DENORM_CLAMP_G_Y[MAX_OPP]; \
|
||||
uint32_t DENORM_CLAMP_B_CB[MAX_OPP];
|
||||
|
||||
#define MPC_COMMON_MASK_SH_LIST_DCN2_0(mask_sh) \
|
||||
MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh),\
|
||||
SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
|
||||
SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\
|
||||
SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
|
||||
SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\
|
||||
SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\
|
||||
SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
|
||||
SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
|
||||
SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\
|
||||
SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\
|
||||
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
|
||||
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
|
||||
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
|
||||
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
|
||||
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\
|
||||
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\
|
||||
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
|
||||
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh),\
|
||||
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\
|
||||
SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
|
||||
SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh),\
|
||||
SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
|
||||
SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh),\
|
||||
SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
|
||||
SF(MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B, MPCC_OGAM_RAMB_EXP_REGION_END_B, mask_sh),\
|
||||
SF(MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh),\
|
||||
SF(MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh),\
|
||||
SF(MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh),\
|
||||
SF(MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_START_B, mask_sh),\
|
||||
SF(MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh),\
|
||||
SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\
|
||||
SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\
|
||||
SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_LUT_WRITE_EN_MASK, mask_sh),\
|
||||
SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_LUT_RAM_SEL, mask_sh),\
|
||||
SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_CONFIG_STATUS, mask_sh),\
|
||||
SF(MPCC_OGAM0_MPCC_OGAM_LUT_DATA, MPCC_OGAM_LUT_DATA, mask_sh),\
|
||||
SF(MPCC_OGAM0_MPCC_OGAM_MODE, MPCC_OGAM_MODE, mask_sh),\
|
||||
SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\
|
||||
SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\
|
||||
SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\
|
||||
SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\
|
||||
SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\
|
||||
SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\
|
||||
SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh)
|
||||
|
||||
#define MPC_REG_FIELD_LIST_DCN2_0(type) \
|
||||
MPC_REG_FIELD_LIST(type)\
|
||||
type MPCC_BG_BPC;\
|
||||
type MPCC_BOT_GAIN_MODE;\
|
||||
type MPCC_TOP_GAIN;\
|
||||
type MPCC_BOT_GAIN_INSIDE;\
|
||||
type MPCC_BOT_GAIN_OUTSIDE;\
|
||||
type MPC_OCSC_MODE;\
|
||||
type MPC_OCSC_C11_A;\
|
||||
type MPC_OCSC_C12_A;\
|
||||
type MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;\
|
||||
type MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;\
|
||||
type MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;\
|
||||
type MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;\
|
||||
type MPCC_OGAM_RAMA_EXP_REGION_END_B;\
|
||||
type MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B;\
|
||||
type MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B;\
|
||||
type MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B;\
|
||||
type MPCC_OGAM_RAMA_EXP_REGION_START_B;\
|
||||
type MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;\
|
||||
type MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET;\
|
||||
type MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS;\
|
||||
type MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET;\
|
||||
type MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS;\
|
||||
type MPCC_OGAM_RAMB_EXP_REGION_END_B;\
|
||||
type MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B;\
|
||||
type MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B;\
|
||||
type MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;\
|
||||
type MPCC_OGAM_RAMB_EXP_REGION_START_B;\
|
||||
type MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B;\
|
||||
type MPCC_OGAM_MEM_PWR_FORCE;\
|
||||
type MPCC_OGAM_LUT_INDEX;\
|
||||
type MPCC_OGAM_LUT_WRITE_EN_MASK;\
|
||||
type MPCC_OGAM_LUT_RAM_SEL;\
|
||||
type MPCC_OGAM_CONFIG_STATUS;\
|
||||
type MPCC_OGAM_LUT_DATA;\
|
||||
type MPCC_OGAM_MODE;\
|
||||
type MPC_OUT_DENORM_MODE;\
|
||||
type MPC_OUT_DENORM_CLAMP_MAX_R_CR;\
|
||||
type MPC_OUT_DENORM_CLAMP_MIN_R_CR;\
|
||||
type MPC_OUT_DENORM_CLAMP_MAX_G_Y;\
|
||||
type MPC_OUT_DENORM_CLAMP_MIN_G_Y;\
|
||||
type MPC_OUT_DENORM_CLAMP_MAX_B_CB;\
|
||||
type MPC_OUT_DENORM_CLAMP_MIN_B_CB;\
|
||||
type MPCC_DISABLED;
|
||||
|
||||
struct dcn20_mpc_registers {
|
||||
MPC_REG_VARIABLE_LIST_DCN2_0
|
||||
};
|
||||
|
||||
struct dcn20_mpc_shift {
|
||||
MPC_REG_FIELD_LIST_DCN2_0(uint8_t)
|
||||
};
|
||||
|
||||
struct dcn20_mpc_mask {
|
||||
MPC_REG_FIELD_LIST_DCN2_0(uint32_t)
|
||||
};
|
||||
|
||||
struct dcn20_mpc {
|
||||
struct mpc base;
|
||||
|
||||
int mpcc_in_use_mask;
|
||||
int num_mpcc;
|
||||
const struct dcn20_mpc_registers *mpc_regs;
|
||||
const struct dcn20_mpc_shift *mpc_shift;
|
||||
const struct dcn20_mpc_mask *mpc_mask;
|
||||
};
|
||||
|
||||
void dcn20_mpc_construct(struct dcn20_mpc *mpcc20,
|
||||
struct dc_context *ctx,
|
||||
const struct dcn20_mpc_registers *mpc_regs,
|
||||
const struct dcn20_mpc_shift *mpc_shift,
|
||||
const struct dcn20_mpc_mask *mpc_mask,
|
||||
int num_mpcc);
|
||||
|
||||
void mpc2_update_blending(
|
||||
struct mpc *mpc,
|
||||
struct mpcc_blnd_cfg *blnd_cfg,
|
||||
int mpcc_id);
|
||||
|
||||
void mpc2_set_denorm(
|
||||
struct mpc *mpc,
|
||||
int opp_id,
|
||||
enum dc_color_depth output_depth);
|
||||
|
||||
void mpc2_set_denorm_clamp(
|
||||
struct mpc *mpc,
|
||||
int opp_id,
|
||||
struct mpc_denorm_clamp denorm_clamp);
|
||||
|
||||
void mpc2_set_output_csc(
|
||||
struct mpc *mpc,
|
||||
int opp_id,
|
||||
const uint16_t *regval,
|
||||
enum mpc_output_csc_mode ocsc_mode);
|
||||
|
||||
void mpc2_set_ocsc_default(
|
||||
struct mpc *mpc,
|
||||
int opp_id,
|
||||
enum dc_color_space color_space,
|
||||
enum mpc_output_csc_mode ocsc_mode);
|
||||
|
||||
void mpc2_set_output_gamma(
|
||||
struct mpc *mpc,
|
||||
int mpcc_id,
|
||||
const struct pwl_params *params);
|
||||
|
||||
void mpc2_assert_idle_mpcc(struct mpc *mpc, int id);
|
||||
void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id);
|
||||
#endif
|
||||
|
|
@ -31,6 +31,10 @@
|
|||
#define MAX_MPCC 6
|
||||
#define MAX_OPP 6
|
||||
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
|
||||
#define MAX_DWB 1
|
||||
#endif
|
||||
|
||||
enum mpc_output_csc_mode {
|
||||
MPC_OUTPUT_CSC_DISABLE = 0,
|
||||
MPC_OUTPUT_CSC_COEF_A,
|
||||
|
|
@ -62,6 +66,14 @@ struct mpcc_blnd_cfg {
|
|||
int global_alpha;
|
||||
bool overlap_only;
|
||||
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
|
||||
/* MPCC top/bottom gain settings */
|
||||
int bottom_gain_mode;
|
||||
int background_color_bpc;
|
||||
int top_gain;
|
||||
int bottom_inside_gain;
|
||||
int bottom_outside_gain;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct mpcc_sm_cfg {
|
||||
|
|
@ -78,6 +90,17 @@ struct mpcc_sm_cfg {
|
|||
int force_next_field_polarity;
|
||||
};
|
||||
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
|
||||
struct mpc_denorm_clamp {
|
||||
int clamp_max_r_cr;
|
||||
int clamp_min_r_cr;
|
||||
int clamp_max_g_y;
|
||||
int clamp_min_g_y;
|
||||
int clamp_max_b_cb;
|
||||
int clamp_min_b_cb;
|
||||
};
|
||||
#endif
|
||||
|
||||
/*
|
||||
* MPCC connection and blending configuration for a single MPCC instance.
|
||||
* This struct is used as a node in an MPC tree.
|
||||
|
|
@ -103,6 +126,9 @@ struct mpc {
|
|||
struct dc_context *ctx;
|
||||
|
||||
struct mpcc mpcc_array[MAX_MPCC];
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
|
||||
struct pwl_params blender_params;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct mpcc_state {
|
||||
|
|
@ -200,6 +226,32 @@ struct mpc_funcs {
|
|||
struct mpc *mpc,
|
||||
struct mpc_tree *tree);
|
||||
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
|
||||
void (*set_denorm)(struct mpc *mpc,
|
||||
int opp_id,
|
||||
enum dc_color_depth output_depth);
|
||||
|
||||
void (*set_denorm_clamp)(
|
||||
struct mpc *mpc,
|
||||
int opp_id,
|
||||
struct mpc_denorm_clamp denorm_clamp);
|
||||
|
||||
void (*set_output_csc)(struct mpc *mpc,
|
||||
int opp_id,
|
||||
const uint16_t *regval,
|
||||
enum mpc_output_csc_mode ocsc_mode);
|
||||
|
||||
void (*set_ocsc_default)(struct mpc *mpc,
|
||||
int opp_id,
|
||||
enum dc_color_space color_space,
|
||||
enum mpc_output_csc_mode ocsc_mode);
|
||||
|
||||
void (*set_output_gamma)(
|
||||
struct mpc *mpc,
|
||||
int mpcc_id,
|
||||
const struct pwl_params *params);
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue