drm/amdgpu/gfx8: wait for completion in KIQ init
We need to make sure the various init sequences submitted to KIQ complete before testing the rings. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -4639,9 +4639,25 @@ static void gfx_v8_0_kiq_setting(struct amdgpu_ring *ring)
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WREG32(mmRLC_CP_SCHEDULERS, tmp);
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}
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static void gfx_v8_0_kiq_enable(struct amdgpu_ring *ring)
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static int gfx_v8_0_kiq_enable(struct amdgpu_ring *ring)
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{
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amdgpu_ring_alloc(ring, 8);
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struct amdgpu_device *adev = ring->adev;
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uint32_t scratch, tmp = 0;
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int r, i;
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r = amdgpu_gfx_scratch_get(adev, &scratch);
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if (r) {
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DRM_ERROR("Failed to get scratch reg (%d).\n", r);
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return r;
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}
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WREG32(scratch, 0xCAFEDEAD);
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r = amdgpu_ring_alloc(ring, 11);
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if (r) {
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DRM_ERROR("Failed to lock KIQ (%d).\n", r);
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amdgpu_gfx_scratch_free(adev, scratch);
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return r;
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}
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/* set resources */
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amdgpu_ring_write(ring, PACKET3(PACKET3_SET_RESOURCES, 6));
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amdgpu_ring_write(ring, 0); /* vmid_mask:0 queue_type:0 (KIQ) */
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@ -4651,20 +4667,53 @@ static void gfx_v8_0_kiq_enable(struct amdgpu_ring *ring)
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amdgpu_ring_write(ring, 0); /* gws mask hi */
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amdgpu_ring_write(ring, 0); /* oac mask */
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amdgpu_ring_write(ring, 0); /* gds heap base:0, gds heap size:0 */
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/* write to scratch for completion */
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amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
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amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
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amdgpu_ring_write(ring, 0xDEADBEEF);
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amdgpu_ring_commit(ring);
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udelay(50);
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for (i = 0; i < adev->usec_timeout; i++) {
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tmp = RREG32(scratch);
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if (tmp == 0xDEADBEEF)
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break;
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DRM_UDELAY(1);
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}
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if (i >= adev->usec_timeout) {
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DRM_ERROR("KIQ enable failed (scratch(0x%04X)=0x%08X)\n",
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scratch, tmp);
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r = -EINVAL;
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}
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amdgpu_gfx_scratch_free(adev, scratch);
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return r;
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}
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static void gfx_v8_0_map_queue_enable(struct amdgpu_ring *kiq_ring,
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struct amdgpu_ring *ring)
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static int gfx_v8_0_map_queue_enable(struct amdgpu_ring *kiq_ring,
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struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = kiq_ring->adev;
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uint64_t mqd_addr, wptr_addr;
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uint32_t scratch, tmp = 0;
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int r, i;
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r = amdgpu_gfx_scratch_get(adev, &scratch);
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if (r) {
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DRM_ERROR("Failed to get scratch reg (%d).\n", r);
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return r;
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}
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WREG32(scratch, 0xCAFEDEAD);
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mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
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wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
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amdgpu_ring_alloc(kiq_ring, 8);
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r = amdgpu_ring_alloc(kiq_ring, 11);
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if (r) {
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DRM_ERROR("Failed to lock KIQ (%d).\n", r);
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amdgpu_gfx_scratch_free(adev, scratch);
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return r;
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}
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/* map queues */
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amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
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/* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
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amdgpu_ring_write(kiq_ring, 0x21010000);
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@ -4676,8 +4725,26 @@ static void gfx_v8_0_map_queue_enable(struct amdgpu_ring *kiq_ring,
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amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
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amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
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amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
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/* write to scratch for completion */
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amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
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amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
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amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
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amdgpu_ring_commit(kiq_ring);
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udelay(50);
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for (i = 0; i < adev->usec_timeout; i++) {
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tmp = RREG32(scratch);
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if (tmp == 0xDEADBEEF)
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break;
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DRM_UDELAY(1);
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}
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if (i >= adev->usec_timeout) {
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DRM_ERROR("KCQ %d enable failed (scratch(0x%04X)=0x%08X)\n",
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ring->idx, scratch, tmp);
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r = -EINVAL;
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}
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amdgpu_gfx_scratch_free(adev, scratch);
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return r;
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}
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static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
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@ -4903,6 +4970,7 @@ static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring)
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struct vi_mqd *mqd = ring->mqd_ptr;
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bool is_kiq = (ring->funcs->type == AMDGPU_RING_TYPE_KIQ);
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int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
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int r;
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if (is_kiq) {
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gfx_v8_0_kiq_setting(&kiq->ring);
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@ -4941,11 +5009,11 @@ static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring)
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}
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if (is_kiq)
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gfx_v8_0_kiq_enable(ring);
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r = gfx_v8_0_kiq_enable(ring);
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else
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gfx_v8_0_map_queue_enable(&kiq->ring, ring);
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r = gfx_v8_0_map_queue_enable(&kiq->ring, ring);
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return 0;
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return r;
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}
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static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev)
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