arm64: Add ARM64_WORKAROUND_1319367 for all A57 and A72 versions
Rework the EL2 vector hardening that is only selected for A57 and A72 so that the table can also be used for ARM64_WORKAROUND_1319367. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org>
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@ -52,7 +52,8 @@
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#define ARM64_HAS_IRQ_PRIO_MASKING 42
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#define ARM64_HAS_DCPODP 43
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#define ARM64_WORKAROUND_1463225 44
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#define ARM64_WORKAROUND_1319367 45
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#define ARM64_NCAPS 45
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#define ARM64_NCAPS 46
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#endif /* __ASM_CPUCAPS_H */
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@ -623,9 +623,9 @@ check_branch_predictor(const struct arm64_cpu_capabilities *entry, int scope)
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return (need_wa > 0);
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}
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#ifdef CONFIG_HARDEN_EL2_VECTORS
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#if defined(CONFIG_HARDEN_EL2_VECTORS) || defined(CONFIG_ARM64_ERRATUM_1319367)
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static const struct midr_range arm64_harden_el2_vectors[] = {
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static const struct midr_range ca57_a72[] = {
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
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{},
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@ -819,7 +819,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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{
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.desc = "EL2 vector hardening",
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.capability = ARM64_HARDEN_EL2_VECTORS,
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ERRATA_MIDR_RANGE_LIST(arm64_harden_el2_vectors),
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ERRATA_MIDR_RANGE_LIST(ca57_a72),
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},
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#endif
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{
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@ -851,6 +851,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
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.matches = has_cortex_a76_erratum_1463225,
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_1319367
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{
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.desc = "ARM erratum 1319367",
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.capability = ARM64_WORKAROUND_1319367,
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ERRATA_MIDR_RANGE_LIST(ca57_a72),
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},
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#endif
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{
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}
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