TI K3 device tree updates for v6.3
New features: J784S4 SoC and EVM support AM68 and AM69 StarterKit, phyBOARD-Electra-AM642, Siemens IoT2050 M.2 AM62A7 SK additional peripherals AM62 SK USB support Non critical fixes AM62: McSPI Clock ID fixes MMC TAP value updates J7200: pinmux range update All: Cache DT node fixes Cleanups: Reorder dts Makefile entries alphabetically -----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEEyRC2zAhGcGjrhiNExEYeRXyRFuMFAmPdN9UQHHZpZ25lc2hy QHRpLmNvbQAKCRDERh5FfJEW4w4NB/9BebQHfTau/InqXqL24ofgqzpEbq51zmcl 2TN1cCMG7Dpln8cvIwoj2KBLkTD//gP5Vx5oTdbFo5EJ/cH5Ohg39zLy773+ZU9O tD3wqzI1jUZjvn4H+atds1r5TmDyBoyRiDq90h6XiAFvu72GabW3wCF6wj3kQirl 5a8+gjKZuEeV990ypppmsKWdZcfEX2b84tGdz+4vtMFNbQamXfbmrozYB1Fcjj3Y sZDi8J+HUmUq+wHpaoQVSTfeKQxnHg4nmrn5jVifGnEQcKNQUjRvSrZ0Mh3ARbXR OdhA5U+5urEUK3YtDj7STW2VmKCSZiTyEsXwNPCuEMk3/4THWLk6 =Ddwb -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmPg3wAACgkQmmx57+YA GNkwZw//fJqEFL7a8QXVwIF2xkCyPvLMliD4KpqrLGp48XcWo/PoJhAgp2oP5qG8 keN8VqlYSth1BKqL8UCY7bU3tR7TfGWFTF9r0TnNW/ZGY3HwEntSTeoNXUgF4rGW 3F7euW2+2DELAzmoHNNCR7i4IaCnlXgZBEzxKOmLPmJtbzWIIKWJCHGyw2kjfCqo 8rOIwHQjEOQ9iDe9j96BE89meVRqOrNM3YoUn0Wyah28Vm1qyhLX9enbeUPw7TYe CzfLQCF0POre42iOYOqwBeflnrgj1ZqTbO+FnKCozJhgLesZEdL6Yv19vjnE04VN 7kriiPTKSH4jrOccvc3SFHuekUfRnlCF+Tsku/Ft+JjtvSHMghqsIgtLMoMforrC c5iBmem4xnoVvyjWlgvI8NfLvRSZQ1HWe9SsF282Iy950LxqrLwH9nXzPd5HMJNB tBp+sWa3fzW/u4Qic7YppwZ6w0lX8jbnC3qn1ngBudM9UjrHupHmsDaTE94VWi1B PjjcPmAXKDje1IiLBVG0mRBVmr5hFf3wZq2j6+ylr8aq7QqWE4ksHFk1m9XitQ2T dIsuH6nJXP/bhjv3Kgfb4igHFewmh9PiZJ9OQ/H2A1Zz1P2owX2G1gc9qXrePfvs lX/X4n+hNOt+l9YmJKCTlfuOpnuslqtM9Dt6ZMMcKFw7f9/+Hgg= =StZP -----END PGP SIGNATURE----- Merge tag 'ti-k3-dt-for-v6.3' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into arm/dt TI K3 device tree updates for v6.3 New features: J784S4 SoC and EVM support AM68 and AM69 StarterKit, phyBOARD-Electra-AM642, Siemens IoT2050 M.2 AM62A7 SK additional peripherals AM62 SK USB support Non critical fixes AM62: McSPI Clock ID fixes MMC TAP value updates J7200: pinmux range update All: Cache DT node fixes Cleanups: Reorder dts Makefile entries alphabetically * tag 'ti-k3-dt-for-v6.3' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: (25 commits) arm64: dts: ti: Makefile: Rearrange entries alphabetically arch: arm64: dts: Add support for AM69 Starter Kit dt-bindings: arm: ti: Add binding for AM69 Starter Kit arm64: dts: ti: iot2050: Add support for M.2 variant dt-bindings: arm: ti: Add binding for Siemens IOT2050 M.2 variant arm64: dts: ti: iot2050: Add layout of OSPI flash arm64: dts: ti: k3-j7200: Fix wakeup pinmux range arm64: dts: ti: k3-am68-sk: Add support for AM68 SK base board arm64: dts: ti: Add initial support for AM68 SK System on Module dt-bindings: arm: ti: Add binding for AM68 SK arm64: dts: Update cache properties for ti arm64: dts: ti: Add support for phyBOARD-Electra-AM642 dt-bindings: arm: ti: Add bindings for PHYTEC AM64x based hardware arm64: dts: ti: k3-am62a7-sk: Enable USB1 node arm64: dts: ti: k3-am62a7-sk: Enable ethernet port arm64: dts: ti: k3-am62a-main: Add more peripheral nodes arm64: dts: ti: k3-am62a-mcu: Add MCU domain peripherals arm64: dts: ti: Add support for J784S4 EVM board arm64: dts: ti: Add initial support for J784S4 SoC dt-bindings: pinctrl: k3: Introduce pinmux definitions for J784s4 ... Link: https://lore.kernel.org/r/642cf238-43e5-d6fa-68b5-a9dfbc0277bf@ti.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
f7401f6bc7
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@ -38,10 +38,17 @@ properties:
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- ti,am642-sk
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- const: ti,am642
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- description: K3 AM642 SoC PHYTEC phyBOARD-Electra
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items:
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- const: phytec,am642-phyboard-electra-rdk
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- const: phytec,am64-phycore-som
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- const: ti,am642
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- description: K3 AM654 SoC
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items:
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- enum:
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- siemens,iot2050-advanced
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- siemens,iot2050-advanced-m2
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- siemens,iot2050-advanced-pg2
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- siemens,iot2050-basic
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- siemens,iot2050-basic-pg2
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@ -69,9 +76,17 @@ properties:
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- description: K3 J721s2 SoC
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items:
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- enum:
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- ti,am68-sk
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- ti,j721s2-evm
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- const: ti,j721s2
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- description: K3 J784s4 SoC
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items:
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- enum:
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- ti,am69-sk
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- ti,j784s4-evm
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- const: ti,j784s4
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additionalProperties: true
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...
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@ -5,24 +5,43 @@
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#
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# Copyright (C) 2016-2021 Texas Instruments Incorporated - https://www.ti.com/
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#
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# Entries are grouped as per SoC present on the board. Groups are sorted
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# alphabetically.
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dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
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# Boards with AM62x SoC
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dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb
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# Boards with AM62Ax SoC
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dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb
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# Boards with AM64x SoC
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dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-rdk.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb
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# Boards with AM65x SoC
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dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic-pg2.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-m2.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-pg2.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
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# Boards with J7200 SoC
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dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb
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# Boards with J721e SoC
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dtb-$(CONFIG_ARCH_K3) += k3-j721e-beagleboneai64.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb
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# Boards with J721s2 SoC
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dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-j721s2-common-proc-board.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb
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# Boards with J784s4 SoC
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dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb
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# Enable support for device-tree overlays
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DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@
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@ -413,7 +413,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 172 0>;
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clocks = <&k3_clks 141 0>;
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status = "disabled";
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};
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@ -424,7 +424,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 173 0>;
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clocks = <&k3_clks 142 0>;
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status = "disabled";
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};
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@ -435,7 +435,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 174 0>;
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clocks = <&k3_clks 143 0>;
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status = "disabled";
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};
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@ -501,8 +501,10 @@
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ti,clkbuf-sel = <0x7>;
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ti,otap-del-sel-legacy = <0x0>;
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ti,otap-del-sel-mmc-hs = <0x0>;
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ti,otap-del-sel-ddr52 = <0x9>;
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ti,otap-del-sel-hs200 = <0x6>;
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ti,otap-del-sel-ddr52 = <0x5>;
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ti,otap-del-sel-hs200 = <0x5>;
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ti,itap-del-sel-legacy = <0xa>;
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ti,itap-del-sel-mmc-hs = <0x1>;
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status = "disabled";
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};
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@ -514,17 +516,17 @@
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clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
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clock-names = "clk_ahb", "clk_xin";
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ti,trm-icp = <0x2>;
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ti,otap-del-sel-legacy = <0x0>;
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ti,otap-del-sel-legacy = <0x8>;
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ti,otap-del-sel-sd-hs = <0x0>;
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ti,otap-del-sel-sdr12 = <0xf>;
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ti,otap-del-sel-sdr25 = <0xf>;
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ti,otap-del-sel-sdr50 = <0xc>;
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ti,otap-del-sel-sdr104 = <0x6>;
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ti,otap-del-sel-ddr50 = <0x9>;
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ti,itap-del-sel-legacy = <0x0>;
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ti,itap-del-sel-sd-hs = <0x0>;
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ti,itap-del-sel-sdr12 = <0x0>;
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ti,itap-del-sel-sdr25 = <0x0>;
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ti,otap-del-sel-sdr12 = <0x0>;
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ti,otap-del-sel-sdr25 = <0x0>;
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ti,otap-del-sel-sdr50 = <0x8>;
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ti,otap-del-sel-sdr104 = <0x7>;
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ti,otap-del-sel-ddr50 = <0x4>;
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ti,itap-del-sel-legacy = <0xa>;
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ti,itap-del-sel-sd-hs = <0x1>;
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ti,itap-del-sel-sdr12 = <0xa>;
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ti,itap-del-sel-sdr25 = <0x1>;
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ti,clkbuf-sel = <0x7>;
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bus-width = <4>;
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status = "disabled";
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@ -538,21 +540,67 @@
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clocks = <&k3_clks 184 5>, <&k3_clks 184 6>;
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clock-names = "clk_ahb", "clk_xin";
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ti,trm-icp = <0x2>;
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ti,otap-del-sel-legacy = <0x0>;
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ti,otap-del-sel-legacy = <0x8>;
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ti,otap-del-sel-sd-hs = <0x0>;
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ti,otap-del-sel-sdr12 = <0xf>;
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ti,otap-del-sel-sdr25 = <0xf>;
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ti,otap-del-sel-sdr50 = <0xc>;
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ti,otap-del-sel-sdr104 = <0x6>;
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ti,otap-del-sel-ddr50 = <0x9>;
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ti,itap-del-sel-legacy = <0x0>;
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ti,itap-del-sel-sd-hs = <0x0>;
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ti,itap-del-sel-sdr12 = <0x0>;
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ti,itap-del-sel-sdr25 = <0x0>;
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ti,otap-del-sel-sdr12 = <0x0>;
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ti,otap-del-sel-sdr25 = <0x0>;
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ti,otap-del-sel-sdr50 = <0x8>;
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ti,otap-del-sel-sdr104 = <0x7>;
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ti,otap-del-sel-ddr50 = <0x8>;
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ti,itap-del-sel-legacy = <0xa>;
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ti,itap-del-sel-sd-hs = <0xa>;
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ti,itap-del-sel-sdr12 = <0xa>;
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ti,itap-del-sel-sdr25 = <0x1>;
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ti,clkbuf-sel = <0x7>;
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status = "disabled";
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};
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usbss0: dwc3-usb@f900000 {
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compatible = "ti,am62-usb";
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reg = <0x00 0x0f900000 0x00 0x800>;
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clocks = <&k3_clks 161 3>;
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clock-names = "ref";
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ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>;
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#address-cells = <2>;
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#size-cells = <2>;
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power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
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ranges;
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status = "disabled";
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usb0: usb@31000000 {
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compatible = "snps,dwc3";
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reg =<0x00 0x31000000 0x00 0x50000>;
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interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
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<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
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interrupt-names = "host", "peripheral";
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maximum-speed = "high-speed";
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dr_mode = "otg";
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};
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};
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usbss1: dwc3-usb@f910000 {
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compatible = "ti,am62-usb";
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reg = <0x00 0x0f910000 0x00 0x800>;
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clocks = <&k3_clks 162 3>;
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clock-names = "ref";
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ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
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#address-cells = <2>;
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#size-cells = <2>;
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power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
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ranges;
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status = "disabled";
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usb1: usb@31100000 {
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compatible = "snps,dwc3";
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reg =<0x00 0x31100000 0x00 0x50000>;
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interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
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<GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
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interrupt-names = "host", "peripheral";
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maximum-speed = "high-speed";
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dr_mode = "otg";
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};
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};
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fss: bus@fc00000 {
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compatible = "simple-bus";
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reg = <0x00 0x0fc00000 0x00 0x70000>;
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@ -24,6 +24,8 @@
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spi0 = &ospi0;
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ethernet0 = &cpsw_port1;
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ethernet1 = &cpsw_port2;
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usb0 = &usb0;
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usb1 = &usb1;
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};
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chosen {
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@ -284,6 +286,12 @@
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AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */
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>;
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};
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main_usb1_pins_default: main-usb1-pins-default {
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pinctrl-single,pins = <
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AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */
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>;
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};
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};
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&wkup_uart0 {
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@ -464,3 +472,22 @@
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};
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};
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};
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&usbss0 {
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status = "okay";
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ti,vbus-divider;
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};
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&usbss1 {
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status = "okay";
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};
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&usb0 {
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dr_mode = "peripheral";
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};
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&usb1 {
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dr_mode = "host";
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pinctrl-names = "default";
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pinctrl-0 = <&main_usb1_pins_default>;
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};
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@ -146,6 +146,7 @@
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L2_0: l2-cache0 {
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compatible = "cache";
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cache-unified;
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cache-level = <2>;
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cache-size = <0x40000>;
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cache-line-size = <64>;
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@ -48,6 +48,18 @@
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00 0x00 0x00100000 0x20000>;
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phy_gmii_sel: phy@4044 {
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compatible = "ti,am654-phy-gmii-sel";
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reg = <0x4044 0x8>;
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#phy-cells = <1>;
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};
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epwm_tbclk: clock-controller@4130 {
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compatible = "ti,am62-epwm-tbclk", "syscon";
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reg = <0x4130 0x4>;
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#clock-cells = <1>;
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};
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};
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dmss: bus@48000000 {
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@ -69,6 +81,67 @@
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interrupt-names = "rx_012";
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||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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||||
};
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||||
inta_main_dmss: interrupt-controller@48000000 {
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compatible = "ti,sci-inta";
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reg = <0x00 0x48000000 0x00 0x100000>;
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#interrupt-cells = <0>;
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interrupt-controller;
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interrupt-parent = <&gic500>;
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msi-controller;
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||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <28>;
|
||||
ti,interrupt-ranges = <6 70 34>;
|
||||
ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
|
||||
};
|
||||
|
||||
main_bcdma: dma-controller@485c0100 {
|
||||
compatible = "ti,am64-dmss-bcdma";
|
||||
reg = <0x00 0x485c0100 0x00 0x100>,
|
||||
<0x00 0x4c000000 0x00 0x20000>,
|
||||
<0x00 0x4a820000 0x00 0x20000>,
|
||||
<0x00 0x4aa40000 0x00 0x20000>,
|
||||
<0x00 0x4bc00000 0x00 0x100000>;
|
||||
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
|
||||
msi-parent = <&inta_main_dmss>;
|
||||
#dma-cells = <3>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <26>;
|
||||
ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
|
||||
ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
|
||||
ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
|
||||
};
|
||||
|
||||
main_pktdma: dma-controller@485c0000 {
|
||||
compatible = "ti,am64-dmss-pktdma";
|
||||
reg = <0x00 0x485c0000 0x00 0x100>,
|
||||
<0x00 0x4a800000 0x00 0x20000>,
|
||||
<0x00 0x4aa00000 0x00 0x40000>,
|
||||
<0x00 0x4b800000 0x00 0x400000>;
|
||||
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
|
||||
msi-parent = <&inta_main_dmss>;
|
||||
#dma-cells = <2>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <30>;
|
||||
ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
|
||||
<0x24>, /* CPSW_TX_CHAN */
|
||||
<0x25>, /* SAUL_TX_0_CHAN */
|
||||
<0x26>; /* SAUL_TX_1_CHAN */
|
||||
ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
|
||||
<0x11>, /* RING_CPSW_TX_CHAN */
|
||||
<0x12>, /* RING_SAUL_TX_0_CHAN */
|
||||
<0x13>; /* RING_SAUL_TX_1_CHAN */
|
||||
ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
|
||||
<0x2b>, /* CPSW_RX_CHAN */
|
||||
<0x2d>, /* SAUL_RX_0_CHAN */
|
||||
<0x2f>, /* SAUL_RX_1_CHAN */
|
||||
<0x31>, /* SAUL_RX_2_CHAN */
|
||||
<0x33>; /* SAUL_RX_3_CHAN */
|
||||
ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
|
||||
<0x2c>, /* FLOW_CPSW_RX_CHAN */
|
||||
<0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
|
||||
<0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
|
||||
};
|
||||
};
|
||||
|
||||
dmsc: system-controller@44043000 {
|
||||
|
|
@ -222,6 +295,39 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
main_spi0: spi@20100000 {
|
||||
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
|
||||
reg = <0x00 0x20100000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 141 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_spi1: spi@20110000 {
|
||||
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x00 0x20110000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 142 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_spi2: spi@20120000 {
|
||||
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x00 0x20120000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 143 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_gpio_intr: interrupt-controller@a00000 {
|
||||
compatible = "ti,sci-intr";
|
||||
reg = <0x00 0x00a00000 0x00 0x800>;
|
||||
|
|
@ -295,4 +401,263 @@
|
|||
no-1-8-v;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbss0: dwc3-usb@f900000 {
|
||||
compatible = "ti,am62-usb";
|
||||
reg = <0x00 0x0f900000 0x00 0x800>;
|
||||
clocks = <&k3_clks 161 3>;
|
||||
clock-names = "ref";
|
||||
ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
|
||||
ranges;
|
||||
status = "disabled";
|
||||
|
||||
usb0: usb@31000000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg =<0x00 0x31000000 0x00 0x50000>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
|
||||
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
|
||||
interrupt-names = "host", "peripheral";
|
||||
maximum-speed = "high-speed";
|
||||
dr_mode = "otg";
|
||||
};
|
||||
};
|
||||
|
||||
usbss1: dwc3-usb@f910000 {
|
||||
compatible = "ti,am62-usb";
|
||||
reg = <0x00 0x0f910000 0x00 0x800>;
|
||||
clocks = <&k3_clks 162 3>;
|
||||
clock-names = "ref";
|
||||
ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
|
||||
ranges;
|
||||
status = "disabled";
|
||||
|
||||
usb1: usb@31100000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg =<0x00 0x31100000 0x00 0x50000>;
|
||||
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
|
||||
<GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
|
||||
interrupt-names = "host", "peripheral";
|
||||
maximum-speed = "high-speed";
|
||||
dr_mode = "otg";
|
||||
};
|
||||
};
|
||||
|
||||
fss: bus@fc00000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x00 0x0fc00000 0x00 0x70000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
status = "disabled";
|
||||
|
||||
ospi0: spi@fc40000 {
|
||||
compatible = "ti,am654-ospi", "cdns,qspi-nor";
|
||||
reg = <0x00 0x0fc40000 0x00 0x100>,
|
||||
<0x05 0x00000000 0x01 0x00000000>;
|
||||
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
|
||||
cdns,fifo-depth = <256>;
|
||||
cdns,fifo-width = <4>;
|
||||
cdns,trigger-address = <0x0>;
|
||||
clocks = <&k3_clks 75 7>;
|
||||
assigned-clocks = <&k3_clks 75 7>;
|
||||
assigned-clock-parents = <&k3_clks 75 8>;
|
||||
assigned-clock-rates = <166666666>;
|
||||
power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
cpsw3g: ethernet@8000000 {
|
||||
compatible = "ti,am642-cpsw-nuss";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
reg = <0x0 0x8000000 0x0 0x200000>;
|
||||
reg-names = "cpsw_nuss";
|
||||
ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
|
||||
clocks = <&k3_clks 13 0>;
|
||||
assigned-clocks = <&k3_clks 13 3>;
|
||||
assigned-clock-parents = <&k3_clks 13 11>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
|
||||
dmas = <&main_pktdma 0xc600 15>,
|
||||
<&main_pktdma 0xc601 15>,
|
||||
<&main_pktdma 0xc602 15>,
|
||||
<&main_pktdma 0xc603 15>,
|
||||
<&main_pktdma 0xc604 15>,
|
||||
<&main_pktdma 0xc605 15>,
|
||||
<&main_pktdma 0xc606 15>,
|
||||
<&main_pktdma 0xc607 15>,
|
||||
<&main_pktdma 0x4600 15>;
|
||||
dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
|
||||
"tx7", "rx";
|
||||
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpsw_port1: port@1 {
|
||||
reg = <1>;
|
||||
ti,mac-only;
|
||||
label = "port1";
|
||||
phys = <&phy_gmii_sel 1>;
|
||||
mac-address = [00 00 00 00 00 00];
|
||||
ti,syscon-efuse = <&wkup_conf 0x200>;
|
||||
};
|
||||
|
||||
cpsw_port2: port@2 {
|
||||
reg = <2>;
|
||||
ti,mac-only;
|
||||
label = "port2";
|
||||
phys = <&phy_gmii_sel 2>;
|
||||
mac-address = [00 00 00 00 00 00];
|
||||
};
|
||||
};
|
||||
|
||||
cpsw3g_mdio: mdio@f00 {
|
||||
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
|
||||
reg = <0x0 0xf00 0x0 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&k3_clks 13 0>;
|
||||
clock-names = "fck";
|
||||
bus_freq = <1000000>;
|
||||
};
|
||||
|
||||
cpts@3d000 {
|
||||
compatible = "ti,j721e-cpts";
|
||||
reg = <0x0 0x3d000 0x0 0x400>;
|
||||
clocks = <&k3_clks 13 3>;
|
||||
clock-names = "cpts";
|
||||
interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "cpts";
|
||||
ti,cpts-ext-ts-inputs = <4>;
|
||||
ti,cpts-periodic-outputs = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
hwspinlock: spinlock@2a000000 {
|
||||
compatible = "ti,am64-hwspinlock";
|
||||
reg = <0x00 0x2a000000 0x00 0x1000>;
|
||||
#hwlock-cells = <1>;
|
||||
};
|
||||
|
||||
mailbox0_cluster0: mailbox@29000000 {
|
||||
compatible = "ti,am64-mailbox";
|
||||
reg = <0x00 0x29000000 0x00 0x200>;
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
};
|
||||
|
||||
mailbox0_cluster1: mailbox@29010000 {
|
||||
compatible = "ti,am64-mailbox";
|
||||
reg = <0x00 0x29010000 0x00 0x200>;
|
||||
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
};
|
||||
|
||||
mailbox0_cluster2: mailbox@29020000 {
|
||||
compatible = "ti,am64-mailbox";
|
||||
reg = <0x00 0x29020000 0x00 0x200>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
};
|
||||
|
||||
mailbox0_cluster3: mailbox@29030000 {
|
||||
compatible = "ti,am64-mailbox";
|
||||
reg = <0x00 0x29030000 0x00 0x200>;
|
||||
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
};
|
||||
|
||||
main_mcan0: can@20701000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0x00 0x20701000 0x00 0x200>,
|
||||
<0x00 0x20708000 0x00 0x8000>;
|
||||
reg-names = "m_can", "message_ram";
|
||||
power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 98 6>, <&k3_clks 98 1>;
|
||||
clock-names = "hclk", "cclk";
|
||||
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "int0", "int1";
|
||||
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
epwm0: pwm@23000000 {
|
||||
compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x00 0x23000000 0x00 0x100>;
|
||||
power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
|
||||
clock-names = "tbclk", "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
epwm1: pwm@23010000 {
|
||||
compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x00 0x23010000 0x00 0x100>;
|
||||
power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
|
||||
clock-names = "tbclk", "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
epwm2: pwm@23020000 {
|
||||
compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x00 0x23020000 0x00 0x100>;
|
||||
power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
|
||||
clock-names = "tbclk", "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecap0: pwm@23100000 {
|
||||
compatible = "ti,am3352-ecap";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x00 0x23100000 0x00 0x100>;
|
||||
power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 51 0>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecap1: pwm@23110000 {
|
||||
compatible = "ti,am3352-ecap";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x00 0x23110000 0x00 0x100>;
|
||||
power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 52 0>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecap2: pwm@23120000 {
|
||||
compatible = "ti,am3352-ecap";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x00 0x23120000 0x00 0x100>;
|
||||
power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 53 0>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -36,4 +36,55 @@
|
|||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcu_spi0: spi@4b00000 {
|
||||
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
|
||||
reg = <0x00 0x04b00000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 147 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcu_spi1: spi@4b10000 {
|
||||
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x00 0x04b10000 0x00 0x400>;
|
||||
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 148 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcu_gpio_intr: interrupt-controller@4210000 {
|
||||
compatible = "ti,sci-intr";
|
||||
reg = <0x00 0x04210000 0x00 0x200>;
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
#interrupt-cells = <1>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <5>;
|
||||
ti,interrupt-ranges = <0 104 4>;
|
||||
};
|
||||
|
||||
mcu_gpio0: gpio@4201000 {
|
||||
compatible = "ti,am64-gpio", "ti,keystone-gpio";
|
||||
reg = <0x00 0x04201000 0x00 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&mcu_gpio_intr>;
|
||||
interrupts = <30>, <31>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <24>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 79 0>;
|
||||
clock-names = "gpio";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@
|
|||
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
#include "k3-am62a7.dtsi"
|
||||
|
||||
/ {
|
||||
|
|
@ -158,6 +159,36 @@
|
|||
AM62AX_IOPAD(0x244, PIN_OUTPUT, 7) /* (D18) MMC1_SDWP.GPIO1_49 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_usb1_pins_default: main-usb1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM62AX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mdio1_pins_default: main-mdio1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM62AX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */
|
||||
AM62AX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */
|
||||
>;
|
||||
};
|
||||
|
||||
main_rgmii1_pins_default: main-rgmii1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM62AX_IOPAD(0x14c, PIN_INPUT, 0) /* (AB16) RGMII1_RD0 */
|
||||
AM62AX_IOPAD(0x150, PIN_INPUT, 0) /* (V15) RGMII1_RD1 */
|
||||
AM62AX_IOPAD(0x154, PIN_INPUT, 0) /* (W15) RGMII1_RD2 */
|
||||
AM62AX_IOPAD(0x158, PIN_INPUT, 0) /* (V14) RGMII1_RD3 */
|
||||
AM62AX_IOPAD(0x148, PIN_INPUT, 0) /* (AA16) RGMII1_RXC */
|
||||
AM62AX_IOPAD(0x144, PIN_INPUT, 0) /* (AA15) RGMII1_RX_CTL */
|
||||
AM62AX_IOPAD(0x134, PIN_INPUT, 0) /* (Y17) RGMII1_TD0 */
|
||||
AM62AX_IOPAD(0x138, PIN_INPUT, 0) /* (V16) RGMII1_TD1 */
|
||||
AM62AX_IOPAD(0x13c, PIN_INPUT, 0) /* (Y16) RGMII1_TD2 */
|
||||
AM62AX_IOPAD(0x140, PIN_INPUT, 0) /* (AA17) RGMII1_TD3 */
|
||||
AM62AX_IOPAD(0x130, PIN_INPUT, 0) /* (AB17) RGMII1_TXC */
|
||||
AM62AX_IOPAD(0x12c, PIN_INPUT, 0) /* (W16) RGMII1_TX_CTL */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_i2c0 {
|
||||
|
|
@ -221,3 +252,42 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart0_pins_default>;
|
||||
};
|
||||
|
||||
&usbss1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
dr_mode = "host";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_usb1_pins_default>;
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_rgmii1_pins_default>;
|
||||
};
|
||||
|
||||
&cpsw_port1 {
|
||||
status = "okay";
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&cpsw3g_phy0>;
|
||||
};
|
||||
|
||||
&cpsw_port2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cpsw3g_mdio {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mdio1_pins_default>;
|
||||
|
||||
cpsw3g_phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
ti,min-output-impedance;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -95,6 +95,7 @@
|
|||
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
cache-size = <0x40000>;
|
||||
cache-line-size = <64>;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,231 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com
|
||||
* Author: Matt McKee <mmckee@phytec.com>
|
||||
*
|
||||
* Copyright (C) 2022 PHYTEC Messtechnik GmbH
|
||||
* Author: Wadim Egorov <w.egorov@phytec.de>
|
||||
*
|
||||
* Product homepage:
|
||||
* https://www.phytec.com/product/phycore-am64x
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
|
||||
/ {
|
||||
model = "PHYTEC phyCORE-AM64x";
|
||||
compatible = "phytec,am64-phycore-som", "ti,am642";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &cpsw_port1;
|
||||
mmc0 = &sdhci0;
|
||||
rtc0 = &i2c_som_rtc;
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
secure_ddr: optee@9e800000 {
|
||||
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&leds_pins_default>;
|
||||
|
||||
led-0 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
gpios = <&main_gpio0 12 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
function = LED_FUNCTION_HEARTBEAT;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_5v0_som: regulator-vcc-5v0-som {
|
||||
/* VIN / VCC_5V0_SOM */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCC_5V0_SOM";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
cpsw_mdio_pins_default: cpsw-mdio-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
|
||||
AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
|
||||
AM64X_IOPAD(0x0100, PIN_OUTPUT, 7) /* (V7) PRG1_PRU0_GPO18.GPIO0_63 */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_rgmii1_pins_default: cpsw-rgmii1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
|
||||
AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
|
||||
AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
|
||||
AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
|
||||
AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
|
||||
AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
|
||||
AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
|
||||
AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
|
||||
AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
|
||||
AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
|
||||
AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
|
||||
AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
|
||||
AM64X_IOPAD(0x0154, PIN_INPUT, 7) /* (V12) PRG1_PRU1_GPO19.GPIO0_84 */
|
||||
>;
|
||||
};
|
||||
|
||||
eeprom_wp_pins_default: eeprom-wp-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0208, PIN_OUTPUT, 7) /* (D12) SPI0_CS0.GPIO1_42 */
|
||||
>;
|
||||
};
|
||||
|
||||
leds_pins_default: leds-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0030, PIN_OUTPUT, 7) /* (L18) OSPI0_CSn1.GPIO0_12 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c0_pins_default: main-i2c0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0260, PIN_INPUT, 0) /* (A18) I2C0_SCL */
|
||||
AM64X_IOPAD(0x0264, PIN_INPUT, 0) /* (B18) I2C0_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
ospi0_pins_default: ospi0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
|
||||
AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
|
||||
AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
|
||||
AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
|
||||
AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
|
||||
AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
|
||||
AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
|
||||
AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
|
||||
AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
|
||||
AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
|
||||
AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cpsw_rgmii1_pins_default>;
|
||||
};
|
||||
|
||||
&cpsw3g_mdio {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cpsw_mdio_pins_default>;
|
||||
|
||||
cpsw3g_phy1: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
interrupt-parent = <&main_gpio0>;
|
||||
interrupts = <84 IRQ_TYPE_EDGE_FALLING>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
reset-gpios = <&main_gpio0 63 GPIO_ACTIVE_LOW>;
|
||||
reset-assert-us = <1000>;
|
||||
reset-deassert-us = <1000>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpsw_port1 {
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&cpsw3g_phy1>;
|
||||
};
|
||||
|
||||
&cpsw_port2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster5 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster6 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster7 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_i2c0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c0_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "atmel,24c32";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&eeprom_wp_pins_default>;
|
||||
pagesize = <32>;
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
i2c_som_rtc: rtc@52 {
|
||||
compatible = "microcrystal,rv3028";
|
||||
reg = <0x52>;
|
||||
};
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ospi0_pins_default>;
|
||||
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <8>;
|
||||
spi-rx-bus-width = <8>;
|
||||
spi-max-frequency = <25000000>;
|
||||
cdns,tshsl-ns = <60>;
|
||||
cdns,tsd2d-ns = <60>;
|
||||
cdns,tchsh-ns = <60>;
|
||||
cdns,tslch-ns = <60>;
|
||||
cdns,read-delay = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
keep-power-in-suspend;
|
||||
};
|
||||
|
|
@ -0,0 +1,277 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com
|
||||
* Author: Matt McKee <mmckee@phytec.com>
|
||||
*
|
||||
* Copyright (C) 2022 PHYTEC Messtechnik GmbH
|
||||
* Author: Wadim Egorov <w.egorov@phytec.de>
|
||||
*
|
||||
* Product homepage:
|
||||
* https://www.phytec.com/product/phyboard-am64x
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/mux/ti-serdes.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
#include "k3-am642.dtsi"
|
||||
#include "k3-am64-phycore-som.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "phytec,am642-phyboard-electra-rdk",
|
||||
"phytec,am64-phycore-som", "ti,am642";
|
||||
model = "PHYTEC phyBOARD-Electra-AM64x RDK";
|
||||
|
||||
aliases {
|
||||
mmc1 = &sdhci1;
|
||||
serial2 = &main_uart0;
|
||||
serial3 = &main_uart1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &main_uart0;
|
||||
};
|
||||
|
||||
can_tc1: can-phy0 {
|
||||
compatible = "ti,tcan1042";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&can_tc1_pins_default>;
|
||||
#phy-cells = <0>;
|
||||
max-bitrate = <5000000>;
|
||||
standby-gpios = <&main_gpio0 32 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
can_tc2: can-phy1 {
|
||||
compatible = "ti,tcan1042";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&can_tc2_pins_default>;
|
||||
#phy-cells = <0>;
|
||||
max-bitrate = <5000000>;
|
||||
standby-gpios = <&main_gpio0 35 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
autorepeat;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gpio_keys_pins_default>;
|
||||
|
||||
key-home {
|
||||
label = "home";
|
||||
linux,code = <KEY_HOME>;
|
||||
gpios = <&main_gpio0 17 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
key-menu {
|
||||
label = "menu";
|
||||
linux,code = <KEY_MENU>;
|
||||
gpios = <&main_gpio0 21 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&leds_pins_default &user_leds_pins_default>;
|
||||
|
||||
led-1 {
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
gpios = <&main_gpio0 15 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "mmc0";
|
||||
function = LED_FUNCTION_DISK;
|
||||
};
|
||||
|
||||
led-2 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
gpios = <&main_gpio0 16 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "mmc1";
|
||||
function = LED_FUNCTION_DISK;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3_mmc: regulator-sd {
|
||||
/* TPS22963C */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCC_3V3_MMC";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
can_tc1_pins_default: can-tc1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0084, PIN_OUTPUT, 7) /* (P16) GPMC0_ADVn_ALE.GPIO0_32 */
|
||||
>;
|
||||
};
|
||||
|
||||
can_tc2_pins_default: can-tc2-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0090, PIN_OUTPUT, 7) /* (P17) GPMC0_BE0n_CLE.GPIO0_35 */
|
||||
>;
|
||||
};
|
||||
|
||||
gpio_keys_pins_default: gpio-keys-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0044, PIN_INPUT, 7) /* (T18) GPMC0_AD2.GPIO0_17 */
|
||||
AM64X_IOPAD(0x0054, PIN_INPUT, 7) /* (V20) GPMC0_AD6.GPIO0_21 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c1_pins_default: main-i2c1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0268, PIN_INPUT, 0) /* (C18) I2C1_SCL */
|
||||
AM64X_IOPAD(0x026c, PIN_INPUT, 0) /* (B19) I2C1_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mcan0_pins_default: main-mcan0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */
|
||||
AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mcan1_pins_default: main-mcan1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */
|
||||
AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mmc1_pins_default: main-mmc1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
|
||||
AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
|
||||
AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
|
||||
AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
|
||||
AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
|
||||
AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */
|
||||
AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
|
||||
AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_uart0_pins_default: main-uart0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
|
||||
AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_uart1_pins_default: main-uart1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
|
||||
AM64X_IOPAD(0x024C, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
|
||||
AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
|
||||
AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_usb0_pins_default: main-usb0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
|
||||
>;
|
||||
};
|
||||
|
||||
pcie_usb_sel_pins_default: pcie-usb-sel-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x017c, PIN_OUTPUT, 7) /* (T1) PRG0_PRU0_GPO7.GPIO1_7 */
|
||||
>;
|
||||
};
|
||||
|
||||
pcie0_pins_default: pcie0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0098, PIN_OUTPUT, 7) /* (W19) GPMC0_WAIT0.GPIO0_37 */
|
||||
>;
|
||||
};
|
||||
|
||||
user_leds_pins_default: user-leds-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x003c, PIN_OUTPUT, 7) /* (T20) GPMC0_AD0.GPIO0_15 */
|
||||
AM64X_IOPAD(0x0040, PIN_OUTPUT, 7) /* (U21) GPMC0_AD1.GPIO0_16 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_i2c1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c1_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
eeprom@51 {
|
||||
compatible = "atmel,24c02";
|
||||
pagesize = <16>;
|
||||
reg = <0x51>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_mcan0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mcan0_pins_default>;
|
||||
phys = <&can_tc1>;
|
||||
};
|
||||
|
||||
&main_mcan1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mcan1_pins_default>;
|
||||
phys = <&can_tc2>;
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart0_pins_default>;
|
||||
};
|
||||
|
||||
&main_uart1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart1_pins_default>;
|
||||
uart-has-rtscts;
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
vmmc-supply = <&vcc_3v3_mmc>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
bus-width = <4>;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
disable-wp;
|
||||
no-1-8-v;
|
||||
};
|
||||
|
||||
&serdes0 {
|
||||
serdes0_pcie_usb_link: phy@0 {
|
||||
reg = <0>;
|
||||
cdns,num-lanes = <1>;
|
||||
#phy-cells = <0>;
|
||||
cdns,phy-type = <PHY_TYPE_USB3>;
|
||||
resets = <&serdes_wiz0 1>;
|
||||
};
|
||||
};
|
||||
|
||||
&serdes_ln_ctrl {
|
||||
idle-states = <AM64_SERDES0_LANE0_USB>;
|
||||
};
|
||||
|
||||
&usbss0 {
|
||||
ti,vbus-divider;
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_usb0_pins_default>;
|
||||
dr_mode = "host";
|
||||
maximum-speed = "super-speed";
|
||||
phys = <&serdes0_pcie_usb_link>;
|
||||
phy-names = "cdns3,usb3-phy";
|
||||
};
|
||||
|
|
@ -58,6 +58,7 @@
|
|||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
cache-size = <0x40000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <256>;
|
||||
|
|
|
|||
|
|
@ -609,6 +609,52 @@
|
|||
cdns,tchsh-ns = <60>;
|
||||
cdns,tslch-ns = <60>;
|
||||
cdns,read-delay = <2>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
seboot@0 {
|
||||
label = "seboot";
|
||||
reg = <0x0 0x180000>; /* 1.5M */
|
||||
};
|
||||
|
||||
tispl@180000 {
|
||||
label = "tispl";
|
||||
reg = <0x180000 0x200000>; /* 2M */
|
||||
};
|
||||
|
||||
u-boot@380000 {
|
||||
label = "u-boot";
|
||||
reg = <0x380000 0x300000>; /* 3M */
|
||||
};
|
||||
|
||||
env@680000 {
|
||||
label = "env";
|
||||
reg = <0x680000 0x20000>; /* 128K */
|
||||
};
|
||||
|
||||
env-backup@6a0000 {
|
||||
label = "env.backup";
|
||||
reg = <0x6a0000 0x20000>; /* 128K */
|
||||
};
|
||||
|
||||
otpcmd@6c0000 {
|
||||
label = "otpcmd";
|
||||
reg = <0x6c0000 0x10000>; /* 64K */
|
||||
};
|
||||
|
||||
unused@6d0000 {
|
||||
label = "unused";
|
||||
reg = <0x6d0000 0x7b0000>; /* 7872K */
|
||||
};
|
||||
|
||||
seboot-backup@e80000 {
|
||||
label = "seboot.backup";
|
||||
reg = <0xe80000 0x180000>; /* 1.5M */
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -93,6 +93,7 @@
|
|||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
cache-size = <0x80000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
|
|
@ -102,6 +103,7 @@
|
|||
L2_1: l2-cache1 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
cache-size = <0x80000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,121 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) Siemens AG, 2018-2023
|
||||
*
|
||||
* Authors:
|
||||
* Chao Zeng <chao.zeng@siemens.com>
|
||||
* Jan Kiszka <jan.kiszka@siemens.com>
|
||||
*
|
||||
* AM6548-based (quad-core) IOT2050 M.2 variant (based on Advanced Product
|
||||
* Generation 2), 2 GB RAM, 16 GB eMMC, USB-serial converter on connector X30
|
||||
*
|
||||
* Product homepage:
|
||||
* https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
|
||||
*/
|
||||
|
||||
#include "k3-am6548-iot2050-advanced-common.dtsi"
|
||||
#include "k3-am65-iot2050-common-pg2.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "siemens,iot2050-advanced-m2", "ti,am654";
|
||||
model = "SIMATIC IOT2050 Advanced M2";
|
||||
};
|
||||
|
||||
&mcu_r5fss0 {
|
||||
/* lock-step mode not supported on this board */
|
||||
ti,cluster-mode = <0>;
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
main_m2_enable_pins_default: main-m2-enable-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7) /* (AH13) GPIO1_17 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_bkey_pcie_reset: main-bkey-pcie-reset {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x01bc, PIN_OUTPUT_PULLUP, 7) /* (AG13) GPIO1_15 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_pmx0_m2_config_pins_default: main-pmx0-m2-config-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x01c8, PIN_INPUT_PULLUP, 7) /* (AE13) GPIO1_18 */
|
||||
AM65X_IOPAD(0x01cc, PIN_INPUT_PULLUP, 7) /* (AD13) GPIO1_19 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_m2_pcie_mux_control: main-m2-pcie-mux-control {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x0148, PIN_INPUT_PULLUP, 7) /* (AG22) GPIO0_82 */
|
||||
AM65X_IOPAD(0x0160, PIN_INPUT_PULLUP, 7) /* (AE20) GPIO0_88 */
|
||||
AM65X_IOPAD(0x0164, PIN_INPUT_PULLUP, 7) /* (AF19) GPIO0_89 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx1 {
|
||||
main_pmx1_m2_config_pins_default: main-pmx1-m2-config-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_IOPAD(0x0018, PIN_INPUT_PULLUP, 7) /* (B22) GPIO1_88 */
|
||||
AM65X_IOPAD(0x001c, PIN_INPUT_PULLUP, 7) /* (C23) GPIO1_89 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_gpio0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <
|
||||
&main_m2_pcie_mux_control
|
||||
&arduino_io_d4_to_d9_pins_default
|
||||
>;
|
||||
};
|
||||
|
||||
&main_gpio1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <
|
||||
&main_m2_enable_pins_default
|
||||
&main_pmx0_m2_config_pins_default
|
||||
&main_pmx1_m2_config_pins_default
|
||||
&cp2102n_reset_pin_default
|
||||
>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Base configuration for B-key slot with PCIe x2, E-key with USB 2.0 only.
|
||||
* Firmware switches to other modes via device tree overlays.
|
||||
*/
|
||||
|
||||
&serdes0 {
|
||||
assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
|
||||
assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
|
||||
};
|
||||
|
||||
&pcie0_rc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_bkey_pcie_reset>;
|
||||
|
||||
num-lanes = <2>;
|
||||
phys = <&serdes0 PHY_TYPE_PCIE 1>, <&serdes1 PHY_TYPE_PCIE 1>;
|
||||
phy-names = "pcie-phy0","pcie-phy1";
|
||||
reset-gpios = <&main_gpio1 15 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie1_rc {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&dwc3_0 {
|
||||
assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
|
||||
<&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
|
||||
/delete-property/ phys;
|
||||
/delete-property/ phy-names;
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
maximum-speed = "high-speed";
|
||||
/delete-property/ snps,dis-u1-entry-quirk;
|
||||
/delete-property/ snps,dis-u2-entry-quirk;
|
||||
};
|
||||
|
|
@ -0,0 +1,335 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*
|
||||
* Base Board: https://www.ti.com/lit/zip/SPRR463
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "k3-am68-sk-som.dtsi"
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
#include <dt-bindings/phy/phy-cadence.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
#include <dt-bindings/mux/ti-serdes.h>
|
||||
|
||||
/ {
|
||||
compatible = "ti,am68-sk", "ti,j721s2";
|
||||
model = "Texas Instruments AM68 SK";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:115200n8";
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial2 = &main_uart8;
|
||||
mmc1 = &main_sdhci1;
|
||||
can0 = &mcu_mcan0;
|
||||
can1 = &mcu_mcan1;
|
||||
can2 = &main_mcan6;
|
||||
can3 = &main_mcan7;
|
||||
};
|
||||
|
||||
vusb_main: regulator-vusb-main5v0 {
|
||||
/* USB MAIN INPUT 5V DC */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vusb-main5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vsys_3v3: regulator-vsys3v3 {
|
||||
/* Output of LM5141 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vsys_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vusb_main>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vdd_mmc1: regulator-sd {
|
||||
/* Output of TPS22918 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_mmc1";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
vin-supply = <&vsys_3v3>;
|
||||
gpio = <&exp1 10 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
vdd_sd_dv: regulator-tlv71033 {
|
||||
/* Output of TLV71033 */
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "tlv71033";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vdd_sd_dv_pins_default>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vsys_3v3>;
|
||||
gpios = <&main_gpio0 49 GPIO_ACTIVE_HIGH>;
|
||||
states = <1800000 0x0>,
|
||||
<3300000 0x1>;
|
||||
};
|
||||
|
||||
vsys_io_1v8: regulator-vsys-io-1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vsys_io_1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vsys_io_1v2: regulator-vsys-io-1v2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vsys_io_1v2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
transceiver1: can-phy0 {
|
||||
compatible = "ti,tcan1042";
|
||||
#phy-cells = <0>;
|
||||
max-bitrate = <5000000>;
|
||||
};
|
||||
|
||||
transceiver2: can-phy1 {
|
||||
compatible = "ti,tcan1042";
|
||||
#phy-cells = <0>;
|
||||
max-bitrate = <5000000>;
|
||||
};
|
||||
|
||||
transceiver3: can-phy2 {
|
||||
compatible = "ti,tcan1042";
|
||||
#phy-cells = <0>;
|
||||
max-bitrate = <5000000>;
|
||||
};
|
||||
|
||||
transceiver4: can-phy3 {
|
||||
compatible = "ti,tcan1042";
|
||||
#phy-cells = <0>;
|
||||
max-bitrate = <5000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
main_uart8_pins_default: main-uart8-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
|
||||
J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c0_pins_default: main-i2c0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721S2_IOPAD(0x0e0, PIN_INPUT, 0) /* (AH25) I2C0_SCL */
|
||||
J721S2_IOPAD(0x0e4, PIN_INPUT, 0) /* (AE24) I2C0_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mmc1_pins_default: main-mmc1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */
|
||||
J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */
|
||||
J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */
|
||||
J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
|
||||
J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
|
||||
J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
|
||||
J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
|
||||
>;
|
||||
};
|
||||
|
||||
vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721S2_IOPAD(0x0c4, PIN_INPUT, 7) /* (AB26) ECAP0_IN_APWM_OUT.GPIO0_49 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_usbss0_pins_default: main-usbss0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mcan6_pins_default: main-mcan6-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721S2_IOPAD(0x098, PIN_INPUT, 0) /* (V25) MCASP0_AXR10.MCAN6_RX */
|
||||
J721S2_IOPAD(0x094, PIN_INPUT, 0) /* (AA25) MCASP0_AXR9.MCAN6_TX */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mcan7_pins_default: main-mcan7-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721S2_IOPAD(0x0a0, PIN_INPUT, 0) /* (AB25) MCASP0_AXR12.MCAN7_RX */
|
||||
J721S2_IOPAD(0x09c, PIN_INPUT, 0) /* (T24) MCASP0_AXR11.MCAN7_TX */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_pmx0 {
|
||||
mcu_cpsw_pins_default: mcu-cpsw-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */
|
||||
J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */
|
||||
J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */
|
||||
J721S2_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */
|
||||
J721S2_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */
|
||||
J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */
|
||||
J721S2_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */
|
||||
J721S2_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */
|
||||
J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */
|
||||
J721S2_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */
|
||||
J721S2_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */
|
||||
J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */
|
||||
>;
|
||||
};
|
||||
|
||||
mcu_mdio_pins_default: mcu-mdio-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721S2_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */
|
||||
J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */
|
||||
>;
|
||||
};
|
||||
|
||||
mcu_mcan0_pins_default: mcu-mcan0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721S2_WKUP_IOPAD(0x0bc, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */
|
||||
J721S2_WKUP_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */
|
||||
>;
|
||||
};
|
||||
|
||||
mcu_mcan1_pins_default: mcu-mcan1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */
|
||||
J721S2_WKUP_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/
|
||||
>;
|
||||
};
|
||||
|
||||
mcu_i2c1_pins_default: mcu-i2c1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721S2_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_SCL */
|
||||
J721S2_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_gpio2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_gpio4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_gpio6 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wkup_gpio0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wkup_gpio1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wkup_uart0 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_uart8 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart8_pins_default>;
|
||||
/* Shared with TFA on this platform */
|
||||
power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>;
|
||||
};
|
||||
|
||||
&main_i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c0_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
exp1: gpio@21 {
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x21>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names = "CSI_VIO_SEL", "CSI_SEL_FPC_EXPn", "HDMI_PDn",
|
||||
"HDMI_LS_OE", "DP0_3V3 _EN", "BOARDID_EEPROM_WP",
|
||||
"CAN_STB", " ", "GPIO_uSD_PWR_EN", "eDP_ENABLE",
|
||||
"IO_EXP_PCIe1_M.2_RTSz", "IO_EXP_MCU_RGMII_RSTz",
|
||||
"IO_EXP_CSI2_EXP_RSTz", " ", "CSI0_B_GPIO1",
|
||||
"CSI1_B_GPIO1";
|
||||
};
|
||||
};
|
||||
|
||||
&main_sdhci0 {
|
||||
/* Unused */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_sdhci1 {
|
||||
/* SD card */
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
pinctrl-names = "default";
|
||||
disable-wp;
|
||||
vmmc-supply = <&vdd_mmc1>;
|
||||
vqmmc-supply = <&vdd_sd_dv>;
|
||||
};
|
||||
|
||||
&mcu_cpsw {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
ti,min-output-impedance;
|
||||
};
|
||||
};
|
||||
|
||||
&cpsw_port1 {
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
&mcu_mcan0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_mcan0_pins_default>;
|
||||
phys = <&transceiver1>;
|
||||
};
|
||||
|
||||
&mcu_mcan1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_mcan1_pins_default>;
|
||||
phys = <&transceiver2>;
|
||||
};
|
||||
|
||||
&main_mcan6 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mcan6_pins_default>;
|
||||
phys = <&transceiver3>;
|
||||
};
|
||||
|
||||
&main_mcan7 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mcan7_pins_default>;
|
||||
phys = <&transceiver4>;
|
||||
};
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "k3-j721s2.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* 16 GB RAM */
|
||||
reg = <0x00 0x80000000 0x00 0x80000000>,
|
||||
<0x08 0x80000000 0x03 0x80000000>;
|
||||
};
|
||||
|
||||
reserved_memory: reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
secure_ddr: optee@9e800000 {
|
||||
reg = <0x00 0x9e800000 0x00 0x01800000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,180 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*
|
||||
* Design Files: https://www.ti.com/lit/zip/SPRR466
|
||||
* TRM: https://www.ti.com/lit/zip/spruj52
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "k3-j784s4.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,am69-sk", "ti,j784s4";
|
||||
model = "Texas Instruments AM69 SK";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:115200n8";
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial2 = &main_uart8;
|
||||
mmc1 = &main_sdhci1;
|
||||
i2c0 = &main_i2c0;
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* 32G RAM */
|
||||
reg = <0x00 0x80000000 0x00 0x80000000>,
|
||||
<0x08 0x80000000 0x07 0x80000000>;
|
||||
};
|
||||
|
||||
reserved_memory: reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
secure_ddr: optee@9e800000 {
|
||||
reg = <0x00 0x9e800000 0x00 0x01800000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
vusb_main: regulator-vusb-main5v0 {
|
||||
/* USB MAIN INPUT 5V DC */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vusb-main5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vsys_5v0: regulator-vsys5v0 {
|
||||
/* Output of LM61460 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vsys_5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vusb_main>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vsys_3v3: regulator-vsys3v3 {
|
||||
/* Output of LM5143 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vsys_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vusb_main>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vdd_mmc1: regulator-sd {
|
||||
/* Output of TPS22918 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_mmc1";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
vin-supply = <&vsys_3v3>;
|
||||
gpio = <&exp1 2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
vdd_sd_dv: regulator-tlv71033 {
|
||||
/* Output of TLV71033 */
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "tlv71033";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vdd_sd_dv_pins_default>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vsys_5v0>;
|
||||
gpios = <&main_gpio0 49 GPIO_ACTIVE_HIGH>;
|
||||
states = <1800000 0x0>,
|
||||
<3300000 0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
main_uart8_pins_default: main-uart8-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */
|
||||
J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c0_pins_default: main-i2c0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */
|
||||
J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mmc1_pins_default: main-mmc1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */
|
||||
J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */
|
||||
J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */
|
||||
J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */
|
||||
J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */
|
||||
J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */
|
||||
J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */
|
||||
J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */
|
||||
>;
|
||||
};
|
||||
|
||||
vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J784S4_IOPAD(0x0C4, PIN_INPUT, 7) /* (AD36) ECAP0_IN_APWM_OUT.GPIO0_49 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_uart8 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart8_pins_default>;
|
||||
};
|
||||
|
||||
&main_i2c0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c0_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
exp1: gpio@21 {
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x21>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names = "BOARDID_EEPROM_WP", "CAN_STB", "GPIO_uSD_PWR_EN",
|
||||
"IO_EXP_MCU_RGMII_RST#", "IO_EXP_PCIe0_4L_PERST#",
|
||||
"IO_EXP_PCIe1_M.2_RTSz", "IO_EXP_PCIe3_M.2_RTSz",
|
||||
"PM_INA_BUS_EN", "ENET1_EXP_PWRDN", "EXP1_ENET_RSTz",
|
||||
"ENET1_I2CMUX_SEL", "PCIe0_CLKREQ#", "PCIe1_M.2_CLKREQ#",
|
||||
"PCIe3_M2_CLKREQ#", "PCIe0_PRSNT2#_1", "PCIe0_PRSNT2#_2";
|
||||
};
|
||||
};
|
||||
|
||||
&main_sdhci1 {
|
||||
/* SD card */
|
||||
status = "okay";
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
pinctrl-names = "default";
|
||||
disable-wp;
|
||||
vmmc-supply = <&vdd_mmc1>;
|
||||
vqmmc-supply = <&vdd_sd_dv>;
|
||||
};
|
||||
|
||||
&main_gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -80,7 +80,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
&wkup_pmx0 {
|
||||
&wkup_pmx2 {
|
||||
mcu_cpsw_pins_default: mcu-cpsw-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
|
||||
|
|
|
|||
|
|
@ -56,7 +56,34 @@
|
|||
wkup_pmx0: pinctrl@4301c000 {
|
||||
compatible = "pinctrl-single";
|
||||
/* Proxy 0 addressing */
|
||||
reg = <0x00 0x4301c000 0x00 0x178>;
|
||||
reg = <0x00 0x4301c000 0x00 0x34>;
|
||||
#pinctrl-cells = <1>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
wkup_pmx1: pinctrl@0x4301c038 {
|
||||
compatible = "pinctrl-single";
|
||||
/* Proxy 0 addressing */
|
||||
reg = <0x00 0x4301c038 0x00 0x8>;
|
||||
#pinctrl-cells = <1>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
wkup_pmx2: pinctrl@0x4301c068 {
|
||||
compatible = "pinctrl-single";
|
||||
/* Proxy 0 addressing */
|
||||
reg = <0x00 0x4301c068 0x00 0xec>;
|
||||
#pinctrl-cells = <1>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
wkup_pmx3: pinctrl@0x4301c174 {
|
||||
compatible = "pinctrl-single";
|
||||
/* Proxy 0 addressing */
|
||||
reg = <0x00 0x4301c174 0x00 0x20>;
|
||||
#pinctrl-cells = <1>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0xffffffff>;
|
||||
|
|
|
|||
|
|
@ -84,6 +84,7 @@
|
|||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
cache-size = <0x100000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <1024>;
|
||||
|
|
|
|||
|
|
@ -86,6 +86,7 @@
|
|||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
cache-size = <0x100000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <1024>;
|
||||
|
|
|
|||
|
|
@ -69,6 +69,7 @@
|
|||
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
cache-size = <0x100000>;
|
||||
cache-line-size = <64>;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,196 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*
|
||||
* EVM Board Schematics: https://www.ti.com/lit/zip/sprr458
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "k3-j784s4.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,j784s4-evm", "ti,j784s4";
|
||||
model = "Texas Instruments J784S4 EVM";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:115200n8";
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial2 = &main_uart8;
|
||||
mmc1 = &main_sdhci1;
|
||||
i2c0 = &main_i2c0;
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* 32G RAM */
|
||||
reg = <0x00 0x80000000 0x00 0x80000000>,
|
||||
<0x08 0x80000000 0x07 0x80000000>;
|
||||
};
|
||||
|
||||
reserved_memory: reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
secure_ddr: optee@9e800000 {
|
||||
reg = <0x00 0x9e800000 0x00 0x01800000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
evm_12v0: regulator-evm12v0 {
|
||||
/* main supply */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "evm_12v0";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vsys_3v3: regulator-vsys3v3 {
|
||||
/* Output of LM5140 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vsys_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&evm_12v0>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vsys_5v0: regulator-vsys5v0 {
|
||||
/* Output of LM5140 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vsys_5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&evm_12v0>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vdd_mmc1: regulator-sd {
|
||||
/* Output of TPS22918 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_mmc1";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
vin-supply = <&vsys_3v3>;
|
||||
gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
vdd_sd_dv: regulator-TLV71033 {
|
||||
/* Output of TLV71033 */
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "tlv71033";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vdd_sd_dv_pins_default>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vsys_5v0>;
|
||||
gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>;
|
||||
states = <1800000 0x0>,
|
||||
<3300000 0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
main_uart8_pins_default: main-uart8-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */
|
||||
J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */
|
||||
J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */
|
||||
J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c0_pins_default: main-i2c0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */
|
||||
J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mmc1_pins_default: main-mmc1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */
|
||||
J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */
|
||||
J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */
|
||||
J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */
|
||||
J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */
|
||||
J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */
|
||||
J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */
|
||||
J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */
|
||||
>;
|
||||
};
|
||||
|
||||
vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_uart8 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart8_pins_default>;
|
||||
};
|
||||
|
||||
&main_i2c0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c0_pins_default>;
|
||||
|
||||
clock-frequency = <400000>;
|
||||
|
||||
exp1: gpio@20 {
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names = "PCIE1_2L_MODE_SEL", "PCIE1_4L_PERSTZ", "PCIE1_2L_RC_RSTZ",
|
||||
"PCIE1_2L_EP_RST_EN", "PCIE0_4L_MODE_SEL", "PCIE0_4L_PERSTZ",
|
||||
"PCIE0_4L_RC_RSTZ", "PCIE0_4L_EP_RST_EN", "PCIE1_4L_PRSNT#",
|
||||
"PCIE0_4L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3",
|
||||
"AUDIO_MUX_SEL", "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTZ";
|
||||
};
|
||||
|
||||
exp2: gpio@22 {
|
||||
compatible = "ti,tca6424";
|
||||
reg = <0x22>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names = "R_GPIO_RGMII1_RST", "ENET2_I2CMUX_SEL", "GPIO_USD_PWR_EN",
|
||||
"USBC_PWR_EN", "USBC_MODE_SEL1", "USBC_MODE_SEL0",
|
||||
"GPIO_LIN_EN", "R_CAN_STB", "CTRL_PM_I2C_OE#",
|
||||
"ENET2_EXP_PWRDN", "ENET2_EXP_SPARE2", "CDCI2_RSTZ",
|
||||
"USB2.0_MUX_SEL", "CANUART_MUX_SEL0", "CANUART_MUX2_SEL1",
|
||||
"CANUART_MUX1_SEL1", "ENET1_EXP_PWRDN", "ENET1_EXP_RESETZ",
|
||||
"ENET1_I2CMUX_SEL", "ENET1_EXP_SPARE2", "ENET2_EXP_RESETZ",
|
||||
"USER_INPUT1", "USER_LED1", "USER_LED2";
|
||||
};
|
||||
};
|
||||
|
||||
&main_sdhci1 {
|
||||
/* SD card */
|
||||
status = "okay";
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
pinctrl-names = "default";
|
||||
disable-wp;
|
||||
vmmc-supply = <&vdd_mmc1>;
|
||||
vqmmc-supply = <&vdd_sd_dv>;
|
||||
};
|
||||
|
||||
&main_gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,311 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for J784S4 SoC Family MCU/WAKEUP Domain peripherals
|
||||
*
|
||||
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
&cbass_mcu_wakeup {
|
||||
sms: system-controller@44083000 {
|
||||
compatible = "ti,k2g-sci";
|
||||
ti,host-id = <12>;
|
||||
|
||||
mbox-names = "rx", "tx";
|
||||
|
||||
mboxes = <&secure_proxy_main 11>,
|
||||
<&secure_proxy_main 13>;
|
||||
|
||||
reg-names = "debug_messages";
|
||||
reg = <0x00 0x44083000 0x00 0x1000>;
|
||||
|
||||
k3_pds: power-controller {
|
||||
compatible = "ti,sci-pm-domain";
|
||||
#power-domain-cells = <2>;
|
||||
};
|
||||
|
||||
k3_clks: clock-controller {
|
||||
compatible = "ti,k2g-sci-clk";
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
||||
k3_reset: reset-controller {
|
||||
compatible = "ti,sci-reset";
|
||||
#reset-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
chipid@43000014 {
|
||||
compatible = "ti,am654-chipid";
|
||||
reg = <0x00 0x43000014 0x00 0x4>;
|
||||
};
|
||||
|
||||
mcu_ram: sram@41c00000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00 0x41c00000 0x00 0x100000>;
|
||||
ranges = <0x00 0x00 0x41c00000 0x100000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
wkup_pmx0: pinctrl@4301c000 {
|
||||
compatible = "pinctrl-single";
|
||||
/* Proxy 0 addressing */
|
||||
reg = <0x00 0x4301c000 0x00 0x178>;
|
||||
#pinctrl-cells = <1>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
wkup_gpio_intr: interrupt-controller@42200000 {
|
||||
compatible = "ti,sci-intr";
|
||||
reg = <0x00 0x42200000 0x00 0x400>;
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
#interrupt-cells = <1>;
|
||||
ti,sci = <&sms>;
|
||||
ti,sci-dev-id = <177>;
|
||||
ti,interrupt-ranges = <16 928 16>;
|
||||
};
|
||||
|
||||
mcu_conf: syscon@40f00000 {
|
||||
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
|
||||
reg = <0x00 0x40f00000 0x00 0x20000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00 0x00 0x40f00000 0x20000>;
|
||||
|
||||
phy_gmii_sel: phy@4040 {
|
||||
compatible = "ti,am654-phy-gmii-sel";
|
||||
reg = <0x4040 0x4>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
wkup_uart0: serial@42300000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x42300000 0x00 0x200>;
|
||||
interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
|
||||
current-speed = <115200>;
|
||||
clocks = <&k3_clks 397 0>;
|
||||
clock-names = "fclk";
|
||||
power-domains = <&k3_pds 397 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcu_uart0: serial@40a00000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x40a00000 0x00 0x200>;
|
||||
interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
|
||||
current-speed = <115200>;
|
||||
clocks = <&k3_clks 149 0>;
|
||||
clock-names = "fclk";
|
||||
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wkup_gpio0: gpio@42110000 {
|
||||
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
|
||||
reg = <0x00 0x42110000 0x00 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&wkup_gpio_intr>;
|
||||
interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <89>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 167 0>;
|
||||
clock-names = "gpio";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wkup_gpio1: gpio@42100000 {
|
||||
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
|
||||
reg = <0x00 0x42100000 0x00 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&wkup_gpio_intr>;
|
||||
interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <89>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 168 0>;
|
||||
clock-names = "gpio";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wkup_i2c0: i2c@42120000 {
|
||||
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x42120000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&k3_clks 279 2>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcu_i2c0: i2c@40b00000 {
|
||||
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x40b00000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&k3_clks 277 2>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcu_i2c1: i2c@40b10000 {
|
||||
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x40b10000 0x00 0x100>;
|
||||
interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&k3_clks 278 2>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcu_mcan0: can@40528000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0x00 0x40528000 0x00 0x200>,
|
||||
<0x00 0x40500000 0x00 0x8000>;
|
||||
reg-names = "m_can", "message_ram";
|
||||
power-domains = <&k3_pds 263 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 263 6>, <&k3_clks 263 1>;
|
||||
clock-names = "hclk", "cclk";
|
||||
interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "int0", "int1";
|
||||
bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcu_mcan1: can@40568000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0x00 0x40568000 0x00 0x200>,
|
||||
<0x00 0x40540000 0x00 0x8000>;
|
||||
reg-names = "m_can", "message_ram";
|
||||
power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 264 6>, <&k3_clks 264 1>;
|
||||
clock-names = "hclk", "cclk";
|
||||
interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "int0", "int1";
|
||||
bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcu_navss: bus@28380000{
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
|
||||
dma-coherent;
|
||||
dma-ranges;
|
||||
|
||||
mcu_ringacc: ringacc@2b800000 {
|
||||
compatible = "ti,am654-navss-ringacc";
|
||||
reg = <0x00 0x2b800000 0x00 0x400000>,
|
||||
<0x00 0x2b000000 0x00 0x400000>,
|
||||
<0x00 0x28590000 0x00 0x100>,
|
||||
<0x00 0x2a500000 0x00 0x40000>;
|
||||
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
|
||||
ti,num-rings = <286>;
|
||||
ti,sci-rm-range-gp-rings = <0x1>;
|
||||
ti,sci = <&sms>;
|
||||
ti,sci-dev-id = <328>;
|
||||
msi-parent = <&main_udmass_inta>;
|
||||
};
|
||||
|
||||
mcu_udmap: dma-controller@285c0000 {
|
||||
compatible = "ti,j721e-navss-mcu-udmap";
|
||||
reg = <0x00 0x285c0000 0x00 0x100>,
|
||||
<0x00 0x2a800000 0x00 0x40000>,
|
||||
<0x00 0x2aa00000 0x00 0x40000>;
|
||||
reg-names = "gcfg", "rchanrt", "tchanrt";
|
||||
msi-parent = <&main_udmass_inta>;
|
||||
#dma-cells = <1>;
|
||||
|
||||
ti,sci = <&sms>;
|
||||
ti,sci-dev-id = <329>;
|
||||
ti,ringacc = <&mcu_ringacc>;
|
||||
ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
|
||||
<0x0f>; /* TX_HCHAN */
|
||||
ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
|
||||
<0x0b>; /* RX_HCHAN */
|
||||
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
|
||||
};
|
||||
};
|
||||
|
||||
mcu_cpsw: ethernet@46000000 {
|
||||
compatible = "ti,j721e-cpsw-nuss";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
reg = <0x00 0x46000000 0x00 0x200000>;
|
||||
reg-names = "cpsw_nuss";
|
||||
ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>;
|
||||
dma-coherent;
|
||||
clocks = <&k3_clks 63 0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
dmas = <&mcu_udmap 0xf000>,
|
||||
<&mcu_udmap 0xf001>,
|
||||
<&mcu_udmap 0xf002>,
|
||||
<&mcu_udmap 0xf003>,
|
||||
<&mcu_udmap 0xf004>,
|
||||
<&mcu_udmap 0xf005>,
|
||||
<&mcu_udmap 0xf006>,
|
||||
<&mcu_udmap 0xf007>,
|
||||
<&mcu_udmap 0x7000>;
|
||||
dma-names = "tx0", "tx1", "tx2", "tx3",
|
||||
"tx4", "tx5", "tx6", "tx7",
|
||||
"rx";
|
||||
status = "disabled";
|
||||
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mcu_cpsw_port1: port@1 {
|
||||
reg = <1>;
|
||||
ti,mac-only;
|
||||
label = "port1";
|
||||
ti,syscon-efuse = <&mcu_conf 0x200>;
|
||||
phys = <&phy_gmii_sel 1>;
|
||||
};
|
||||
};
|
||||
|
||||
davinci_mdio: mdio@f00 {
|
||||
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
|
||||
reg = <0x00 0xf00 0x00 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&k3_clks 63 0>;
|
||||
clock-names = "fck";
|
||||
bus_freq = <1000000>;
|
||||
};
|
||||
|
||||
cpts@3d000 {
|
||||
compatible = "ti,am65-cpts";
|
||||
reg = <0x00 0x3d000 0x00 0x400>;
|
||||
clocks = <&k3_clks 63 3>;
|
||||
clock-names = "cpts";
|
||||
assigned-clocks = <&k3_clks 63 3>; /* CPTS_RFT_CLK */
|
||||
assigned-clock-parents = <&k3_clks 63 5>; /* MAIN_0_HSDIV6_CLK */
|
||||
interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "cpts";
|
||||
ti,cpts-ext-ts-inputs = <4>;
|
||||
ti,cpts-periodic-outputs = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,287 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for J784S4 SoC Family
|
||||
*
|
||||
* TRM (SPRUJ43 JULY 2022) : http://www.ti.com/lit/zip/spruj52
|
||||
*
|
||||
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/pinctrl/k3.h>
|
||||
#include <dt-bindings/soc/ti,sci_pm_domain.h>
|
||||
|
||||
/ {
|
||||
model = "Texas Instruments K3 J784S4 SoC";
|
||||
compatible = "ti,j784s4";
|
||||
interrupt-parent = <&gic500>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cpu-map {
|
||||
cluster0: cluster0 {
|
||||
core0 {
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&cpu1>;
|
||||
};
|
||||
|
||||
core2 {
|
||||
cpu = <&cpu2>;
|
||||
};
|
||||
|
||||
core3 {
|
||||
cpu = <&cpu3>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1: cluster1 {
|
||||
core0 {
|
||||
cpu = <&cpu4>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&cpu5>;
|
||||
};
|
||||
|
||||
core2 {
|
||||
cpu = <&cpu6>;
|
||||
};
|
||||
|
||||
core3 {
|
||||
cpu = <&cpu7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x000>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x001>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x002>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x003>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu4: cpu@100 {
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x100>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&L2_1>;
|
||||
};
|
||||
|
||||
cpu5: cpu@101 {
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x101>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&L2_1>;
|
||||
};
|
||||
|
||||
cpu6: cpu@102 {
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x102>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&L2_1>;
|
||||
};
|
||||
|
||||
cpu7: cpu@103 {
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x103>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&L2_1>;
|
||||
};
|
||||
};
|
||||
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
cache-size = <0x200000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <1024>;
|
||||
next-level-cache = <&msmc_l3>;
|
||||
};
|
||||
|
||||
L2_1: l2-cache1 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
cache-size = <0x200000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <1024>;
|
||||
next-level-cache = <&msmc_l3>;
|
||||
};
|
||||
|
||||
msmc_l3: l3-cache0 {
|
||||
compatible = "cache";
|
||||
cache-level = <3>;
|
||||
cache-unified;
|
||||
};
|
||||
|
||||
firmware {
|
||||
optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
psci: psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
|
||||
a72_timer0: timer-cl0-cpu0 {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
|
||||
};
|
||||
|
||||
pmu: pmu {
|
||||
compatible = "arm,cortex-a72-pmu";
|
||||
/* Recommendation from GIC500 TRM Table A.3 */
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
cbass_main: bus@100000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
|
||||
<0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
|
||||
<0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
|
||||
<0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/
|
||||
<0x00 0x10000000 0x00 0x10000000 0x00 0x08000000>, /* PCIe0 DAT0 */
|
||||
<0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
|
||||
<0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */
|
||||
<0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */
|
||||
<0x00 0x66800000 0x00 0x66800000 0x00 0x0070c000>, /* C71_3 */
|
||||
<0x00 0x67800000 0x00 0x67800000 0x00 0x0070c000>, /* C71_4 */
|
||||
<0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
|
||||
<0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */
|
||||
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
|
||||
<0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
|
||||
<0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
|
||||
|
||||
/* MCUSS_WKUP Range */
|
||||
<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
|
||||
<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
|
||||
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
|
||||
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
|
||||
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
|
||||
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
|
||||
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
|
||||
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
|
||||
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
|
||||
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
|
||||
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
|
||||
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
|
||||
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
|
||||
|
||||
cbass_mcu_wakeup: bus@28380000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
|
||||
<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
|
||||
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
|
||||
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
|
||||
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
|
||||
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
|
||||
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
|
||||
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
|
||||
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
|
||||
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
|
||||
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
|
||||
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
|
||||
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Now include peripherals from each bus segment */
|
||||
#include "k3-j784s4-main.dtsi"
|
||||
#include "k3-j784s4-mcu-wakeup.dtsi"
|
||||
|
|
@ -47,4 +47,7 @@
|
|||
#define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
#define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
|
||||
#define J784S4_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
#define J784S4_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue