ARM: dts: r7s72100: sort subnodes of soc node
Sort the subnodes of the soc node to improve maintainability. The sort key is the address on the bus with instances of the same IP block grouped together and sorted alphabetically. This patch should not introduce any functional change. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Simon Horman
parent
b1548238b2
commit
f7255d1fa2
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@ -110,6 +110,289 @@
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#size-cells = <1>;
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ranges;
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L2: cache-controller@3ffff000 {
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compatible = "arm,pl310-cache";
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reg = <0x3ffff000 0x1000>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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arm,early-bresp-disable;
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arm,full-line-zero-disable;
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cache-unified;
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cache-level = <2>;
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};
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scif0: serial@e8007000 {
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compatible = "renesas,scif-r7s72100", "renesas,scif";
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reg = <0xe8007000 64>;
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interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
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clock-names = "fck";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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scif1: serial@e8007800 {
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compatible = "renesas,scif-r7s72100", "renesas,scif";
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reg = <0xe8007800 64>;
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interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
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clock-names = "fck";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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scif2: serial@e8008000 {
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compatible = "renesas,scif-r7s72100", "renesas,scif";
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reg = <0xe8008000 64>;
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interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
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clock-names = "fck";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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scif3: serial@e8008800 {
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compatible = "renesas,scif-r7s72100", "renesas,scif";
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reg = <0xe8008800 64>;
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interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
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clock-names = "fck";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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scif4: serial@e8009000 {
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compatible = "renesas,scif-r7s72100", "renesas,scif";
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reg = <0xe8009000 64>;
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interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
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clock-names = "fck";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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scif5: serial@e8009800 {
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compatible = "renesas,scif-r7s72100", "renesas,scif";
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reg = <0xe8009800 64>;
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interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
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clock-names = "fck";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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scif6: serial@e800a000 {
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compatible = "renesas,scif-r7s72100", "renesas,scif";
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reg = <0xe800a000 64>;
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interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
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clock-names = "fck";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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scif7: serial@e800a800 {
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compatible = "renesas,scif-r7s72100", "renesas,scif";
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reg = <0xe800a800 64>;
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interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
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clock-names = "fck";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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spi0: spi@e800c800 {
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compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
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reg = <0xe800c800 0x24>;
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interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error", "rx", "tx";
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clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
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power-domains = <&cpg_clocks>;
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi1: spi@e800d000 {
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compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
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reg = <0xe800d000 0x24>;
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interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error", "rx", "tx";
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clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
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power-domains = <&cpg_clocks>;
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi2: spi@e800d800 {
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compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
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reg = <0xe800d800 0x24>;
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interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error", "rx", "tx";
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clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
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power-domains = <&cpg_clocks>;
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi3: spi@e800e000 {
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compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
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reg = <0xe800e000 0x24>;
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interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error", "rx", "tx";
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clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
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power-domains = <&cpg_clocks>;
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi4: spi@e800e800 {
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compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
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reg = <0xe800e800 0x24>;
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interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error", "rx", "tx";
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clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
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power-domains = <&cpg_clocks>;
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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usbhs0: usb@e8010000 {
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compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
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reg = <0xe8010000 0x1a0>;
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interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp7_clks R7S72100_CLK_USB0>;
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renesas,buswait = <4>;
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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usbhs1: usb@e8207000 {
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compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
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reg = <0xe8207000 0x1a0>;
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp7_clks R7S72100_CLK_USB1>;
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renesas,buswait = <4>;
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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mmcif: mmc@e804c800 {
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compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
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reg = <0xe804c800 0x80>;
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interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
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power-domains = <&cpg_clocks>;
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reg-io-width = <4>;
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bus-width = <8>;
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status = "disabled";
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};
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sdhi0: sd@e804e000 {
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compatible = "renesas,sdhi-r7s72100";
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reg = <0xe804e000 0x100>;
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interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
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<&mstp12_clks R7S72100_CLK_SDHI01>;
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clock-names = "core", "cd";
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power-domains = <&cpg_clocks>;
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cap-sd-highspeed;
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cap-sdio-irq;
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status = "disabled";
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};
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sdhi1: sd@e804e800 {
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compatible = "renesas,sdhi-r7s72100";
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reg = <0xe804e800 0x100>;
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interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
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<&mstp12_clks R7S72100_CLK_SDHI11>;
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clock-names = "core", "cd";
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power-domains = <&cpg_clocks>;
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cap-sd-highspeed;
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cap-sdio-irq;
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status = "disabled";
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};
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gic: interrupt-controller@e8201000 {
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compatible = "arm,pl390";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0xe8201000 0x1000>,
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<0xe8202000 0x1000>;
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};
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ether: ethernet@e8203000 {
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compatible = "renesas,ether-r7s72100";
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reg = <0xe8203000 0x800>,
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<0xe8204800 0x200>;
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interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
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power-domains = <&cpg_clocks>;
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phy-mode = "mii";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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wdt: watchdog@fcfe0000 {
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compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
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reg = <0xfcfe0000 0x6>;
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interrupts = <GIC_SPI 106 IRQ_TYPE_EDGE_RISING>;
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clocks = <&p0_clk>;
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};
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/* Special CPG clocks */
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cpg_clocks: cpg_clocks@fcfe0000 {
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#clock-cells = <1>;
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@ -293,211 +576,24 @@
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};
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};
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scif0: serial@e8007000 {
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compatible = "renesas,scif-r7s72100", "renesas,scif";
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reg = <0xe8007000 64>;
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interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
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clock-names = "fck";
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ostm0: timer@fcfec000 {
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compatible = "renesas,r7s72100-ostm", "renesas,ostm";
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reg = <0xfcfec000 0x30>;
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interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
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clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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scif1: serial@e8007800 {
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compatible = "renesas,scif-r7s72100", "renesas,scif";
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reg = <0xe8007800 64>;
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interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
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clock-names = "fck";
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ostm1: timer@fcfec400 {
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compatible = "renesas,r7s72100-ostm", "renesas,ostm";
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reg = <0xfcfec400 0x30>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;
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clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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scif2: serial@e8008000 {
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compatible = "renesas,scif-r7s72100", "renesas,scif";
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reg = <0xe8008000 64>;
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interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
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clock-names = "fck";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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scif3: serial@e8008800 {
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compatible = "renesas,scif-r7s72100", "renesas,scif";
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reg = <0xe8008800 64>;
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interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
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clock-names = "fck";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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scif4: serial@e8009000 {
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compatible = "renesas,scif-r7s72100", "renesas,scif";
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reg = <0xe8009000 64>;
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interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
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clock-names = "fck";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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scif5: serial@e8009800 {
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compatible = "renesas,scif-r7s72100", "renesas,scif";
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reg = <0xe8009800 64>;
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interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
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clock-names = "fck";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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scif6: serial@e800a000 {
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compatible = "renesas,scif-r7s72100", "renesas,scif";
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reg = <0xe800a000 64>;
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interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scif7: serial@e800a800 {
|
||||
compatible = "renesas,scif-r7s72100", "renesas,scif";
|
||||
reg = <0xe800a800 64>;
|
||||
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi@e800c800 {
|
||||
compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
|
||||
reg = <0xe800c800 0x24>;
|
||||
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error", "rx", "tx";
|
||||
clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
num-cs = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@e800d000 {
|
||||
compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
|
||||
reg = <0xe800d000 0x24>;
|
||||
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error", "rx", "tx";
|
||||
clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
num-cs = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi2: spi@e800d800 {
|
||||
compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
|
||||
reg = <0xe800d800 0x24>;
|
||||
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error", "rx", "tx";
|
||||
clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
num-cs = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi3: spi@e800e000 {
|
||||
compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
|
||||
reg = <0xe800e000 0x24>;
|
||||
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error", "rx", "tx";
|
||||
clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
num-cs = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi4: spi@e800e800 {
|
||||
compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
|
||||
reg = <0xe800e800 0x24>;
|
||||
interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error", "rx", "tx";
|
||||
clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
num-cs = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@e8201000 {
|
||||
compatible = "arm,pl390";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0xe8201000 0x1000>,
|
||||
<0xe8202000 0x1000>;
|
||||
};
|
||||
|
||||
L2: cache-controller@3ffff000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x3ffff000 0x1000>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
arm,early-bresp-disable;
|
||||
arm,full-line-zero-disable;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
wdt: watchdog@fcfe0000 {
|
||||
compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
|
||||
reg = <0xfcfe0000 0x6>;
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&p0_clk>;
|
||||
};
|
||||
|
||||
i2c0: i2c@fcfee000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -585,82 +681,6 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ether: ethernet@e8203000 {
|
||||
compatible = "renesas,ether-r7s72100";
|
||||
reg = <0xe8203000 0x800>,
|
||||
<0xe8204800 0x200>;
|
||||
interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
phy-mode = "mii";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmcif: mmc@e804c800 {
|
||||
compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
|
||||
reg = <0xe804c800 0x80>;
|
||||
interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
reg-io-width = <4>;
|
||||
bus-width = <8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi0: sd@e804e000 {
|
||||
compatible = "renesas,sdhi-r7s72100";
|
||||
reg = <0xe804e000 0x100>;
|
||||
interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
|
||||
<&mstp12_clks R7S72100_CLK_SDHI01>;
|
||||
clock-names = "core", "cd";
|
||||
power-domains = <&cpg_clocks>;
|
||||
cap-sd-highspeed;
|
||||
cap-sdio-irq;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi1: sd@e804e800 {
|
||||
compatible = "renesas,sdhi-r7s72100";
|
||||
reg = <0xe804e800 0x100>;
|
||||
interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
|
||||
<&mstp12_clks R7S72100_CLK_SDHI11>;
|
||||
clock-names = "core", "cd";
|
||||
power-domains = <&cpg_clocks>;
|
||||
cap-sd-highspeed;
|
||||
cap-sdio-irq;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ostm0: timer@fcfec000 {
|
||||
compatible = "renesas,r7s72100-ostm", "renesas,ostm";
|
||||
reg = <0xfcfec000 0x30>;
|
||||
interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ostm1: timer@fcfec400 {
|
||||
compatible = "renesas,r7s72100-ostm", "renesas,ostm";
|
||||
reg = <0xfcfec400 0x30>;
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc: rtc@fcff1000 {
|
||||
compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc";
|
||||
reg = <0xfcff1000 0x2e>;
|
||||
|
|
@ -674,25 +694,5 @@
|
|||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbhs0: usb@e8010000 {
|
||||
compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
|
||||
reg = <0xe8010000 0x1a0>;
|
||||
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp7_clks R7S72100_CLK_USB0>;
|
||||
renesas,buswait = <4>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbhs1: usb@e8207000 {
|
||||
compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
|
||||
reg = <0xe8207000 0x1a0>;
|
||||
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp7_clks R7S72100_CLK_USB1>;
|
||||
renesas,buswait = <4>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue