ASoC: mediatek: mt8188: support audio clock control
Add audio clock wrapper and audio tuner control. Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230116034131.23943-8-trevor.wu@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Trevor Wu
Mark Brown
parent
5d43bdd712
commit
f6b026479b
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@ -0,0 +1,658 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* mt8188-afe-clk.c -- MediaTek 8188 afe clock ctrl
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*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
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* Trevor Wu <trevor.wu@mediatek.com>
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* Chun-Chia Chiu <chun-chia.chiu@mediatek.com>
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*/
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#include <linux/clk.h>
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#include "mt8188-afe-common.h"
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#include "mt8188-afe-clk.h"
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#include "mt8188-audsys-clk.h"
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#include "mt8188-reg.h"
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static const char *aud_clks[MT8188_CLK_NUM] = {
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/* xtal */
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[MT8188_CLK_XTAL_26M] = "clk26m",
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/* pll */
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[MT8188_CLK_APMIXED_APLL1] = "apll1",
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[MT8188_CLK_APMIXED_APLL2] = "apll2",
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/* divider */
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[MT8188_CLK_TOP_APLL12_DIV0] = "apll12_div0",
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[MT8188_CLK_TOP_APLL12_DIV1] = "apll12_div1",
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[MT8188_CLK_TOP_APLL12_DIV2] = "apll12_div2",
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[MT8188_CLK_TOP_APLL12_DIV3] = "apll12_div3",
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[MT8188_CLK_TOP_APLL12_DIV9] = "apll12_div9",
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/* mux */
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[MT8188_CLK_TOP_A1SYS_HP_SEL] = "top_a1sys_hp",
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[MT8188_CLK_TOP_AUD_INTBUS_SEL] = "top_aud_intbus",
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[MT8188_CLK_TOP_AUDIO_H_SEL] = "top_audio_h",
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[MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL] = "top_audio_local_bus",
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[MT8188_CLK_TOP_DPTX_M_SEL] = "top_dptx",
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[MT8188_CLK_TOP_I2SO1_M_SEL] = "top_i2so1",
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[MT8188_CLK_TOP_I2SO2_M_SEL] = "top_i2so2",
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[MT8188_CLK_TOP_I2SI1_M_SEL] = "top_i2si1",
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[MT8188_CLK_TOP_I2SI2_M_SEL] = "top_i2si2",
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/* clock gate */
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[MT8188_CLK_ADSP_AUDIO_26M] = "adsp_audio_26m",
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/* afe clock gate */
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[MT8188_CLK_AUD_AFE] = "aud_afe",
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[MT8188_CLK_AUD_APLL1_TUNER] = "aud_apll1_tuner",
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[MT8188_CLK_AUD_APLL2_TUNER] = "aud_apll2_tuner",
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[MT8188_CLK_AUD_APLL] = "aud_apll",
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[MT8188_CLK_AUD_APLL2] = "aud_apll2",
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[MT8188_CLK_AUD_DAC] = "aud_dac",
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[MT8188_CLK_AUD_ADC] = "aud_adc",
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[MT8188_CLK_AUD_DAC_HIRES] = "aud_dac_hires",
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[MT8188_CLK_AUD_A1SYS_HP] = "aud_a1sys_hp",
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[MT8188_CLK_AUD_ADC_HIRES] = "aud_adc_hires",
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[MT8188_CLK_AUD_I2SIN] = "aud_i2sin",
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[MT8188_CLK_AUD_TDM_IN] = "aud_tdm_in",
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[MT8188_CLK_AUD_I2S_OUT] = "aud_i2s_out",
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[MT8188_CLK_AUD_TDM_OUT] = "aud_tdm_out",
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[MT8188_CLK_AUD_HDMI_OUT] = "aud_hdmi_out",
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[MT8188_CLK_AUD_ASRC11] = "aud_asrc11",
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[MT8188_CLK_AUD_ASRC12] = "aud_asrc12",
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[MT8188_CLK_AUD_A1SYS] = "aud_a1sys",
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[MT8188_CLK_AUD_A2SYS] = "aud_a2sys",
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[MT8188_CLK_AUD_PCMIF] = "aud_pcmif",
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[MT8188_CLK_AUD_MEMIF_UL1] = "aud_memif_ul1",
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[MT8188_CLK_AUD_MEMIF_UL2] = "aud_memif_ul2",
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[MT8188_CLK_AUD_MEMIF_UL3] = "aud_memif_ul3",
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[MT8188_CLK_AUD_MEMIF_UL4] = "aud_memif_ul4",
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[MT8188_CLK_AUD_MEMIF_UL5] = "aud_memif_ul5",
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[MT8188_CLK_AUD_MEMIF_UL6] = "aud_memif_ul6",
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[MT8188_CLK_AUD_MEMIF_UL8] = "aud_memif_ul8",
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[MT8188_CLK_AUD_MEMIF_UL9] = "aud_memif_ul9",
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[MT8188_CLK_AUD_MEMIF_UL10] = "aud_memif_ul10",
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[MT8188_CLK_AUD_MEMIF_DL2] = "aud_memif_dl2",
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[MT8188_CLK_AUD_MEMIF_DL3] = "aud_memif_dl3",
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[MT8188_CLK_AUD_MEMIF_DL6] = "aud_memif_dl6",
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[MT8188_CLK_AUD_MEMIF_DL7] = "aud_memif_dl7",
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[MT8188_CLK_AUD_MEMIF_DL8] = "aud_memif_dl8",
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[MT8188_CLK_AUD_MEMIF_DL10] = "aud_memif_dl10",
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[MT8188_CLK_AUD_MEMIF_DL11] = "aud_memif_dl11",
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};
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struct mt8188_afe_tuner_cfg {
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unsigned int id;
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int apll_div_reg;
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unsigned int apll_div_shift;
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unsigned int apll_div_maskbit;
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unsigned int apll_div_default;
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int ref_ck_sel_reg;
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unsigned int ref_ck_sel_shift;
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unsigned int ref_ck_sel_maskbit;
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unsigned int ref_ck_sel_default;
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int tuner_en_reg;
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unsigned int tuner_en_shift;
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unsigned int tuner_en_maskbit;
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int upper_bound_reg;
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unsigned int upper_bound_shift;
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unsigned int upper_bound_maskbit;
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unsigned int upper_bound_default;
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spinlock_t ctrl_lock; /* lock for apll tuner ctrl*/
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int ref_cnt;
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};
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static struct mt8188_afe_tuner_cfg
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mt8188_afe_tuner_cfgs[MT8188_AUD_PLL_NUM] = {
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[MT8188_AUD_PLL1] = {
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.id = MT8188_AUD_PLL1,
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.apll_div_reg = AFE_APLL_TUNER_CFG,
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.apll_div_shift = 4,
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.apll_div_maskbit = 0xf,
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.apll_div_default = 0x7,
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.ref_ck_sel_reg = AFE_APLL_TUNER_CFG,
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.ref_ck_sel_shift = 1,
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.ref_ck_sel_maskbit = 0x3,
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.ref_ck_sel_default = 0x2,
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.tuner_en_reg = AFE_APLL_TUNER_CFG,
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.tuner_en_shift = 0,
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.tuner_en_maskbit = 0x1,
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.upper_bound_reg = AFE_APLL_TUNER_CFG,
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.upper_bound_shift = 8,
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.upper_bound_maskbit = 0xff,
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.upper_bound_default = 0x3,
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},
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[MT8188_AUD_PLL2] = {
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.id = MT8188_AUD_PLL2,
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.apll_div_reg = AFE_APLL_TUNER_CFG1,
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.apll_div_shift = 4,
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.apll_div_maskbit = 0xf,
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.apll_div_default = 0x7,
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.ref_ck_sel_reg = AFE_APLL_TUNER_CFG1,
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.ref_ck_sel_shift = 1,
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.ref_ck_sel_maskbit = 0x3,
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.ref_ck_sel_default = 0x1,
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.tuner_en_reg = AFE_APLL_TUNER_CFG1,
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.tuner_en_shift = 0,
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.tuner_en_maskbit = 0x1,
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.upper_bound_reg = AFE_APLL_TUNER_CFG1,
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.upper_bound_shift = 8,
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.upper_bound_maskbit = 0xff,
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.upper_bound_default = 0x3,
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},
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[MT8188_AUD_PLL3] = {
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.id = MT8188_AUD_PLL3,
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.apll_div_reg = AFE_EARC_APLL_TUNER_CFG,
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.apll_div_shift = 4,
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.apll_div_maskbit = 0x3f,
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.apll_div_default = 0x3,
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.ref_ck_sel_reg = AFE_EARC_APLL_TUNER_CFG,
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.ref_ck_sel_shift = 24,
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.ref_ck_sel_maskbit = 0x3,
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.ref_ck_sel_default = 0x0,
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.tuner_en_reg = AFE_EARC_APLL_TUNER_CFG,
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.tuner_en_shift = 0,
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.tuner_en_maskbit = 0x1,
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.upper_bound_reg = AFE_EARC_APLL_TUNER_CFG,
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.upper_bound_shift = 12,
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.upper_bound_maskbit = 0xff,
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.upper_bound_default = 0x4,
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},
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[MT8188_AUD_PLL4] = {
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.id = MT8188_AUD_PLL4,
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.apll_div_reg = AFE_SPDIFIN_APLL_TUNER_CFG,
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.apll_div_shift = 4,
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.apll_div_maskbit = 0x3f,
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.apll_div_default = 0x7,
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.ref_ck_sel_reg = AFE_SPDIFIN_APLL_TUNER_CFG1,
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.ref_ck_sel_shift = 8,
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.ref_ck_sel_maskbit = 0x1,
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.ref_ck_sel_default = 0,
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.tuner_en_reg = AFE_SPDIFIN_APLL_TUNER_CFG,
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.tuner_en_shift = 0,
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.tuner_en_maskbit = 0x1,
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.upper_bound_reg = AFE_SPDIFIN_APLL_TUNER_CFG,
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.upper_bound_shift = 12,
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.upper_bound_maskbit = 0xff,
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.upper_bound_default = 0x4,
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},
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[MT8188_AUD_PLL5] = {
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.id = MT8188_AUD_PLL5,
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.apll_div_reg = AFE_LINEIN_APLL_TUNER_CFG,
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.apll_div_shift = 4,
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.apll_div_maskbit = 0x3f,
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.apll_div_default = 0x3,
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.ref_ck_sel_reg = AFE_LINEIN_APLL_TUNER_CFG,
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.ref_ck_sel_shift = 24,
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.ref_ck_sel_maskbit = 0x1,
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.ref_ck_sel_default = 0,
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.tuner_en_reg = AFE_LINEIN_APLL_TUNER_CFG,
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.tuner_en_shift = 0,
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.tuner_en_maskbit = 0x1,
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.upper_bound_reg = AFE_LINEIN_APLL_TUNER_CFG,
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.upper_bound_shift = 12,
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.upper_bound_maskbit = 0xff,
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.upper_bound_default = 0x4,
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},
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};
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static struct mt8188_afe_tuner_cfg *mt8188_afe_found_apll_tuner(unsigned int id)
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{
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if (id >= MT8188_AUD_PLL_NUM)
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return NULL;
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return &mt8188_afe_tuner_cfgs[id];
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}
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static int mt8188_afe_init_apll_tuner(unsigned int id)
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{
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struct mt8188_afe_tuner_cfg *cfg = mt8188_afe_found_apll_tuner(id);
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if (!cfg)
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return -EINVAL;
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cfg->ref_cnt = 0;
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spin_lock_init(&cfg->ctrl_lock);
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return 0;
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}
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static int mt8188_afe_setup_apll_tuner(struct mtk_base_afe *afe, unsigned int id)
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{
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const struct mt8188_afe_tuner_cfg *cfg = mt8188_afe_found_apll_tuner(id);
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if (!cfg)
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return -EINVAL;
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regmap_update_bits(afe->regmap,
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cfg->apll_div_reg,
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cfg->apll_div_maskbit << cfg->apll_div_shift,
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cfg->apll_div_default << cfg->apll_div_shift);
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regmap_update_bits(afe->regmap,
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cfg->ref_ck_sel_reg,
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cfg->ref_ck_sel_maskbit << cfg->ref_ck_sel_shift,
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cfg->ref_ck_sel_default << cfg->ref_ck_sel_shift);
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regmap_update_bits(afe->regmap,
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cfg->upper_bound_reg,
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cfg->upper_bound_maskbit << cfg->upper_bound_shift,
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cfg->upper_bound_default << cfg->upper_bound_shift);
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return 0;
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}
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static int mt8188_afe_enable_tuner_clk(struct mtk_base_afe *afe,
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unsigned int id)
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{
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struct mt8188_afe_private *afe_priv = afe->platform_priv;
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switch (id) {
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case MT8188_AUD_PLL1:
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mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL]);
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mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL1_TUNER]);
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break;
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case MT8188_AUD_PLL2:
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mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2]);
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mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2_TUNER]);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int mt8188_afe_disable_tuner_clk(struct mtk_base_afe *afe,
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unsigned int id)
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{
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struct mt8188_afe_private *afe_priv = afe->platform_priv;
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switch (id) {
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case MT8188_AUD_PLL1:
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mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL1_TUNER]);
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mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL]);
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break;
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case MT8188_AUD_PLL2:
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mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2_TUNER]);
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mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2]);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int mt8188_afe_enable_apll_tuner(struct mtk_base_afe *afe, unsigned int id)
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{
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struct mt8188_afe_tuner_cfg *cfg = mt8188_afe_found_apll_tuner(id);
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unsigned long flags;
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int ret;
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if (!cfg)
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return -EINVAL;
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ret = mt8188_afe_setup_apll_tuner(afe, id);
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if (ret)
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return ret;
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ret = mt8188_afe_enable_tuner_clk(afe, id);
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if (ret)
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return ret;
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spin_lock_irqsave(&cfg->ctrl_lock, flags);
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cfg->ref_cnt++;
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if (cfg->ref_cnt == 1)
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regmap_update_bits(afe->regmap,
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cfg->tuner_en_reg,
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cfg->tuner_en_maskbit << cfg->tuner_en_shift,
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BIT(cfg->tuner_en_shift));
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spin_unlock_irqrestore(&cfg->ctrl_lock, flags);
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return 0;
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}
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static int mt8188_afe_disable_apll_tuner(struct mtk_base_afe *afe, unsigned int id)
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{
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struct mt8188_afe_tuner_cfg *cfg = mt8188_afe_found_apll_tuner(id);
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unsigned long flags;
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int ret;
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if (!cfg)
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return -EINVAL;
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spin_lock_irqsave(&cfg->ctrl_lock, flags);
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cfg->ref_cnt--;
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if (cfg->ref_cnt == 0)
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regmap_update_bits(afe->regmap,
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cfg->tuner_en_reg,
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cfg->tuner_en_maskbit << cfg->tuner_en_shift,
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0 << cfg->tuner_en_shift);
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else if (cfg->ref_cnt < 0)
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cfg->ref_cnt = 0;
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spin_unlock_irqrestore(&cfg->ctrl_lock, flags);
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ret = mt8188_afe_disable_tuner_clk(afe, id);
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if (ret)
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return ret;
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return 0;
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}
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int mt8188_afe_get_mclk_source_clk_id(int sel)
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{
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switch (sel) {
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case MT8188_MCK_SEL_26M:
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return MT8188_CLK_XTAL_26M;
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case MT8188_MCK_SEL_APLL1:
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return MT8188_CLK_APMIXED_APLL1;
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case MT8188_MCK_SEL_APLL2:
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return MT8188_CLK_APMIXED_APLL2;
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default:
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return -EINVAL;
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}
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}
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int mt8188_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll)
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{
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struct mt8188_afe_private *afe_priv = afe->platform_priv;
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int clk_id = mt8188_afe_get_mclk_source_clk_id(apll);
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if (clk_id < 0) {
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dev_dbg(afe->dev, "invalid clk id\n");
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return 0;
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}
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return clk_get_rate(afe_priv->clk[clk_id]);
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}
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int mt8188_afe_get_default_mclk_source_by_rate(int rate)
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{
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return ((rate % 8000) == 0) ?
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MT8188_MCK_SEL_APLL1 : MT8188_MCK_SEL_APLL2;
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}
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int mt8188_afe_init_clock(struct mtk_base_afe *afe)
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{
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struct mt8188_afe_private *afe_priv = afe->platform_priv;
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int i, ret;
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|
||||
ret = mt8188_audsys_clk_register(afe);
|
||||
if (ret) {
|
||||
dev_err(afe->dev, "register audsys clk fail %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
afe_priv->clk =
|
||||
devm_kcalloc(afe->dev, MT8188_CLK_NUM, sizeof(*afe_priv->clk),
|
||||
GFP_KERNEL);
|
||||
if (!afe_priv->clk)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < MT8188_CLK_NUM; i++) {
|
||||
afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
|
||||
if (IS_ERR(afe_priv->clk[i])) {
|
||||
dev_err(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n",
|
||||
__func__, aud_clks[i],
|
||||
PTR_ERR(afe_priv->clk[i]));
|
||||
return PTR_ERR(afe_priv->clk[i]);
|
||||
}
|
||||
}
|
||||
|
||||
/* initial tuner */
|
||||
for (i = 0; i < MT8188_AUD_PLL_NUM; i++) {
|
||||
ret = mt8188_afe_init_apll_tuner(i);
|
||||
if (ret) {
|
||||
dev_info(afe->dev, "%s(), init apll_tuner%d failed",
|
||||
__func__, (i + 1));
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void mt8188_afe_deinit_clock(void *priv)
|
||||
{
|
||||
struct mtk_base_afe *afe = priv;
|
||||
|
||||
mt8188_audsys_clk_unregister(afe);
|
||||
}
|
||||
|
||||
int mt8188_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (clk) {
|
||||
ret = clk_prepare_enable(clk);
|
||||
if (ret) {
|
||||
dev_dbg(afe->dev, "%s(), failed to enable clk\n",
|
||||
__func__);
|
||||
return ret;
|
||||
}
|
||||
} else {
|
||||
dev_dbg(afe->dev, "NULL clk\n");
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(mt8188_afe_enable_clk);
|
||||
|
||||
void mt8188_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk)
|
||||
{
|
||||
if (clk)
|
||||
clk_disable_unprepare(clk);
|
||||
else
|
||||
dev_dbg(afe->dev, "NULL clk\n");
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(mt8188_afe_disable_clk);
|
||||
|
||||
int mt8188_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
|
||||
unsigned int rate)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (clk) {
|
||||
ret = clk_set_rate(clk, rate);
|
||||
if (ret) {
|
||||
dev_dbg(afe->dev, "%s(), failed to set clk rate\n",
|
||||
__func__);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mt8188_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
|
||||
struct clk *parent)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (clk && parent) {
|
||||
ret = clk_set_parent(clk, parent);
|
||||
if (ret) {
|
||||
dev_dbg(afe->dev, "%s(), failed to set clk parent\n",
|
||||
__func__);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned int get_top_cg_reg(unsigned int cg_type)
|
||||
{
|
||||
switch (cg_type) {
|
||||
case MT8188_TOP_CG_A1SYS_TIMING:
|
||||
case MT8188_TOP_CG_A2SYS_TIMING:
|
||||
case MT8188_TOP_CG_26M_TIMING:
|
||||
return ASYS_TOP_CON;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static unsigned int get_top_cg_mask(unsigned int cg_type)
|
||||
{
|
||||
switch (cg_type) {
|
||||
case MT8188_TOP_CG_A1SYS_TIMING:
|
||||
return ASYS_TOP_CON_A1SYS_TIMING_ON;
|
||||
case MT8188_TOP_CG_A2SYS_TIMING:
|
||||
return ASYS_TOP_CON_A2SYS_TIMING_ON;
|
||||
case MT8188_TOP_CG_26M_TIMING:
|
||||
return ASYS_TOP_CON_26M_TIMING_ON;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static unsigned int get_top_cg_on_val(unsigned int cg_type)
|
||||
{
|
||||
switch (cg_type) {
|
||||
case MT8188_TOP_CG_A1SYS_TIMING:
|
||||
case MT8188_TOP_CG_A2SYS_TIMING:
|
||||
case MT8188_TOP_CG_26M_TIMING:
|
||||
return get_top_cg_mask(cg_type);
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static unsigned int get_top_cg_off_val(unsigned int cg_type)
|
||||
{
|
||||
switch (cg_type) {
|
||||
case MT8188_TOP_CG_A1SYS_TIMING:
|
||||
case MT8188_TOP_CG_A2SYS_TIMING:
|
||||
case MT8188_TOP_CG_26M_TIMING:
|
||||
return 0;
|
||||
default:
|
||||
return get_top_cg_mask(cg_type);
|
||||
}
|
||||
}
|
||||
|
||||
static int mt8188_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
|
||||
{
|
||||
unsigned int reg = get_top_cg_reg(cg_type);
|
||||
unsigned int mask = get_top_cg_mask(cg_type);
|
||||
unsigned int val = get_top_cg_on_val(cg_type);
|
||||
|
||||
regmap_update_bits(afe->regmap, reg, mask, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mt8188_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
|
||||
{
|
||||
unsigned int reg = get_top_cg_reg(cg_type);
|
||||
unsigned int mask = get_top_cg_mask(cg_type);
|
||||
unsigned int val = get_top_cg_off_val(cg_type);
|
||||
|
||||
regmap_update_bits(afe->regmap, reg, mask, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mt8188_afe_enable_reg_rw_clk(struct mtk_base_afe *afe)
|
||||
{
|
||||
struct mt8188_afe_private *afe_priv = afe->platform_priv;
|
||||
|
||||
/* bus clock for AFE external access, like DRAM */
|
||||
mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL]);
|
||||
|
||||
/* bus clock for AFE internal access, like AFE SRAM */
|
||||
mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUD_INTBUS_SEL]);
|
||||
|
||||
/* audio 26m clock source */
|
||||
mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_ADSP_AUDIO_26M]);
|
||||
|
||||
/* AFE hw clock */
|
||||
mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE]);
|
||||
mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS_HP]);
|
||||
mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mt8188_afe_disable_reg_rw_clk(struct mtk_base_afe *afe)
|
||||
{
|
||||
struct mt8188_afe_private *afe_priv = afe->platform_priv;
|
||||
|
||||
mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);
|
||||
mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS_HP]);
|
||||
mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE]);
|
||||
mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_ADSP_AUDIO_26M]);
|
||||
mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUD_INTBUS_SEL]);
|
||||
mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mt8188_afe_enable_afe_on(struct mtk_base_afe *afe)
|
||||
{
|
||||
regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mt8188_afe_disable_afe_on(struct mtk_base_afe *afe)
|
||||
{
|
||||
regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mt8188_afe_enable_timing_sys(struct mtk_base_afe *afe)
|
||||
{
|
||||
struct mt8188_afe_private *afe_priv = afe->platform_priv;
|
||||
|
||||
mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);
|
||||
mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A2SYS]);
|
||||
|
||||
mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_A1SYS_TIMING);
|
||||
mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_A2SYS_TIMING);
|
||||
mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_26M_TIMING);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mt8188_afe_disable_timing_sys(struct mtk_base_afe *afe)
|
||||
{
|
||||
struct mt8188_afe_private *afe_priv = afe->platform_priv;
|
||||
|
||||
mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);
|
||||
mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A2SYS]);
|
||||
|
||||
mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_26M_TIMING);
|
||||
mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_A2SYS_TIMING);
|
||||
mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_A1SYS_TIMING);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mt8188_afe_enable_main_clock(struct mtk_base_afe *afe)
|
||||
{
|
||||
mt8188_afe_enable_timing_sys(afe);
|
||||
|
||||
mt8188_afe_enable_afe_on(afe);
|
||||
|
||||
mt8188_afe_enable_apll_tuner(afe, MT8188_AUD_PLL1);
|
||||
mt8188_afe_enable_apll_tuner(afe, MT8188_AUD_PLL2);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mt8188_afe_disable_main_clock(struct mtk_base_afe *afe)
|
||||
{
|
||||
mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL2);
|
||||
mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL1);
|
||||
|
||||
mt8188_afe_disable_afe_on(afe);
|
||||
|
||||
mt8188_afe_disable_timing_sys(afe);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,115 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* mt8188-afe-clk.h -- MediaTek 8188 afe clock ctrl definition
|
||||
*
|
||||
* Copyright (c) 2022 MediaTek Inc.
|
||||
* Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
|
||||
* Trevor Wu <trevor.wu@mediatek.com>
|
||||
* Chun-Chia Chiu <chun-chia.chiu@mediatek.com>
|
||||
*/
|
||||
|
||||
#ifndef _MT8188_AFE_CLK_H_
|
||||
#define _MT8188_AFE_CLK_H_
|
||||
|
||||
enum {
|
||||
/* xtal */
|
||||
MT8188_CLK_XTAL_26M,
|
||||
/* pll */
|
||||
MT8188_CLK_APMIXED_APLL1,
|
||||
MT8188_CLK_APMIXED_APLL2,
|
||||
/* divider */
|
||||
MT8188_CLK_TOP_APLL12_DIV0,
|
||||
MT8188_CLK_TOP_APLL12_DIV1,
|
||||
MT8188_CLK_TOP_APLL12_DIV2,
|
||||
MT8188_CLK_TOP_APLL12_DIV3,
|
||||
MT8188_CLK_TOP_APLL12_DIV9,
|
||||
/* mux */
|
||||
MT8188_CLK_TOP_A1SYS_HP_SEL,
|
||||
MT8188_CLK_TOP_AUD_INTBUS_SEL,
|
||||
MT8188_CLK_TOP_AUDIO_H_SEL,
|
||||
MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL,
|
||||
MT8188_CLK_TOP_DPTX_M_SEL,
|
||||
MT8188_CLK_TOP_I2SO1_M_SEL,
|
||||
MT8188_CLK_TOP_I2SO2_M_SEL,
|
||||
MT8188_CLK_TOP_I2SI1_M_SEL,
|
||||
MT8188_CLK_TOP_I2SI2_M_SEL,
|
||||
/* clock gate */
|
||||
MT8188_CLK_ADSP_AUDIO_26M,
|
||||
MT8188_CLK_AUD_AFE,
|
||||
MT8188_CLK_AUD_APLL1_TUNER,
|
||||
MT8188_CLK_AUD_APLL2_TUNER,
|
||||
MT8188_CLK_AUD_TOP0_SPDF,
|
||||
MT8188_CLK_AUD_APLL,
|
||||
MT8188_CLK_AUD_APLL2,
|
||||
MT8188_CLK_AUD_DAC,
|
||||
MT8188_CLK_AUD_ADC,
|
||||
MT8188_CLK_AUD_DAC_HIRES,
|
||||
MT8188_CLK_AUD_A1SYS_HP,
|
||||
MT8188_CLK_AUD_ADC_HIRES,
|
||||
MT8188_CLK_AUD_I2SIN,
|
||||
MT8188_CLK_AUD_TDM_IN,
|
||||
MT8188_CLK_AUD_I2S_OUT,
|
||||
MT8188_CLK_AUD_TDM_OUT,
|
||||
MT8188_CLK_AUD_HDMI_OUT,
|
||||
MT8188_CLK_AUD_ASRC11,
|
||||
MT8188_CLK_AUD_ASRC12,
|
||||
MT8188_CLK_AUD_A1SYS,
|
||||
MT8188_CLK_AUD_A2SYS,
|
||||
MT8188_CLK_AUD_PCMIF,
|
||||
MT8188_CLK_AUD_MEMIF_UL1,
|
||||
MT8188_CLK_AUD_MEMIF_UL2,
|
||||
MT8188_CLK_AUD_MEMIF_UL3,
|
||||
MT8188_CLK_AUD_MEMIF_UL4,
|
||||
MT8188_CLK_AUD_MEMIF_UL5,
|
||||
MT8188_CLK_AUD_MEMIF_UL6,
|
||||
MT8188_CLK_AUD_MEMIF_UL8,
|
||||
MT8188_CLK_AUD_MEMIF_UL9,
|
||||
MT8188_CLK_AUD_MEMIF_UL10,
|
||||
MT8188_CLK_AUD_MEMIF_DL2,
|
||||
MT8188_CLK_AUD_MEMIF_DL3,
|
||||
MT8188_CLK_AUD_MEMIF_DL6,
|
||||
MT8188_CLK_AUD_MEMIF_DL7,
|
||||
MT8188_CLK_AUD_MEMIF_DL8,
|
||||
MT8188_CLK_AUD_MEMIF_DL10,
|
||||
MT8188_CLK_AUD_MEMIF_DL11,
|
||||
MT8188_CLK_NUM,
|
||||
};
|
||||
|
||||
enum {
|
||||
MT8188_AUD_PLL1,
|
||||
MT8188_AUD_PLL2,
|
||||
MT8188_AUD_PLL3,
|
||||
MT8188_AUD_PLL4,
|
||||
MT8188_AUD_PLL5,
|
||||
MT8188_AUD_PLL_NUM,
|
||||
};
|
||||
|
||||
enum {
|
||||
MT8188_MCK_SEL_26M,
|
||||
MT8188_MCK_SEL_APLL1,
|
||||
MT8188_MCK_SEL_APLL2,
|
||||
MT8188_MCK_SEL_APLL3,
|
||||
MT8188_MCK_SEL_APLL4,
|
||||
MT8188_MCK_SEL_APLL5,
|
||||
MT8188_MCK_SEL_NUM,
|
||||
};
|
||||
|
||||
struct mtk_base_afe;
|
||||
|
||||
int mt8188_afe_get_mclk_source_clk_id(int sel);
|
||||
int mt8188_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll);
|
||||
int mt8188_afe_get_default_mclk_source_by_rate(int rate);
|
||||
int mt8188_afe_init_clock(struct mtk_base_afe *afe);
|
||||
void mt8188_afe_deinit_clock(void *priv);
|
||||
int mt8188_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk);
|
||||
void mt8188_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk);
|
||||
int mt8188_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
|
||||
unsigned int rate);
|
||||
int mt8188_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
|
||||
struct clk *parent);
|
||||
int mt8188_afe_enable_main_clock(struct mtk_base_afe *afe);
|
||||
int mt8188_afe_disable_main_clock(struct mtk_base_afe *afe);
|
||||
int mt8188_afe_enable_reg_rw_clk(struct mtk_base_afe *afe);
|
||||
int mt8188_afe_disable_reg_rw_clk(struct mtk_base_afe *afe);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue