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ath9k_hw: Add carrier leak correction in desired gain calculation 

Cc: muddin@qca.qualcomm.com
Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Mohammed Shafi Shajakhan 2011-06-23 20:03:38 +05:30 committed by John W. Linville
parent dcfcbd590d
commit f68e20f0f8
2 changed files with 27 additions and 10 deletions
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34
drivers/net/wireless/ath/ath9k/ar9003_paprd.c
View File

@ -246,13 +246,13 @@ static void ar9003_paprd_get_gain_table(struct ath_hw *ah)
static unsigned int ar9003_get_desired_gain(struct ath_hw *ah, int chain, static unsigned int ar9003_get_desired_gain(struct ath_hw *ah, int chain,
int target_power) int target_power)
{ {
int olpc_gain_delta = 0; int olpc_gain_delta = 0, cl_gain_mod;
int alpha_therm, alpha_volt; int alpha_therm, alpha_volt;
int therm_cal_value, volt_cal_value; int therm_cal_value, volt_cal_value;
int therm_value, volt_value; int therm_value, volt_value;
int thermal_gain_corr, voltage_gain_corr; int thermal_gain_corr, voltage_gain_corr;
int desired_scale, desired_gain = 0; int desired_scale, desired_gain = 0;
u32 reg; u32 reg_olpc = 0, reg_cl_gain = 0;
REG_CLR_BIT(ah, AR_PHY_PAPRD_TRAINER_STAT1, REG_CLR_BIT(ah, AR_PHY_PAPRD_TRAINER_STAT1,
AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE); AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE);
@ -271,15 +271,29 @@ static unsigned int ar9003_get_desired_gain(struct ath_hw *ah, int chain,
volt_value = REG_READ_FIELD(ah, AR_PHY_BB_THERM_ADC_4, volt_value = REG_READ_FIELD(ah, AR_PHY_BB_THERM_ADC_4,
AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE); AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE);
if (chain == 0) switch (chain) {
reg = AR_PHY_TPC_11_B0; case 0:
else if (chain == 1) reg_olpc = AR_PHY_TPC_11_B0;
reg = AR_PHY_TPC_11_B1; reg_cl_gain = AR_PHY_CL_TAB_0;
else break;
reg = AR_PHY_TPC_11_B2; case 1:
reg_olpc = AR_PHY_TPC_11_B1;
reg_cl_gain = AR_PHY_CL_TAB_1;
break;
case 2:
reg_olpc = AR_PHY_TPC_11_B2;
reg_cl_gain = AR_PHY_CL_TAB_2;
break;
default:
ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
"Invalid chainmask: %d\n", chain);
break;
}
olpc_gain_delta = REG_READ_FIELD(ah, reg, olpc_gain_delta = REG_READ_FIELD(ah, reg_olpc,
AR_PHY_TPC_11_OLPC_GAIN_DELTA); AR_PHY_TPC_11_OLPC_GAIN_DELTA);
cl_gain_mod = REG_READ_FIELD(ah, reg_cl_gain,
AR_PHY_CL_TAB_CL_GAIN_MOD);
if (olpc_gain_delta >= 128) if (olpc_gain_delta >= 128)
olpc_gain_delta = olpc_gain_delta - 256; olpc_gain_delta = olpc_gain_delta - 256;
@ -289,7 +303,7 @@ static unsigned int ar9003_get_desired_gain(struct ath_hw *ah, int chain,
voltage_gain_corr = (alpha_volt * (volt_value - volt_cal_value) + voltage_gain_corr = (alpha_volt * (volt_value - volt_cal_value) +
(128 / 2)) / 128; (128 / 2)) / 128;
desired_gain = target_power - olpc_gain_delta - thermal_gain_corr - desired_gain = target_power - olpc_gain_delta - thermal_gain_corr -
voltage_gain_corr + desired_scale; voltage_gain_corr + desired_scale + cl_gain_mod;
return desired_gain; return desired_gain;
} }

3
drivers/net/wireless/ath/ath9k/ar9003_phy.h
View File

@ -1121,6 +1121,9 @@
#define AR_PHY_POWERTX_RATE8_POWERTXHT40_5 0x3F00 #define AR_PHY_POWERTX_RATE8_POWERTXHT40_5 0x3F00
#define AR_PHY_POWERTX_RATE8_POWERTXHT40_5_S 8 #define AR_PHY_POWERTX_RATE8_POWERTXHT40_5_S 8
#define AR_PHY_CL_TAB_CL_GAIN_MOD 0x1f
#define AR_PHY_CL_TAB_CL_GAIN_MOD_S 0
void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx); void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
#endif /* AR9003_PHY_H */ #endif /* AR9003_PHY_H */