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Merge branch '1GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue 

Jeff Kirsher says:

====================
1GbE Intel Wired LAN Driver Updates 2015-12-12

This series contains updates to e1000, e1000e and igb.

Joern Engel fixes up the e1000 driver to reduce scheduler latencies by
making the eeprom read/write functions scheduler friendly by using a mutex
lock instead of a spin lock.

Todd adds code for igb to initialize the 88E1543 PHY properly.  Then fixed
igb to use the correct i210 register for EEMNGCTL, since the i210 has two
EEPROM access registers (EEARBC and EEMNGCTL).

Dmitry Vyukov provides a fix for e1000 to resolve a data race found with
KernelThreadSanitizer (KTSAN), where no memory barriers were being used
when buffers get recycled, so the recycled buffers can be corrupted.  So
use smp_store_release() to update tx_ring->next_to_clean and
smp_load_acquire() to read tx_ring->next_to_clean to properly hand off
buffers from e1000_clean_tx_irq() to e1000_xmit_frame().

Jarod Wilson fixes igb so that we do not try to unmap a NULL hw_addr.  Then
cleaned up array_rd32() so that it uses igb_rd32() the same as rd32() and
use io_addr() in more places so that we do not have to call E1000_REMOVED().

Janusz Wolak cleans up the e1000 driver by correcting warnings produced
by checkpatch.pl for the driver.

Jean Sacren provides several patches with general cleanups for e1000 and
e1000e, which include code comment fix-ups and cleanup of local variables
not needed.

Dmitry Fleytman fixes a possible division by zero in the receive interrupt
handler for e1000e when working without adaptive interrupt moderation,
which is typically disabled on jumbo MTUs.

Raanan increases the timeout of the polling bit due to timing changes to
the ME firmware on a platform, so increase the timeout to 300ms.  Added
initial support for i219-LM, which is a LOM that will be available on
systems with the Lewisburg Platform Controller HUB (PCH) chipset.

Jan Beulich fixes a NULL dereference in igb, due to the adapter->vf _data
being NULL while adapter->vfs_allocated_count is non-zero.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2015-12-13 17:06:00 -05:00
parent 91190237df f3ed935de0
commit f68766d884
15 changed files with 379 additions and 195 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/net/ethernet/intel/e1000/e1000.h
View File

@ -213,8 +213,11 @@ struct e1000_rx_ring {
};
#define E1000_DESC_UNUSED(R) \
((((R)->next_to_clean > (R)->next_to_use) \
? 0 : (R)->count) + (R)->next_to_clean - (R)->next_to_use - 1)
({ \
unsigned int clean = smp_load_acquire(&(R)->next_to_clean); \
unsigned int use = READ_ONCE((R)->next_to_use); \
(clean > use ? 0 : (R)->count) + clean - use - 1; \
})
#define E1000_RX_DESC_EXT(R, i) \
(&(((union e1000_rx_desc_extended *)((R).desc))[i]))

132
drivers/net/ethernet/intel/e1000/e1000_hw.c
View File

@ -1,5 +1,5 @@
/*******************************************************************************
*
Intel PRO/1000 Linux driver
Copyright(c) 1999 - 2006 Intel Corporation.
@ -106,7 +106,7 @@ u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = {
120, 120
};
static DEFINE_SPINLOCK(e1000_eeprom_lock);
static DEFINE_MUTEX(e1000_eeprom_lock);
static DEFINE_SPINLOCK(e1000_phy_lock);
/**
@ -624,8 +624,8 @@ s32 e1000_init_hw(struct e1000_hw *hw)
/* Workaround for PCI-X problem when BIOS sets MMRBC
* incorrectly.
*/
if (hw->bus_type == e1000_bus_type_pcix
&& e1000_pcix_get_mmrbc(hw) > 2048)
if (hw->bus_type == e1000_bus_type_pcix &&
e1000_pcix_get_mmrbc(hw) > 2048)
e1000_pcix_set_mmrbc(hw, 2048);
break;
}
@ -684,9 +684,8 @@ static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
&eeprom_data);
if (ret_val) {
if (ret_val)
return ret_val;
}
if (eeprom_data != EEPROM_RESERVED_WORD) {
/* Adjust SERDES output amplitude only. */
@ -1074,8 +1073,8 @@ static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)
if (hw->mac_type <= e1000_82543 ||
hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
hw->mac_type == e1000_82541_rev_2
|| hw->mac_type == e1000_82547_rev_2)
hw->mac_type == e1000_82541_rev_2 ||
hw->mac_type == e1000_82547_rev_2)
hw->phy_reset_disable = false;
return E1000_SUCCESS;
@ -1881,10 +1880,11 @@ static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
if (ret_val)
return ret_val;
if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543)
&& (!hw->autoneg)
&& (hw->forced_speed_duplex == e1000_10_full
|| hw->forced_speed_duplex == e1000_10_half)) {
if ((hw->mac_type == e1000_82544 ||
hw->mac_type == e1000_82543) &&
(!hw->autoneg) &&
(hw->forced_speed_duplex == e1000_10_full ||
hw->forced_speed_duplex == e1000_10_half)) {
ret_val = e1000_polarity_reversal_workaround(hw);
if (ret_val)
return ret_val;
@ -2084,11 +2084,12 @@ static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
* so we had to force link. In this case, we need to force the
* configuration of the MAC to match the "fc" parameter.
*/
if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
|| ((hw->media_type == e1000_media_type_internal_serdes)
&& (hw->autoneg_failed))
|| ((hw->media_type == e1000_media_type_copper)
&& (!hw->autoneg))) {
if (((hw->media_type == e1000_media_type_fiber) &&
(hw->autoneg_failed)) ||
((hw->media_type == e1000_media_type_internal_serdes) &&
(hw->autoneg_failed)) ||
((hw->media_type == e1000_media_type_copper) &&
(!hw->autoneg))) {
ret_val = e1000_force_mac_fc(hw);
if (ret_val) {
e_dbg("Error forcing flow control settings\n");
@ -2193,8 +2194,7 @@ static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
(mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
(mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
{
(mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
hw->fc = E1000_FC_TX_PAUSE;
e_dbg
("Flow Control = TX PAUSE frames only.\n");
@ -2210,8 +2210,7 @@ static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
(mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
!(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
(mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
{
(mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
hw->fc = E1000_FC_RX_PAUSE;
e_dbg
("Flow Control = RX PAUSE frames only.\n");
@ -2460,10 +2459,11 @@ s32 e1000_check_for_link(struct e1000_hw *hw)
* happen due to the execution of this workaround.
*/
if ((hw->mac_type == e1000_82544
|| hw->mac_type == e1000_82543) && (!hw->autoneg)
&& (hw->forced_speed_duplex == e1000_10_full
|| hw->forced_speed_duplex == e1000_10_half)) {
if ((hw->mac_type == e1000_82544 ||
hw->mac_type == e1000_82543) &&
(!hw->autoneg) &&
(hw->forced_speed_duplex == e1000_10_full ||
hw->forced_speed_duplex == e1000_10_half)) {
ew32(IMC, 0xffffffff);
ret_val =
e1000_polarity_reversal_workaround(hw);
@ -2528,8 +2528,10 @@ s32 e1000_check_for_link(struct e1000_hw *hw)
*/
if (hw->tbi_compatibility_en) {
u16 speed, duplex;
ret_val =
e1000_get_speed_and_duplex(hw, &speed, &duplex);
if (ret_val) {
e_dbg
("Error getting link speed and duplex\n");
@ -2628,10 +2630,10 @@ s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex)
e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
if (ret_val)
return ret_val;
if ((*speed == SPEED_100
&& !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
|| (*speed == SPEED_10
&& !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
if ((*speed == SPEED_100 &&
!(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
(*speed == SPEED_10 &&
!(phy_data & NWAY_LPAR_10T_FD_CAPS)))
*duplex = HALF_DUPLEX;
}
}
@ -2664,9 +2666,9 @@ static s32 e1000_wait_autoneg(struct e1000_hw *hw)
ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
if (ret_val)
return ret_val;
if (phy_data & MII_SR_AUTONEG_COMPLETE) {
if (phy_data & MII_SR_AUTONEG_COMPLETE)
return E1000_SUCCESS;
}
msleep(100);
}
return E1000_SUCCESS;
@ -2803,11 +2805,11 @@ static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
return data;
}
/**
* e1000_read_phy_reg - read a phy register
* @hw: Struct containing variables accessed by shared code
* @reg_addr: address of the PHY register to read
* @phy_data: pointer to the value on the PHY register
*
* Reads the value from a PHY register, if the value is on a specific non zero
* page, sets the page first.
@ -2823,14 +2825,13 @@ s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data)
(reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
(u16) reg_addr);
if (ret_val) {
spin_unlock_irqrestore(&e1000_phy_lock, flags);
return ret_val;
}
if (ret_val)
goto out;
}
ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
phy_data);
out:
spin_unlock_irqrestore(&e1000_phy_lock, flags);
return ret_val;
@ -3401,7 +3402,6 @@ static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
}
return E1000_SUCCESS;
@ -3611,11 +3611,11 @@ static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count)
*/
mask = 0x01 << (count - 1);
eecd = er32(EECD);
if (eeprom->type == e1000_eeprom_microwire) {
if (eeprom->type == e1000_eeprom_microwire)
eecd &= ~E1000_EECD_DO;
} else if (eeprom->type == e1000_eeprom_spi) {
else if (eeprom->type == e1000_eeprom_spi)
eecd |= E1000_EECD_DO;
}
do {
/* A "1" is shifted out to the EEPROM by setting bit "DI" to a
* "1", and then raising and then lowering the clock (the SK bit
@ -3882,9 +3882,10 @@ static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw)
s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
{
s32 ret;
spin_lock(&e1000_eeprom_lock);
mutex_lock(&e1000_eeprom_lock);
ret = e1000_do_read_eeprom(hw, offset, words, data);
spin_unlock(&e1000_eeprom_lock);
mutex_unlock(&e1000_eeprom_lock);
return ret;
}
@ -3903,8 +3904,9 @@ static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
/* A check for invalid values: offset too large, too many words, and
* not enough words.
*/
if ((offset >= eeprom->word_size)
|| (words > eeprom->word_size - offset) || (words == 0)) {
if ((offset >= eeprom->word_size) ||
(words > eeprom->word_size - offset) ||
(words == 0)) {
e_dbg("\"words\" parameter out of bounds. Words = %d,"
"size = %d\n", offset, eeprom->word_size);
return -E1000_ERR_EEPROM;
@ -3968,6 +3970,7 @@ static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
*/
data[i] = e1000_shift_in_ee_bits(hw, 16);
e1000_standby_eeprom(hw);
cond_resched();
}
}
@ -4052,9 +4055,10 @@ s32 e1000_update_eeprom_checksum(struct e1000_hw *hw)
s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
{
s32 ret;
spin_lock(&e1000_eeprom_lock);
mutex_lock(&e1000_eeprom_lock);
ret = e1000_do_write_eeprom(hw, offset, words, data);
spin_unlock(&e1000_eeprom_lock);
mutex_unlock(&e1000_eeprom_lock);
return ret;
}
@ -4073,8 +4077,9 @@ static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
/* A check for invalid values: offset too large, too many words, and
* not enough words.
*/
if ((offset >= eeprom->word_size)
|| (words > eeprom->word_size - offset) || (words == 0)) {
if ((offset >= eeprom->word_size) ||
(words > eeprom->word_size - offset) ||
(words == 0)) {
e_dbg("\"words\" parameter out of bounds\n");
return -E1000_ERR_EEPROM;
}
@ -4116,6 +4121,7 @@ static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words,
return -E1000_ERR_EEPROM;
e1000_standby_eeprom(hw);
cond_resched();
/* Send the WRITE ENABLE command (8 bit opcode ) */
e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
@ -4142,6 +4148,7 @@ static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words,
*/
while (widx < words) {
u16 word_out = data[widx];
word_out = (word_out >> 8) | (word_out << 8);
e1000_shift_out_ee_bits(hw, word_out, 16);
widx++;
@ -4224,6 +4231,7 @@ static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
/* Recover from write */
e1000_standby_eeprom(hw);
cond_resched();
words_written++;
}
@ -4816,8 +4824,8 @@ void e1000_update_adaptive(struct e1000_hw *hw)
}
}
} else {
if (hw->in_ifs_mode
&& (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
if (hw->in_ifs_mode &&
(hw->tx_packet_delta <= MIN_NUM_XMITS)) {
hw->current_ifs_val = 0;
hw->in_ifs_mode = false;
ew32(AIT, 0);
@ -4922,7 +4930,6 @@ static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
/* Use old method for Phy older than IGP */
if (hw->phy_type == e1000_phy_m88) {
ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
&phy_data);
if (ret_val)
@ -4966,7 +4973,6 @@ static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
};
/* Read the AGC registers for all channels */
for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
ret_val =
e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
if (ret_val)
@ -4976,8 +4982,8 @@ static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
/* Value bound check. */
if ((cur_agc_value >=
IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1)
|| (cur_agc_value == 0))
IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
(cur_agc_value == 0))
return -E1000_ERR_PHY;
agc_value += cur_agc_value;
@ -5054,7 +5060,6 @@ static s32 e1000_check_polarity(struct e1000_hw *hw,
*/
if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
IGP01E1000_PSSR_SPEED_1000MBPS) {
/* Read the GIG initialization PCS register (0x00B4) */
ret_val =
e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
@ -5346,9 +5351,8 @@ static s32 e1000_set_phy_mode(struct e1000_hw *hw)
ret_val =
e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1,
&eeprom_data);
if (ret_val) {
if (ret_val)
return ret_val;
}
if ((eeprom_data != EEPROM_RESERVED_WORD) &&
(eeprom_data & EEPROM_PHY_CLASS_A)) {
@ -5395,8 +5399,8 @@ static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
* from the lowest speeds starting from 10Mbps. The capability is used
* for Dx transitions and states
*/
if (hw->mac_type == e1000_82541_rev_2
|| hw->mac_type == e1000_82547_rev_2) {
if (hw->mac_type == e1000_82541_rev_2 ||
hw->mac_type == e1000_82547_rev_2) {
ret_val =
e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
if (ret_val)
@ -5446,11 +5450,9 @@ static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
if (ret_val)
return ret_val;
}
} else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
|| (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL)
|| (hw->autoneg_advertised ==
AUTONEG_ADVERTISE_10_100_ALL)) {
} else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
(hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
(hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
if (hw->mac_type == e1000_82541_rev_2 ||
hw->mac_type == e1000_82547_rev_2) {
phy_data |= IGP01E1000_GMII_FLEX_SPD;
@ -5474,7 +5476,6 @@ static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
phy_data);
if (ret_val)
return ret_val;
}
return E1000_SUCCESS;
}
@ -5542,7 +5543,6 @@ static s32 e1000_set_vco_speed(struct e1000_hw *hw)
return E1000_SUCCESS;
}
/**
* e1000_enable_mng_pass_thru - check for bmc pass through
* @hw: Struct containing variables accessed by shared code

55
drivers/net/ethernet/intel/e1000/e1000_main.c
View File

@ -943,8 +943,8 @@ static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
struct e1000_adapter *adapter;
struct e1000_hw *hw;
static int cards_found = 0;
static int global_quad_port_a = 0; /* global ksp3 port a indication */
static int cards_found;
static int global_quad_port_a; /* global ksp3 port a indication */
int i, err, pci_using_dac;
u16 eeprom_data = 0;
u16 tmp = 0;
@ -1199,13 +1199,13 @@ static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
for (i = 0; i < 32; i++) {
hw->phy_addr = i;
e1000_read_phy_reg(hw, PHY_ID2, &tmp);
if (tmp == 0 || tmp == 0xFF) {
if (i == 31)
goto err_eeprom;
continue;
} else
if (tmp != 0 && tmp != 0xFF)
break;
}
if (i >= 32)
goto err_eeprom;
}
/* reset the hardware with the new settings */
@ -1263,7 +1263,7 @@ err_pci_reg:
* @pdev: PCI device information struct
*
* e1000_remove is called by the PCI subsystem to alert the driver
* that it should release a PCI device. The could be caused by a
* that it should release a PCI device. That could be caused by a
* Hot-Plug event, or because the driver is going to be removed from
* memory.
**/
@ -2761,7 +2761,9 @@ static int e1000_tso(struct e1000_adapter *adapter,
buffer_info->time_stamp = jiffies;
buffer_info->next_to_watch = i;
if (++i == tx_ring->count) i = 0;
if (++i == tx_ring->count)
i = 0;
tx_ring->next_to_use = i;
return true;
@ -2816,7 +2818,9 @@ static bool e1000_tx_csum(struct e1000_adapter *adapter,
buffer_info->time_stamp = jiffies;
buffer_info->next_to_watch = i;
if (unlikely(++i == tx_ring->count)) i = 0;
if (unlikely(++i == tx_ring->count))
i = 0;
tx_ring->next_to_use = i;
return true;
@ -3013,7 +3017,8 @@ static void e1000_tx_queue(struct e1000_adapter *adapter,
tx_desc->lower.data =
cpu_to_le32(txd_lower | buffer_info->length);
tx_desc->upper.data = cpu_to_le32(txd_upper);
if (unlikely(++i == tx_ring->count)) i = 0;
if (unlikely(++i == tx_ring->count))
i = 0;
}
tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
@ -3869,14 +3874,18 @@ static bool e1000_clean_tx_irq(struct e1000_adapter *adapter,
e1000_unmap_and_free_tx_resource(adapter, buffer_info);
tx_desc->upper.data = 0;
if (unlikely(++i == tx_ring->count)) i = 0;
if (unlikely(++i == tx_ring->count))
i = 0;
}
eop = tx_ring->buffer_info[i].next_to_watch;
eop_desc = E1000_TX_DESC(*tx_ring, eop);
}
tx_ring->next_to_clean = i;
/* Synchronize with E1000_DESC_UNUSED called from e1000_xmit_frame,
* which will reuse the cleaned buffers.
*/
smp_store_release(&tx_ring->next_to_clean, i);
netdev_completed_queue(netdev, pkts_compl, bytes_compl);
@ -3954,9 +3963,11 @@ static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
skb_checksum_none_assert(skb);
/* 82543 or newer only */
if (unlikely(hw->mac_type < e1000_82543)) return;
if (unlikely(hw->mac_type < e1000_82543))
return;
/* Ignore Checksum bit is set */
if (unlikely(status & E1000_RXD_STAT_IXSM)) return;
if (unlikely(status & E1000_RXD_STAT_IXSM))
return;
/* TCP/UDP checksum error bit is set */
if (unlikely(errors & E1000_RXD_ERR_TCPE)) {
/* let the stack verify checksum errors */
@ -4153,7 +4164,9 @@ static bool e1000_clean_jumbo_rx_irq(struct e1000_adapter *adapter,
status = rx_desc->status;
if (++i == rx_ring->count) i = 0;
if (++i == rx_ring->count)
i = 0;
next_rxd = E1000_RX_DESC(*rx_ring, i);
prefetch(next_rxd);
@ -4395,7 +4408,9 @@ static bool e1000_clean_rx_irq(struct e1000_adapter *adapter,
buffer_info->rxbuf.data = NULL;
}
if (++i == rx_ring->count) i = 0;
if (++i == rx_ring->count)
i = 0;
next_rxd = E1000_RX_DESC(*rx_ring, i);
prefetch(next_rxd);
@ -4683,9 +4698,11 @@ static void e1000_smartspeed(struct e1000_adapter *adapter)
* we assume back-to-back
*/
e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status);
if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
if (!(phy_status & SR_1000T_MS_CONFIG_FAULT))
return;
e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status);
if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
if (!(phy_status & SR_1000T_MS_CONFIG_FAULT))
return;
e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl);
if (phy_ctrl & CR_1000T_MS_ENABLE) {
phy_ctrl &= ~CR_1000T_MS_ENABLE;

1
drivers/net/ethernet/intel/e1000e/hw.h
View File

@ -91,6 +91,7 @@ struct e1000_hw;
#define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* SPT PCH */
#define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* SPT-H PCH */
#define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* SPT-H PCH */
#define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LBG PCH */
#define E1000_REVISION_4 4

45
drivers/net/ethernet/intel/e1000e/ich8lan.c
View File

@ -1984,7 +1984,7 @@ static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
int i = 0;
while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) &&
(i++ < 10))
(i++ < 30))
usleep_range(10000, 20000);
return blocked ? E1000_BLK_PHY_RESET : 0;
}
@ -3093,24 +3093,45 @@ static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
struct e1000_nvm_info *nvm = &hw->nvm;
u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
u32 nvm_dword = 0;
u8 sig_byte = 0;
s32 ret_val;
switch (hw->mac.type) {
/* In SPT, read from the CTRL_EXT reg instead of
* accessing the sector valid bits from the nvm
*/
case e1000_pch_spt:
*bank = er32(CTRL_EXT)
& E1000_CTRL_EXT_NVMVS;
if ((*bank == 0) || (*bank == 1)) {
e_dbg("ERROR: No valid NVM bank present\n");
return -E1000_ERR_NVM;
} else {
*bank = *bank - 2;
bank1_offset = nvm->flash_bank_size;
act_offset = E1000_ICH_NVM_SIG_WORD;
/* set bank to 0 in case flash read fails */
*bank = 0;
/* Check bank 0 */
ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
&nvm_dword);
if (ret_val)
return ret_val;
sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
E1000_ICH_NVM_SIG_VALUE) {
*bank = 0;
return 0;
}
break;
/* Check bank 1 */
ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
bank1_offset,
&nvm_dword);
if (ret_val)
return ret_val;
sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
E1000_ICH_NVM_SIG_VALUE) {
*bank = 1;
return 0;
}
e_dbg("ERROR: No valid NVM bank present\n");
return -E1000_ERR_NVM;
case e1000_ich8lan:
case e1000_ich9lan:
eecd = er32(EECD);

12
drivers/net/ethernet/intel/e1000e/netdev.c
View File

@ -1959,8 +1959,10 @@ static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data)
* previous interrupt.
*/
if (rx_ring->set_itr) {
writel(1000000000 / (rx_ring->itr_val * 256),
rx_ring->itr_register);
u32 itr = rx_ring->itr_val ?
1000000000 / (rx_ring->itr_val * 256) : 0;
writel(itr, rx_ring->itr_register);
rx_ring->set_itr = 0;
}
@ -7465,6 +7467,7 @@ static const struct pci_device_id e1000_pci_tbl[] = {
{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt },
{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt },
{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt },
{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LBG_I219_LM3), board_pch_spt },
{ 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
};
@ -7504,14 +7507,11 @@ static struct pci_driver e1000_driver = {
**/
static int __init e1000_init_module(void)
{
int ret;
pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
e1000e_driver_version);
pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n");
ret = pci_register_driver(&e1000_driver);
return ret;
return pci_register_driver(&e1000_driver);
}
module_init(e1000_init_module);

8
drivers/net/ethernet/intel/igb/e1000_82575.c
View File

@ -272,6 +272,11 @@ static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
if (ret_val)
goto out;
}
if (phy->id == M88E1543_E_PHY_ID) {
ret_val = igb_initialize_M88E1543_phy(hw);
if (ret_val)
goto out;
}
break;
case IGP03E1000_E_PHY_ID:
phy->type = e1000_phy_igp_3;
@ -294,6 +299,7 @@ static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
case I210_I_PHY_ID:
phy->type = e1000_phy_i210;
phy->ops.check_polarity = igb_check_polarity_m88;
phy->ops.get_cfg_done = igb_get_cfg_done_i210;
phy->ops.get_phy_info = igb_get_phy_info_m88;
phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
@ -925,6 +931,8 @@ static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
if (phy->id == M88E1512_E_PHY_ID)
ret_val = igb_initialize_M88E1512_phy(hw);
if (phy->id == M88E1543_E_PHY_ID)
ret_val = igb_initialize_M88E1543_phy(hw);
out:
return ret_val;
}

1
drivers/net/ethernet/intel/igb/e1000_defines.h
View File

@ -990,6 +990,7 @@
#define E1000_M88E1543_PAGE_ADDR 0x16 /* Page Offset Register */
#define E1000_M88E1543_EEE_CTRL_1 0x0
#define E1000_M88E1543_EEE_CTRL_1_MS 0x0001 /* EEE Master/Slave */
#define E1000_M88E1543_FIBER_CTRL 0x0
#define E1000_EEE_ADV_DEV_I354 7
#define E1000_EEE_ADV_ADDR_I354 60
#define E1000_EEE_ADV_100_SUPPORTED (1 << 1) /* 100BaseTx EEE Supported */

27
drivers/net/ethernet/intel/igb/e1000_i210.c
View File

@ -900,3 +900,30 @@ s32 igb_pll_workaround_i210(struct e1000_hw *hw)
wr32(E1000_MDICNFG, mdicnfg);
return ret_val;
}
/**
* igb_get_cfg_done_i210 - Read config done bit
* @hw: pointer to the HW structure
*
* Read the management control register for the config done bit for
* completion status. NOTE: silicon which is EEPROM-less will fail trying
* to read the config done bit, so an error is *ONLY* logged and returns
* 0. If we were to return with error, EEPROM-less silicon
* would not be able to be reset or change link.
**/
s32 igb_get_cfg_done_i210(struct e1000_hw *hw)
{
s32 timeout = PHY_CFG_TIMEOUT;
u32 mask = E1000_NVM_CFG_DONE_PORT_0;
while (timeout) {
if (rd32(E1000_EEMNGCTL_I210) & mask)
break;
usleep_range(1000, 2000);
timeout--;
}
if (!timeout)
hw_dbg("MNG configuration cycle has not completed.\n");
return 0;
}

1
drivers/net/ethernet/intel/igb/e1000_i210.h
View File

@ -34,6 +34,7 @@ s32 igb_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 data);
s32 igb_init_nvm_params_i210(struct e1000_hw *hw);
bool igb_get_flash_presence_i210(struct e1000_hw *hw);
s32 igb_pll_workaround_i210(struct e1000_hw *hw);
s32 igb_get_cfg_done_i210(struct e1000_hw *hw);
#define E1000_STM_OPCODE 0xDB00
#define E1000_EEPROM_FLASH_SIZE_WORD 0x11

94
drivers/net/ethernet/intel/igb/e1000_phy.c
View File

@ -2277,6 +2277,100 @@ out:
return ret_val;
}
/**
* igb_initialize_M88E1543_phy - Initialize M88E1512 PHY
* @hw: pointer to the HW structure
*
* Initialize Marvell 1543 to work correctly with Avoton.
**/
s32 igb_initialize_M88E1543_phy(struct e1000_hw *hw)
{
struct e1000_phy_info *phy = &hw->phy;
s32 ret_val = 0;
/* Switch to PHY page 0xFF. */
ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
if (ret_val)
goto out;
ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
if (ret_val)
goto out;
ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
if (ret_val)
goto out;
ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
if (ret_val)
goto out;
ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
if (ret_val)
goto out;
ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
if (ret_val)
goto out;
ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
if (ret_val)
goto out;
ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C);
if (ret_val)
goto out;
ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
if (ret_val)
goto out;
/* Switch to PHY page 0xFB. */
ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
if (ret_val)
goto out;
ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x0C0D);
if (ret_val)
goto out;
/* Switch to PHY page 0x12. */
ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
if (ret_val)
goto out;
/* Change mode to SGMII-to-Copper */
ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
if (ret_val)
goto out;
/* Switch to PHY page 1. */
ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1);
if (ret_val)
goto out;
/* Change mode to 1000BASE-X/SGMII and autoneg enable */
ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140);
if (ret_val)
goto out;
/* Return the PHY to page 0. */
ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
if (ret_val)
goto out;
ret_val = igb_phy_sw_reset(hw);
if (ret_val) {
hw_dbg("Error committing the PHY changes\n");
return ret_val;
}
/* msec_delay(1000); */
usleep_range(1000, 2000);
out:
return ret_val;
}
/**
* igb_power_up_phy_copper - Restore copper link in case of PHY power down
* @hw: pointer to the HW structure

1
drivers/net/ethernet/intel/igb/e1000_phy.h
View File

@ -62,6 +62,7 @@ void igb_power_up_phy_copper(struct e1000_hw *hw);
void igb_power_down_phy_copper(struct e1000_hw *hw);
s32 igb_phy_init_script_igp3(struct e1000_hw *hw);
s32 igb_initialize_M88E1512_phy(struct e1000_hw *hw);
s32 igb_initialize_M88E1543_phy(struct e1000_hw *hw);
s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);

4
drivers/net/ethernet/intel/igb/e1000_regs.h
View File

@ -66,6 +66,7 @@
#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
#define E1000_PBS 0x01008 /* Packet Buffer Size */
#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
#define E1000_EEMNGCTL_I210 0x12030 /* MNG EEprom Control */
#define E1000_EEARBC_I210 0x12024 /* EEPROM Auto Read Bus Control */
#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
#define E1000_I2CCMD 0x01028 /* SFPI2C Command Register - RW */
@ -385,8 +386,7 @@ do { \
#define array_wr32(reg, offset, value) \
wr32((reg) + ((offset) << 2), (value))
#define array_rd32(reg, offset) \
(readl(hw->hw_addr + reg + ((offset) << 2)))
#define array_rd32(reg, offset) (igb_rd32(hw, reg + ((offset) << 2)))
/* DMA Coalescing registers */
#define E1000_PCIEMISC 0x05BB8 /* PCIE misc config register */

2
drivers/net/ethernet/intel/igb/igb.h
View File

@ -389,6 +389,8 @@ struct igb_adapter {
u16 link_speed;
u16 link_duplex;
u8 __iomem *io_addr; /* Mainly for iounmap use */
struct work_struct reset_task;
struct work_struct watchdog_task;
bool fc_autoneg;

22
drivers/net/ethernet/intel/igb/igb_main.c
View File

@ -946,7 +946,6 @@ static void igb_configure_msix(struct igb_adapter *adapter)
static int igb_request_msix(struct igb_adapter *adapter)
{
struct net_device *netdev = adapter->netdev;
struct e1000_hw *hw = &adapter->hw;
int i, err = 0, vector = 0, free_vector = 0;
err = request_irq(adapter->msix_entries[vector].vector,
@ -959,7 +958,7 @@ static int igb_request_msix(struct igb_adapter *adapter)
vector++;
q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
q_vector->itr_register = adapter->io_addr + E1000_EITR(vector);
if (q_vector->rx.ring && q_vector->tx.ring)
sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
@ -1230,7 +1229,7 @@ static int igb_alloc_q_vector(struct igb_adapter *adapter,
q_vector->tx.work_limit = adapter->tx_work_limit;
/* initialize ITR configuration */
q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
q_vector->itr_register = adapter->io_addr + E1000_EITR(0);
q_vector->itr_val = IGB_START_ITR;
/* initialize pointer to rings */
@ -2294,9 +2293,11 @@ static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
err = -EIO;
hw->hw_addr = pci_iomap(pdev, 0, 0);
if (!hw->hw_addr)
adapter->io_addr = pci_iomap(pdev, 0, 0);
if (!adapter->io_addr)
goto err_ioremap;
/* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */
hw->hw_addr = adapter->io_addr;
netdev->netdev_ops = &igb_netdev_ops;
igb_set_ethtool_ops(netdev);
@ -2656,7 +2657,7 @@ err_sw_init:
#ifdef CONFIG_PCI_IOV
igb_disable_sriov(pdev);
#endif
pci_iounmap(pdev, hw->hw_addr);
pci_iounmap(pdev, adapter->io_addr);
err_ioremap:
free_netdev(netdev);
err_alloc_etherdev:
@ -2823,7 +2824,7 @@ static void igb_remove(struct pci_dev *pdev)
igb_clear_interrupt_scheme(adapter);
pci_iounmap(pdev, hw->hw_addr);
pci_iounmap(pdev, adapter->io_addr);
if (hw->flash_address)
iounmap(hw->flash_address);
pci_release_selected_regions(pdev,
@ -2856,6 +2857,13 @@ static void igb_probe_vfs(struct igb_adapter *adapter)
if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
return;
/* Of the below we really only want the effect of getting
* IGB_FLAG_HAS_MSIX set (if available), without which
* igb_enable_sriov() has no effect.
*/
igb_set_interrupt_capability(adapter, true);
igb_reset_interrupt_capability(adapter);
pci_sriov_set_totalvfs(pdev, 7);
igb_enable_sriov(pdev, max_vfs);