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ARM: dts: lan966x: Fix the interrupt number for internal PHYs 

According to the datasheet the interrupts for internal PHYs are
80 and 81.

Fixes: 6ad69e07de ("ARM: dts: lan966x: add MIIM nodes")
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220912192629.461452-1-horatiu.vultur@microchip.com
This commit is contained in:
Horatiu Vultur 2022-09-12 21:26:29 +02:00 committed by Claudiu Beznea
parent 3d074b750d
commit f5fc22cbbd
1 changed files with 2 additions and 2 deletions
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4
arch/arm/boot/dts/lan966x.dtsi
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@ -541,13 +541,13 @@
phy0: ethernet-phy@1 { phy0: ethernet-phy@1 {
reg = <1>; reg = <1>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled"; status = "disabled";
}; };
phy1: ethernet-phy@2 { phy1: ethernet-phy@2 {
reg = <2>; reg = <2>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled"; status = "disabled";
}; };
}; };