drm/etnaviv: use a 32 bit mask as coherent DMA mask
The STLB and the first command buffer (which is used to set up the TLBs) has a 32 bit size restriction in hardware. There seems to be no way to specify addresses larger than 32 bit. Keep it simple and restict the addresses to the lower 4 GiB range for all coherent DMA memory allocations. Please note, that platform_device_alloc() will initialize dev->dma_mask to point to pdev->platform_dma_mask, thus dma_set_mask() will work as expected. While at it, move the dma_mask setup code to the of_dma_configure() to keep all the DMA setup code next to each other. Suggested-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
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@ -613,6 +613,24 @@ static int etnaviv_pdev_probe(struct platform_device *pdev)
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component_match_add(dev, &match, compare_str, names[i]);
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}
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/*
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* PTA and MTLB can have 40 bit base addresses, but
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* unfortunately, an entry in the MTLB can only point to a
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* 32 bit base address of a STLB. Moreover, to initialize the
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* MMU we need a command buffer with a 32 bit address because
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* without an MMU there is only an indentity mapping between
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* the internal 32 bit addresses and the bus addresses.
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*
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* To make things easy, we set the dma_coherent_mask to 32
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* bit to make sure we are allocating the command buffers and
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* TLBs in the lower 4 GiB address space.
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*/
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if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(40)) ||
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dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) {
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dev_dbg(&pdev->dev, "No suitable DMA available\n");
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return -ENODEV;
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}
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/*
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* Apply the same DMA configuration to the virtual etnaviv
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* device as the GPU we found. This assumes that all Vivante
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@ -671,8 +689,6 @@ static int __init etnaviv_init(void)
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of_node_put(np);
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goto unregister_platform_driver;
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}
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pdev->dev.coherent_dma_mask = DMA_BIT_MASK(40);
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pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
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ret = platform_device_add(pdev);
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if (ret) {
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