blackfin updates for Linux 3.10
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) iQIcBAABAgAGBQJRi4ZDAAoJEJommM3PjknHTDYP/j/xtxd9IEsqVS6lGoNhvOL2 L3q+BbvijtsYVR08iQhroeCGCm8S7V6vdWNlFOjZESP1mDO9JAyDOloaWe/asPB5 HJVrfD+Z4taRTaeRq1br2T/knYMezDEKTxxilZcGYnLkx4a+uOT7kGywgd82jR2J VlZcpa4JRSiWa1jB3kQNz1+6LHPNogFeufUY4VsHnOEuiD667c3wd865OTicsxil eomr9VHOhA4nj5ac9Qlf+HZAQGkp71ugAx9YBzfLxt0lHpYTU2aqGwzkVD3PShH4 5zYQA7nYIGskLWyGNopomdXY9SmOwe0sIU5r0BcDQEaiizZFX0CnO00i2zdcH104 +Q2iCaU+NNTb5QDnUUnAuj7vFcwiSMBHFADvgloyuwafLPtF6X8Xi4qB/NOPneM4 q03i7kT0K723XVtqjpaaf904TuAmhoZREOESMkzPrEM+Dm7KReO3VBUhIs/BjcFO DGIBRhIIFNzSfGjVBP0idWRTqQoJ0Akf/dLnDbTM+IvBaYcL+ck6gKYZ0UvCM3IO 16VEtUuIxNeJsLD5xwGKTOJ6cyYqmYrZ8ZIG5Fc/b3Y1EFcexSY1FwtplG9yHx2Q ulRxLpmY25KWVa5Op9Hl9MU131FWaZ5qJJXvW6nU8C4bvGjP97MoS9ObsuD20fwI TiUpia3+Dom2O4dtvx7N =0WkM -----END PGP SIGNATURE----- Merge tag 'for-linus' of git://github.com/realmz/blackfin-linux Pull blackfin updates from Steven Miao. * tag 'for-linus' of git://github.com/realmz/blackfin-linux: bfin cache: dcplb map: add 16M dcplb map for BF60x blackfin: smp: fix smp build after drop asm/system.h blackfin: fix bootup core clock and system clock display Platform Nand: Set the GPIO for NAND read as input blackfin: rename vmImage to uImage after we move to buildroot blackfin: twi: Remove bogus #endif bf609: rsi: Add bf609 rsi MMR macro and board platform data. blackfin: dmc: Improve DDR2 write through in DMC effict controller.
This commit is contained in:
Linus Torvalds
commit
f5b8fcb48b
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@ -141,11 +141,11 @@ archclean:
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INSTALL_PATH ?= /tftpboot
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boot := arch/$(ARCH)/boot
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BOOT_TARGETS = vmImage vmImage.bin vmImage.bz2 vmImage.gz vmImage.lzma vmImage.lzo vmImage.xip
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BOOT_TARGETS = uImage uImage.bin uImage.bz2 uImage.gz uImage.lzma uImage.lzo uImage.xip
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PHONY += $(BOOT_TARGETS) install
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KBUILD_IMAGE := $(boot)/vmImage
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KBUILD_IMAGE := $(boot)/uImage
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all: vmImage
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all: uImage
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$(BOOT_TARGETS): vmlinux
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$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
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@ -6,7 +6,7 @@
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# for more details.
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#
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targets := vmImage vmImage.bin vmImage.bz2 vmImage.gz vmImage.lzma vmImage.lzo vmImage.xip
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targets := uImage uImage.bin uImage.bz2 uImage.gz uImage.lzma uImage.lzo uImage.xip
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extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma vmlinux.bin.lzo vmlinux.bin.xip
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ifeq ($(CONFIG_RAMKERNEL),y)
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@ -39,22 +39,22 @@ quiet_cmd_mk_bin_xip = BIN $@
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$(obj)/vmlinux.bin.xip: $(obj)/vmlinux.bin FORCE
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$(call if_changed,mk_bin_xip)
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$(obj)/vmImage.bin: $(obj)/vmlinux.bin
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$(obj)/uImage.bin: $(obj)/vmlinux.bin
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$(call if_changed,uimage,none)
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$(obj)/vmImage.bz2: $(obj)/vmlinux.bin.bz2
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$(obj)/uImage.bz2: $(obj)/vmlinux.bin.bz2
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$(call if_changed,uimage,bzip2)
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$(obj)/vmImage.gz: $(obj)/vmlinux.bin.gz
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$(obj)/uImage.gz: $(obj)/vmlinux.bin.gz
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$(call if_changed,uimage,gzip)
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$(obj)/vmImage.lzma: $(obj)/vmlinux.bin.lzma
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$(obj)/uImage.lzma: $(obj)/vmlinux.bin.lzma
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$(call if_changed,uimage,lzma)
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$(obj)/vmImage.lzo: $(obj)/vmlinux.bin.lzo
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$(obj)/uImage.lzo: $(obj)/vmlinux.bin.lzo
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$(call if_changed,uimage,lzo)
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$(obj)/vmImage.xip: $(obj)/vmlinux.bin.xip
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$(obj)/uImage.xip: $(obj)/vmlinux.bin.xip
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$(call if_changed,uimage,none)
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suffix-y := bin
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@ -64,7 +64,7 @@ suffix-$(CONFIG_KERNEL_LZMA) := lzma
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suffix-$(CONFIG_KERNEL_LZO) := lzo
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suffix-$(CONFIG_ROMKERNEL) := xip
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$(obj)/vmImage: $(obj)/vmImage.$(suffix-y)
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$(obj)/uImage: $(obj)/uImage.$(suffix-y)
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@ln -sf $(notdir $<) $@
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install:
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@ -11,7 +11,9 @@
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#ifdef CONFIG_SMP
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#include <asm/barrier.h>
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#include <linux/linkage.h>
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#include <linux/types.h>
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asmlinkage int __raw_uncached_fetch_asm(const volatile int *ptr);
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asmlinkage int __raw_atomic_update_asm(volatile int *ptr, int value);
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@ -24,18 +24,27 @@ struct bfin_sd_host {
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#define CMD_INT_E (1 << 8) /* Command Interrupt */
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#define CMD_PEND_E (1 << 9) /* Command Pending */
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#define CMD_E (1 << 10) /* Command Enable */
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#ifdef RSI_BLKSZ
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#define CMD_CRC_CHECK_D (1 << 11) /* CRC Check is disabled */
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#define CMD_DATA0_BUSY (1 << 12) /* Check for Busy State on the DATA0 pin */
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#endif
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/* SDH_PWR_CTL bitmasks */
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#ifndef RSI_BLKSZ
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#define PWR_ON 0x3 /* Power On */
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#define SD_CMD_OD (1 << 6) /* Open Drain Output */
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#define ROD_CTL (1 << 7) /* Rod Control */
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#endif
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/* SDH_CLK_CTL bitmasks */
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#define CLKDIV 0xff /* MC_CLK Divisor */
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#define CLK_E (1 << 8) /* MC_CLK Bus Clock Enable */
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#define PWR_SV_E (1 << 9) /* Power Save Enable */
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#define CLKDIV_BYPASS (1 << 10) /* Bypass Divisor */
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#define WIDE_BUS (1 << 11) /* Wide Bus Mode Enable */
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#define BUS_MODE_MASK 0x1800 /* Bus Mode Mask */
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#define STD_BUS_1 0x000 /* Standard Bus 1 bit mode */
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#define WIDE_BUS_4 0x800 /* Wide Bus 4 bit mode */
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#define BYTE_BUS_8 0x1000 /* Byte Bus 8 bit mode */
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/* SDH_RESP_CMD bitmasks */
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#define RESP_CMD 0x3f /* Response Command */
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@ -45,7 +54,13 @@ struct bfin_sd_host {
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#define DTX_DIR (1 << 1) /* Data Transfer Direction */
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#define DTX_MODE (1 << 2) /* Data Transfer Mode */
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#define DTX_DMA_E (1 << 3) /* Data Transfer DMA Enable */
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#ifndef RSI_BLKSZ
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#define DTX_BLK_LGTH (0xf << 4) /* Data Transfer Block Length */
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#else
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/* Bit masks for SDH_BLK_SIZE */
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#define DTX_BLK_LGTH 0x1fff /* Data Transfer Block Length */
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#endif
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/* SDH_STATUS bitmasks */
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#define CMD_CRC_FAIL (1 << 0) /* CMD CRC Fail */
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@ -114,10 +129,14 @@ struct bfin_sd_host {
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/* SDH_E_STATUS bitmasks */
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#define SDIO_INT_DET (1 << 1) /* SDIO Int Detected */
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#define SD_CARD_DET (1 << 4) /* SD Card Detect */
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#define SD_CARD_BUSYMODE (1 << 31) /* Card is in Busy mode */
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#define SD_CARD_SLPMODE (1 << 30) /* Card in Sleep Mode */
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#define SD_CARD_READY (1 << 17) /* Card Ready */
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/* SDH_E_MASK bitmasks */
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#define SDIO_MSK (1 << 1) /* Mask SDIO Int Detected */
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#define SCD_MSK (1 << 6) /* Mask Card Detect */
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#define SCD_MSK (1 << 4) /* Mask Card Detect */
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#define CARD_READY_MSK (1 << 16) /* Mask Card Ready */
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/* SDH_CFG bitmasks */
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#define CLKS_EN (1 << 0) /* Clocks Enable */
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@ -126,7 +145,15 @@ struct bfin_sd_host {
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#define SD_RST (1 << 4) /* SDMMC Reset */
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#define PUP_SDDAT (1 << 5) /* Pull-up SD_DAT */
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#define PUP_SDDAT3 (1 << 6) /* Pull-up SD_DAT3 */
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#ifndef RSI_BLKSZ
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#define PD_SDDAT3 (1 << 7) /* Pull-down SD_DAT3 */
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#else
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#define PWR_ON 0x600 /* Power On */
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#define SD_CMD_OD (1 << 11) /* Open Drain Output */
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#define BOOT_EN (1 << 12) /* Boot Enable */
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#define BOOT_MODE (1 << 13) /* Alternate Boot Mode */
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#define BOOT_ACK_EN (1 << 14) /* Boot ACK is expected */
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#endif
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/* SDH_RD_WAIT_EN bitmasks */
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#define RWR (1 << 0) /* Read Wait Request */
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@ -41,6 +41,7 @@
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#include <asm-generic/bitops/non-atomic.h>
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#else
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#include <asm/barrier.h>
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#include <asm/byteorder.h> /* swab32 */
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#include <linux/linkage.h>
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@ -622,10 +622,12 @@ do { \
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#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
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#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
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#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */
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#ifdef CONFIG_BF60x
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#define PAGE_SIZE_16KB 0x00040000 /* 16 KB page size */
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#define PAGE_SIZE_64KB 0x00050000 /* 64 KB page size */
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#define PAGE_SIZE_16MB 0x00060000 /* 16 MB page size */
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#define PAGE_SIZE_64MB 0x00070000 /* 64 MB page size */
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#endif
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#define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not
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* mapped to L1
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*/
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@ -335,6 +335,7 @@
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struct ddr_config {
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u32 ddr_clk;
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u32 dmc_ddrctl;
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u32 dmc_effctl;
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u32 dmc_ddrcfg;
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u32 dmc_ddrtr0;
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u32 dmc_ddrtr1;
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@ -348,6 +349,7 @@ static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1")))
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[0] = {
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.ddr_clk = 125,
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.dmc_ddrctl = 0x00000904,
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.dmc_effctl = 0x004400C0,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20705212,
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.dmc_ddrtr1 = 0x201003CF,
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@ -358,6 +360,7 @@ static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1")))
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[1] = {
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.ddr_clk = 133,
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.dmc_ddrctl = 0x00000904,
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.dmc_effctl = 0x004400C0,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20806313,
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.dmc_ddrtr1 = 0x2013040D,
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@ -368,6 +371,7 @@ static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1")))
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[2] = {
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.ddr_clk = 150,
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.dmc_ddrctl = 0x00000904,
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.dmc_effctl = 0x004400C0,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20A07323,
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.dmc_ddrtr1 = 0x20160492,
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@ -378,6 +382,7 @@ static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1")))
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[3] = {
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.ddr_clk = 166,
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.dmc_ddrctl = 0x00000904,
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.dmc_effctl = 0x004400C0,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20A07323,
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.dmc_ddrtr1 = 0x2016050E,
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@ -388,6 +393,7 @@ static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1")))
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[4] = {
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.ddr_clk = 200,
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.dmc_ddrctl = 0x00000904,
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.dmc_effctl = 0x004400C0,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20a07323,
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.dmc_ddrtr1 = 0x2016050f,
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@ -398,6 +404,7 @@ static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1")))
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[5] = {
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.ddr_clk = 225,
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.dmc_ddrctl = 0x00000904,
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.dmc_effctl = 0x004400C0,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20E0A424,
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.dmc_ddrtr1 = 0x302006DB,
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@ -408,6 +415,7 @@ static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1")))
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[6] = {
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.ddr_clk = 250,
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.dmc_ddrctl = 0x00000904,
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.dmc_effctl = 0x004400C0,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20E0A424,
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.dmc_ddrtr1 = 0x3020079E,
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@ -469,6 +477,7 @@ static inline void init_dmc(u32 dmc_clk)
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bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2);
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bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr);
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bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1);
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bfin_write_DMC0_EFFCTL(ddr_config_table[i].dmc_effctl);
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bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl);
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break;
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}
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|
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@ -30,6 +30,7 @@ void __init generate_cplb_tables_cpu(unsigned int cpu)
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{
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int i_d, i_i;
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unsigned long addr;
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unsigned long cplb_pageflags, cplb_pagesize;
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struct cplb_entry *d_tbl = dcplb_tbl[cpu];
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struct cplb_entry *i_tbl = icplb_tbl[cpu];
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@ -49,11 +50,20 @@ void __init generate_cplb_tables_cpu(unsigned int cpu)
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/* Cover kernel memory with 4M pages. */
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addr = 0;
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for (; addr < memory_start; addr += 4 * 1024 * 1024) {
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#ifdef PAGE_SIZE_16MB
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cplb_pageflags = PAGE_SIZE_16MB;
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cplb_pagesize = SIZE_16M;
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#else
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cplb_pageflags = PAGE_SIZE_4MB;
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cplb_pagesize = SIZE_4M;
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#endif
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for (; addr < memory_start; addr += cplb_pagesize) {
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d_tbl[i_d].addr = addr;
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d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_4MB;
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d_tbl[i_d++].data = SDRAM_DGENERIC | cplb_pageflags;
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i_tbl[i_i].addr = addr;
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i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_4MB;
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i_tbl[i_i++].data = SDRAM_IGENERIC | cplb_pageflags;
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}
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#ifdef CONFIG_ROMKERNEL
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|
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@ -145,7 +145,7 @@ MGR_ATTR static int dcplb_miss(int cpu)
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unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();
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int status = bfin_read_DCPLB_STATUS();
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int idx;
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unsigned long d_data, base, addr1, eaddr;
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unsigned long d_data, base, addr1, eaddr, cplb_pagesize, cplb_pageflags;
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nr_dcplb_miss[cpu]++;
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if (unlikely(status & FAULT_USERSUPV))
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@ -167,18 +167,37 @@ MGR_ATTR static int dcplb_miss(int cpu)
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if (unlikely(d_data == 0))
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return CPLB_NO_ADDR_MATCH;
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addr1 = addr & ~(SIZE_4M - 1);
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addr &= ~(SIZE_1M - 1);
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d_data |= PAGE_SIZE_1MB;
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if (addr1 >= base && (addr1 + SIZE_4M) <= eaddr) {
|
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|
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/* BF60x support large than 4M CPLB page size */
|
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#ifdef PAGE_SIZE_16MB
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cplb_pageflags = PAGE_SIZE_16MB;
|
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cplb_pagesize = SIZE_16M;
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#else
|
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cplb_pageflags = PAGE_SIZE_4MB;
|
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cplb_pagesize = SIZE_4M;
|
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#endif
|
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|
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find_pagesize:
|
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addr1 = addr & ~(cplb_pagesize - 1);
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if (addr1 >= base && (addr1 + cplb_pagesize) <= eaddr) {
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/*
|
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* This works because
|
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* (PAGE_SIZE_4MB & PAGE_SIZE_1MB) == PAGE_SIZE_1MB.
|
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*/
|
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d_data |= PAGE_SIZE_4MB;
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d_data |= cplb_pageflags;
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addr = addr1;
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goto found_pagesize;
|
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} else {
|
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if (cplb_pagesize > SIZE_4M) {
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cplb_pageflags = PAGE_SIZE_4MB;
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cplb_pagesize = SIZE_4M;
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goto find_pagesize;
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}
|
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}
|
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|
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found_pagesize:
|
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#ifdef CONFIG_BF60x
|
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if ((addr >= ASYNC_BANK0_BASE)
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&& (addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE))
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|
|
|
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|
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@ -17,8 +17,13 @@
|
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#include <asm/cplbinit.h>
|
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#include <asm/blackfin.h>
|
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|
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static char const page_strtbl[][3] = { "1K", "4K", "1M", "4M" };
|
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#define page(flags) (((flags) & 0x30000) >> 16)
|
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static char const page_strtbl[][4] = {
|
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"1K", "4K", "1M", "4M",
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#ifdef CONFIG_BF60x
|
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"16K", "64K", "16M", "64M",
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#endif
|
||||
};
|
||||
#define page(flags) (((flags) & 0x70000) >> 16)
|
||||
#define strpage(flags) page_strtbl[page(flags)]
|
||||
|
||||
struct cplbinfo_data {
|
||||
|
|
|
|||
|
|
@ -1314,7 +1314,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
|
|||
seq_printf(m, "(Compiled for Rev %d)", bfin_compiled_revid());
|
||||
}
|
||||
|
||||
seq_printf(m, "\ncpu MHz\t\t: %lu.%03lu/%lu.%03lu\n",
|
||||
seq_printf(m, "\ncpu MHz\t\t: %lu.%06lu/%lu.%06lu\n",
|
||||
cclk/1000000, cclk%1000000,
|
||||
sclk/1000000, sclk%1000000);
|
||||
seq_printf(m, "bogomips\t: %lu.%02lu\n"
|
||||
|
|
|
|||
|
|
@ -455,6 +455,7 @@ static struct platform_device bfin_async_nand_device = {
|
|||
static void bfin_plat_nand_init(void)
|
||||
{
|
||||
gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat");
|
||||
gpio_direction_input(BFIN_NAND_PLAT_READY);
|
||||
}
|
||||
#else
|
||||
static void bfin_plat_nand_init(void) {}
|
||||
|
|
|
|||
|
|
@ -764,7 +764,6 @@ static struct platform_device i2c_bfin_twi1_device = {
|
|||
.num_resources = ARRAY_SIZE(bfin_twi1_resource),
|
||||
.resource = bfin_twi1_resource,
|
||||
};
|
||||
#endif /* CONFIG_BF542 */
|
||||
#endif /* CONFIG_I2C_BLACKFIN_TWI */
|
||||
|
||||
#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
|
||||
|
|
|
|||
|
|
@ -312,6 +312,8 @@
|
|||
#define bfin_write_DMC0_EMR1(val) bfin_write32(DMC0_EMR1, val)
|
||||
#define bfin_read_DMC0_CTL() bfin_read32(DMC0_CTL)
|
||||
#define bfin_write_DMC0_CTL(val) bfin_write32(DMC0_CTL, val)
|
||||
#define bfin_read_DMC0_EFFCTL() bfin_read32(DMC0_EFFCTL)
|
||||
#define bfin_write_DMC0_EFFCTL(val) bfin_write32(DMC0_EFFCTL, val)
|
||||
#define bfin_read_DMC0_STAT() bfin_read32(DMC0_STAT)
|
||||
#define bfin_write_DMC0_STAT(val) bfin_write32(DMC0_STAT, val)
|
||||
#define bfin_read_DMC0_DLLCTL() bfin_read32(DMC0_DLLCTL)
|
||||
|
|
|
|||
Loading…
Reference in New Issue