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Staging: agnx: Fixup pci.c checkpatch warnings 

Signed-off-by: Erik Andrén <erik.andren@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Erik Andrén 2009-03-14 22:39:30 +01:00 committed by Greg Kroah-Hartman
parent b6da26e017
commit f58e12e4f8
1 changed files with 33 additions and 35 deletions
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68
drivers/staging/agnx/pci.c
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@ -39,34 +39,34 @@ static inline void agnx_interrupt_ack(struct agnx_priv *priv, u32 *reason)
void __iomem *ctl = priv->ctl;
u32 reg;
if ( *reason & AGNX_STAT_RX ) {
if (*reason & AGNX_STAT_RX) {
/* Mark complete RX */
reg = ioread32(ctl + AGNX_CIR_RXCTL);
reg |= 0x4;
iowrite32(reg, ctl + AGNX_CIR_RXCTL);
/* disable Rx interrupt */
}
if ( *reason & AGNX_STAT_TX ) {
if (*reason & AGNX_STAT_TX) {
reg = ioread32(ctl + AGNX_CIR_TXDCTL);
if (reg & 0x4) {
iowrite32(reg, ctl + AGNX_CIR_TXDCTL);
*reason |= AGNX_STAT_TXD;
}
reg = ioread32(ctl + AGNX_CIR_TXMCTL);
reg = ioread32(ctl + AGNX_CIR_TXMCTL);
if (reg & 0x4) {
iowrite32(reg, ctl + AGNX_CIR_TXMCTL);
*reason |= AGNX_STAT_TXM;
}
}
if ( *reason & AGNX_STAT_X ) {
/* reg = ioread32(ctl + AGNX_INT_STAT); */
/* iowrite32(reg, ctl + AGNX_INT_STAT); */
/* /\* FIXME reinit interrupt mask *\/ */
/* reg = 0xc390bf9 & ~IRQ_TX_BEACON; */
/* reg &= ~IRQ_TX_DISABLE; */
/* iowrite32(reg, ctl + AGNX_INT_MASK); */
/* iowrite32(0x800, ctl + AGNX_CIR_BLKCTL); */
}
/* if (*reason & AGNX_STAT_X) {
reg = ioread32(ctl + AGNX_INT_STAT);
iowrite32(reg, ctl + AGNX_INT_STAT);
/* FIXME reinit interrupt mask *\/
reg = 0xc390bf9 & ~IRQ_TX_BEACON;
reg &= ~IRQ_TX_DISABLE;
iowrite32(reg, ctl + AGNX_INT_MASK);
iowrite32(0x800, ctl + AGNX_CIR_BLKCTL);
} */
} /* agnx_interrupt_ack */
static irqreturn_t agnx_interrupt_handler(int irq, void *dev_id)
@ -79,7 +79,7 @@ static irqreturn_t agnx_interrupt_handler(int irq, void *dev_id)
spin_lock(&priv->lock);
// printk(KERN_ERR PFX "Get a interrupt %s\n", __func__);
/* printk(KERN_ERR PFX "Get a interrupt %s\n", __func__); */
if (priv->init_status != AGNX_START)
goto out;
@ -92,7 +92,7 @@ static irqreturn_t agnx_interrupt_handler(int irq, void *dev_id)
ret = IRQ_HANDLED;
priv->irq_status = ioread32(ctl + AGNX_INT_STAT);
// printk(PFX "Interrupt reason is 0x%x\n", irq_reason);
/* printk(PFX "Interrupt reason is 0x%x\n", irq_reason); */
/* Make sure the txm and txd flags don't conflict with other unknown
interrupt flag, maybe is not necessary */
irq_reason &= 0xF;
@ -101,13 +101,13 @@ static irqreturn_t agnx_interrupt_handler(int irq, void *dev_id)
/* TODO Make sure the card finished initialized */
agnx_interrupt_ack(priv, &irq_reason);
if ( irq_reason & AGNX_STAT_RX )
if (irq_reason & AGNX_STAT_RX)
handle_rx_irq(priv);
if ( irq_reason & AGNX_STAT_TXD )
if (irq_reason & AGNX_STAT_TXD)
handle_txd_irq(priv);
if ( irq_reason & AGNX_STAT_TXM )
if (irq_reason & AGNX_STAT_TXM)
handle_txm_irq(priv);
if ( irq_reason & AGNX_STAT_X )
if (irq_reason & AGNX_STAT_X)
handle_other_irq(priv);
enable_rx_interrupt(priv);
@ -171,7 +171,7 @@ static int agnx_alloc_rings(struct agnx_priv *priv)
len = priv->rx.size + priv->txm.size + priv->txd.size;
// priv->rx.info = kzalloc(sizeof(struct agnx_info) * len, GFP_KERNEL);
/* priv->rx.info = kzalloc(sizeof(struct agnx_info) * len, GFP_KERNEL); */
priv->rx.info = kzalloc(sizeof(struct agnx_info) * len, GFP_ATOMIC);
if (!priv->rx.info)
return -ENOMEM;
@ -210,28 +210,27 @@ static void rings_free(struct agnx_priv *priv)
#if 0
static void agnx_periodic_work_handler(struct work_struct *work)
{
struct agnx_priv *priv = container_of(work, struct agnx_priv,
periodic_work.work);
// unsigned long flags;
struct agnx_priv *priv = container_of(work, struct agnx_priv, periodic_work.work);
/* unsigned long flags; */
unsigned long delay;
/* fixme: using mutex?? */
// spin_lock_irqsave(&priv->lock, flags);
/* spin_lock_irqsave(&priv->lock, flags); */
/* TODO Recalibrate*/
// calibrate_oscillator(priv);
// antenna_calibrate(priv);
// agnx_send_packet(priv, 997);
/* calibrate_oscillator(priv); */
/* antenna_calibrate(priv); */
/* agnx_send_packet(priv, 997); /
/* FIXME */
/* if (debug == 3) */
/* delay = msecs_to_jiffies(AGNX_PERIODIC_DELAY); */
/* else */
delay = msecs_to_jiffies(AGNX_PERIODIC_DELAY);
// delay = round_jiffies(HZ * 15);
/* delay = round_jiffies(HZ * 15); */
queue_delayed_work(priv->hw->workqueue, &priv->periodic_work, delay);
// spin_unlock_irqrestore(&priv->lock, flags);
/* spin_unlock_irqrestore(&priv->lock, flags); */
}
#endif
@ -255,12 +254,12 @@ static int agnx_start(struct ieee80211_hw *dev)
goto out;
}
// mdelay(500);
/* mdelay(500); */
might_sleep();
agnx_hw_init(priv);
// mdelay(500);
/* mdelay(500); */
might_sleep();
priv->init_status = AGNX_START;
@ -280,8 +279,8 @@ static void agnx_stop(struct ieee80211_hw *dev)
/* make sure hardware will not generate irq */
agnx_hw_reset(priv);
free_irq(priv->pdev->irq, dev);
flush_workqueue(priv->hw->workqueue);
// cancel_delayed_work_sync(&priv->periodic_work);
flush_workqueue(priv->hw->workqueue);
/* cancel_delayed_work_sync(&priv->periodic_work); */
unfill_rings(priv);
rings_free(priv);
}
@ -315,7 +314,6 @@ static int agnx_config_interface(struct ieee80211_hw *dev,
spin_lock(&priv->lock);
if (memcmp(conf->bssid, priv->bssid, ETH_ALEN)) {
// u32 reghi, reglo;
agnx_set_bssid(priv, conf->bssid);
memcpy(priv->bssid, conf->bssid, ETH_ALEN);
hash_write(priv, conf->bssid, BSSID_STAID);
@ -425,7 +423,7 @@ static struct ieee80211_ops agnx_ops = {
.remove_interface = agnx_remove_interface,
.config = agnx_config,
.config_interface = agnx_config_interface,
.configure_filter = agnx_configure_filter,
.configure_filter = agnx_configure_filter,
.get_stats = agnx_get_stats,
.get_tx_stats = agnx_get_tx_stats,
.get_tsf = agnx_get_tsft
@ -505,7 +503,7 @@ static int __devinit agnx_pci_probe(struct pci_dev *pdev,
/* Map mem #1 and #2 */
priv->ctl = pci_iomap(pdev, 0, mem_len0);
// printk(KERN_DEBUG PFX"MEM1 mapped address is 0x%p\n", priv->ctl);
/* printk(KERN_DEBUG PFX"MEM1 mapped address is 0x%p\n", priv->ctl); */
if (!priv->ctl) {
printk(KERN_ERR PFX "Can't map device memory\n");
goto err_free_dev;