serial: 8250_pci: add Intel Penwell ports
Intel Penwell supports 3 HSUART ports which are 8250 compatible. The patch adds necessary bits to the driver. The functions have intel_mid_* prefix due to more than one platform will use this code. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Andy Shevchenko
Greg Kroah-Hartman
parent
2b49e0c567
commit
f549e94eff
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@ -27,6 +27,7 @@
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#include <linux/dmaengine.h>
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#include <linux/platform_data/dma-dw.h>
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#include <linux/platform_data/dma-hsu.h>
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#include "8250.h"
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@ -1525,6 +1526,148 @@ byt_serial_setup(struct serial_private *priv,
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return ret;
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}
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#define INTEL_MID_UART_PS 0x30
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#define INTEL_MID_UART_MUL 0x34
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static void intel_mid_set_termios_50M(struct uart_port *p,
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struct ktermios *termios,
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struct ktermios *old)
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{
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unsigned int baud = tty_termios_baud_rate(termios);
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u32 ps, mul;
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/*
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* The uart clk is 50Mhz, and the baud rate come from:
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* baud = 50M * MUL / (DIV * PS * DLAB)
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*
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* For those basic low baud rate we can get the direct
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* scalar from 2746800, like 115200 = 2746800/24. For those
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* higher baud rate, we handle them case by case, mainly by
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* adjusting the MUL/PS registers, and DIV register is kept
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* as default value 0x3d09 to make things simple.
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*/
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ps = 0x10;
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switch (baud) {
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case 500000:
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case 1000000:
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case 1500000:
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case 3000000:
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mul = 0x3a98;
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p->uartclk = 48000000;
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break;
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case 2000000:
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case 4000000:
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mul = 0x2710;
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ps = 0x08;
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p->uartclk = 64000000;
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break;
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case 2500000:
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mul = 0x30d4;
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p->uartclk = 40000000;
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break;
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case 3500000:
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mul = 0x3345;
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ps = 0x0c;
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p->uartclk = 56000000;
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break;
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default:
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mul = 0x2400;
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p->uartclk = 29491200;
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}
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writel(ps, p->membase + INTEL_MID_UART_PS); /* set PS */
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writel(mul, p->membase + INTEL_MID_UART_MUL); /* set MUL */
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serial8250_do_set_termios(p, termios, old);
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}
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static bool intel_mid_dma_filter(struct dma_chan *chan, void *param)
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{
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struct hsu_dma_slave *s = param;
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if (s->dma_dev != chan->device->dev || s->chan_id != chan->chan_id)
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return false;
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chan->private = s;
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return true;
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}
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static int intel_mid_serial_setup(struct serial_private *priv,
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const struct pciserial_board *board,
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struct uart_8250_port *port, int idx,
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int index, struct pci_dev *dma_dev)
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{
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struct device *dev = port->port.dev;
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struct uart_8250_dma *dma;
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struct hsu_dma_slave *tx_param, *rx_param;
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dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
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if (!dma)
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return -ENOMEM;
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tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
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if (!tx_param)
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return -ENOMEM;
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rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
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if (!rx_param)
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return -ENOMEM;
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rx_param->chan_id = index * 2 + 1;
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tx_param->chan_id = index * 2;
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dma->rxconf.src_maxburst = 64;
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dma->txconf.dst_maxburst = 64;
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rx_param->dma_dev = &dma_dev->dev;
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tx_param->dma_dev = &dma_dev->dev;
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dma->fn = intel_mid_dma_filter;
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dma->rx_param = rx_param;
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dma->tx_param = tx_param;
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port->port.type = PORT_16750;
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port->port.flags |= UPF_FIXED_PORT | UPF_FIXED_TYPE;
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port->dma = dma;
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return pci_default_setup(priv, board, port, idx);
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}
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#define PCI_DEVICE_ID_INTEL_PNW_UART1 0x081b
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#define PCI_DEVICE_ID_INTEL_PNW_UART2 0x081c
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#define PCI_DEVICE_ID_INTEL_PNW_UART3 0x081d
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static int pnw_serial_setup(struct serial_private *priv,
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const struct pciserial_board *board,
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struct uart_8250_port *port, int idx)
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{
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struct pci_dev *pdev = priv->dev;
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struct pci_dev *dma_dev;
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int index;
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switch (pdev->device) {
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case PCI_DEVICE_ID_INTEL_PNW_UART1:
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index = 0;
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break;
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case PCI_DEVICE_ID_INTEL_PNW_UART2:
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index = 1;
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break;
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case PCI_DEVICE_ID_INTEL_PNW_UART3:
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index = 2;
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break;
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default:
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return -EINVAL;
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}
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dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 3));
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port->port.set_termios = intel_mid_set_termios_50M;
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return intel_mid_serial_setup(priv, board, port, idx, index, dma_dev);
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}
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static int
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pci_omegapci_setup(struct serial_private *priv,
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const struct pciserial_board *board,
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@ -1987,6 +2130,27 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
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.subdevice = PCI_ANY_ID,
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.setup = byt_serial_setup,
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},
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{
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_PNW_UART1,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.setup = pnw_serial_setup,
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},
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{
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_PNW_UART2,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.setup = pnw_serial_setup,
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},
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{
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_PNW_UART3,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.setup = pnw_serial_setup,
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},
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{
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_QRK_UART,
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@ -2878,6 +3042,7 @@ enum pci_board_num_t {
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pbn_ADDIDATA_PCIe_8_3906250,
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pbn_ce4100_1_115200,
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pbn_byt,
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pbn_pnw,
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pbn_qrk,
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pbn_omegapci,
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pbn_NETMOS9900_2s_115200,
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@ -3644,6 +3809,11 @@ static struct pciserial_board pci_boards[] = {
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.uart_offset = 0x80,
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.reg_shift = 2,
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},
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[pbn_pnw] = {
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.flags = FL_BASE0,
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.num_ports = 1,
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.base_baud = 115200,
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},
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[pbn_qrk] = {
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.flags = FL_BASE0,
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.num_ports = 1,
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@ -5376,6 +5546,19 @@ static struct pci_device_id serial_pci_tbl[] = {
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PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
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pbn_byt },
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/*
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* Intel Penwell
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*/
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART1,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_pnw},
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART2,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_pnw},
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART3,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_pnw},
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/*
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* Intel Quark x1000
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*/
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