drm/amd/display: fixed an error related to 4:2:0/4:2:2 DSC
[Why] OPTC_BYTES_PER_PIXEL calculation for 4:2:2 and 4:2:0 could have error. [How] Change to use following formula: OPTC_DSC_BYTES_PER_PIXEL = ceiling((chunk size * 2^28) / slice width) v2: squash in 64 bit divide fix (Alex) Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Bing Guo <Bing.Guo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -61,16 +61,6 @@ static double dsc_roundf(double num)
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return (int)(num);
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}
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static double dsc_ceil(double num)
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{
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double retval = (int)num;
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if (retval != num && num > 0)
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retval = num + 1;
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return (int)retval;
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}
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static void get_qp_set(qp_set qps, enum colour_mode cm, enum bits_per_comp bpc,
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enum max_min max_min, float bpp)
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{
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@ -268,24 +258,3 @@ void _do_calc_rc_params(struct rc_params *rc,
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rc->rc_buf_thresh[13] = 8064;
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}
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u32 _do_bytes_per_pixel_calc(int slice_width,
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u16 drm_bpp,
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bool is_navite_422_or_420)
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{
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float bpp;
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u32 bytes_per_pixel;
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double d_bytes_per_pixel;
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dc_assert_fp_enabled();
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bpp = ((float)drm_bpp / 16.0);
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d_bytes_per_pixel = dsc_ceil(bpp * slice_width / 8.0) / slice_width;
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// TODO: Make sure the formula for calculating this is precise (ceiling
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// vs. floor, and at what point they should be applied)
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if (is_navite_422_or_420)
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d_bytes_per_pixel /= 2;
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bytes_per_pixel = (u32)dsc_ceil(d_bytes_per_pixel * 0x10000000);
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return bytes_per_pixel;
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}
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@ -78,10 +78,6 @@ struct qp_entry {
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typedef struct qp_entry qp_table[];
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u32 _do_bytes_per_pixel_calc(int slice_width,
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u16 drm_bpp,
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bool is_navite_422_or_420);
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void _do_calc_rc_params(struct rc_params *rc,
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enum colour_mode cm,
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enum bits_per_comp bpc,
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@ -60,31 +60,3 @@ void calc_rc_params(struct rc_params *rc, const struct drm_dsc_config *pps)
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pps->dsc_version_minor);
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DC_FP_END();
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}
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/**
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* calc_dsc_bytes_per_pixel - calculate bytes per pixel
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* @pps: DRM struct with all required DSC values
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*
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* Based on the information inside drm_dsc_config, this function calculates the
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* total of bytes per pixel.
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*
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* @note This calculation requires float point operation, most of it executes
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* under kernel_fpu_{begin,end}.
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*
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* Return:
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* Return the number of bytes per pixel
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*/
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u32 calc_dsc_bytes_per_pixel(const struct drm_dsc_config *pps)
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{
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u32 ret;
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u16 drm_bpp = pps->bits_per_pixel;
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int slice_width = pps->slice_width;
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bool is_navite_422_or_420 = pps->native_422 || pps->native_420;
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DC_FP_START();
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ret = _do_bytes_per_pixel_calc(slice_width, drm_bpp,
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is_navite_422_or_420);
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DC_FP_END();
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return ret;
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}
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@ -30,7 +30,6 @@
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#include "dml/dsc/rc_calc_fpu.h"
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void calc_rc_params(struct rc_params *rc, const struct drm_dsc_config *pps);
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u32 calc_dsc_bytes_per_pixel(const struct drm_dsc_config *pps);
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#endif
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@ -100,8 +100,7 @@ int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps, struct dsc_par
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int ret;
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struct rc_params rc;
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struct drm_dsc_config dsc_cfg;
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dsc_params->bytes_per_pixel = calc_dsc_bytes_per_pixel(pps);
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unsigned long long tmp;
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calc_rc_params(&rc, pps);
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dsc_params->pps = *pps;
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@ -113,6 +112,9 @@ int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps, struct dsc_par
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dsc_cfg.mux_word_size = dsc_params->pps.bits_per_component <= 10 ? 48 : 64;
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ret = drm_dsc_compute_rc_parameters(&dsc_cfg);
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tmp = (unsigned long long)dsc_cfg.slice_chunk_size * 0x10000000 + (dsc_cfg.slice_width - 1);
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do_div(tmp, (uint32_t)dsc_cfg.slice_width); //ROUND-UP
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dsc_params->bytes_per_pixel = (uint32_t)tmp;
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copy_pps_fields(&dsc_params->pps, &dsc_cfg);
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dsc_params->rc_buffer_model_size = dsc_cfg.rc_bits;
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