Merge tag 'drm-fixes-5.3-2019-08-07' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
drm-fixes-5.3-2019-08-07: amdgpu: - Fixes VCN to handle the latest navi10 firmware - Fixes for fan control on navi10 - Properly handle SMU metrics table on navi10 - Fix a resume regression on Stoney amdkfd: - Revert new GWS ioctl. It's not ready. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190807184221.3323-1-alexander.deucher@amd.com
This commit is contained in:
Dave Airlie
commit
f536579c14
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@ -32,7 +32,6 @@ struct amdgpu_gds {
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uint32_t gws_size;
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uint32_t oa_size;
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uint32_t gds_compute_max_wave_id;
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uint32_t vgt_gs_max_wave_id;
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};
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struct amdgpu_gds_reg_offset {
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@ -30,6 +30,7 @@
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#define AMDGPU_VCN_FIRMWARE_OFFSET 256
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#define AMDGPU_VCN_MAX_ENC_RINGS 3
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#define VCN_DEC_KMD_CMD 0x80000000
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#define VCN_DEC_CMD_FENCE 0x00000000
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#define VCN_DEC_CMD_TRAP 0x00000001
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#define VCN_DEC_CMD_WRITE_REG 0x00000004
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@ -4206,15 +4206,6 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
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unsigned vmid = AMDGPU_JOB_GET_VMID(job);
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u32 header, control = 0;
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/* Prevent a hw deadlock due to a wave ID mismatch between ME and GDS.
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* This resets the wave ID counters. (needed by transform feedback)
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* TODO: This might only be needed on a VMID switch when we change
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* the GDS OA mapping, not sure.
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*/
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amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
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amdgpu_ring_write(ring, mmVGT_GS_MAX_WAVE_ID);
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amdgpu_ring_write(ring, ring->adev->gds.vgt_gs_max_wave_id);
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if (ib->flags & AMDGPU_IB_FLAG_CE)
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header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
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else
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@ -4961,7 +4952,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
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5 + /* HDP_INVL */
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8 + 8 + /* FENCE x2 */
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2, /* SWITCH_BUFFER */
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.emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_gfx */
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.emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
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.emit_ib = gfx_v10_0_ring_emit_ib_gfx,
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.emit_fence = gfx_v10_0_ring_emit_fence,
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.emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
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@ -5112,7 +5103,6 @@ static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
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default:
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adev->gds.gds_size = 0x10000;
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adev->gds.gds_compute_max_wave_id = 0x4ff;
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adev->gds.vgt_gs_max_wave_id = 0x3ff;
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break;
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}
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@ -1321,6 +1321,39 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
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return 0;
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}
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static int gfx_v8_0_csb_vram_pin(struct amdgpu_device *adev)
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{
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int r;
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r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
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if (unlikely(r != 0))
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return r;
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r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
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AMDGPU_GEM_DOMAIN_VRAM);
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if (!r)
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adev->gfx.rlc.clear_state_gpu_addr =
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amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
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amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
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return r;
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}
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static void gfx_v8_0_csb_vram_unpin(struct amdgpu_device *adev)
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{
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int r;
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if (!adev->gfx.rlc.clear_state_obj)
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return;
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r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
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if (likely(r == 0)) {
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amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
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amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
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}
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}
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static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
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{
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amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
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@ -4785,6 +4818,10 @@ static int gfx_v8_0_hw_init(void *handle)
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gfx_v8_0_init_golden_registers(adev);
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gfx_v8_0_constants_init(adev);
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r = gfx_v8_0_csb_vram_pin(adev);
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if (r)
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return r;
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r = adev->gfx.rlc.funcs->resume(adev);
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if (r)
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return r;
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@ -4901,6 +4938,9 @@ static int gfx_v8_0_hw_fini(void *handle)
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else
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pr_err("rlc is busy, skip halt rlc\n");
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amdgpu_gfx_rlc_exit_safe_mode(adev);
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gfx_v8_0_csb_vram_unpin(adev);
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return 0;
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}
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@ -1485,7 +1485,7 @@ static void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
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amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0));
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amdgpu_ring_write(ring, 0);
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amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
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amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1);
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amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
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}
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/**
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@ -1498,7 +1498,7 @@ static void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
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static void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
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{
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amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
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amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1);
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amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1));
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}
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/**
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@ -1543,7 +1543,7 @@ static void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64
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amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
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amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
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amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1);
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amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE << 1));
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amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0));
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amdgpu_ring_write(ring, 0);
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@ -1553,7 +1553,7 @@ static void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64
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amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
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amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1);
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amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP << 1));
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}
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/**
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@ -1597,7 +1597,7 @@ static void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring,
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amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
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amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1);
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amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_REG_READ_COND_WAIT << 1));
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}
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static void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
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@ -1626,7 +1626,7 @@ static void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
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amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
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amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1);
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amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG << 1));
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}
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/**
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@ -2079,6 +2079,36 @@ static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev,
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return 0;
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}
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static int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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uint32_t tmp = 0;
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unsigned i;
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int r;
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WREG32(adev->vcn.external.scratch9, 0xCAFEDEAD);
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r = amdgpu_ring_alloc(ring, 4);
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if (r)
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return r;
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amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
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amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
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amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
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amdgpu_ring_write(ring, 0xDEADBEEF);
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amdgpu_ring_commit(ring);
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for (i = 0; i < adev->usec_timeout; i++) {
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tmp = RREG32(adev->vcn.external.scratch9);
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if (tmp == 0xDEADBEEF)
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break;
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DRM_UDELAY(1);
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}
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if (i >= adev->usec_timeout)
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r = -ETIMEDOUT;
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return r;
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}
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static int vcn_v2_0_set_powergating_state(void *handle,
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enum amd_powergating_state state)
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{
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@ -2142,7 +2172,7 @@ static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = {
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.emit_ib = vcn_v2_0_dec_ring_emit_ib,
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.emit_fence = vcn_v2_0_dec_ring_emit_fence,
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.emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
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.test_ring = amdgpu_vcn_dec_ring_test_ring,
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.test_ring = vcn_v2_0_dec_ring_test_ring,
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.test_ib = amdgpu_vcn_dec_ring_test_ib,
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.insert_nop = vcn_v2_0_dec_ring_insert_nop,
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.insert_start = vcn_v2_0_dec_ring_insert_start,
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@ -1567,32 +1567,6 @@ copy_from_user_failed:
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return err;
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}
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static int kfd_ioctl_alloc_queue_gws(struct file *filep,
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struct kfd_process *p, void *data)
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{
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int retval;
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struct kfd_ioctl_alloc_queue_gws_args *args = data;
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struct kfd_dev *dev;
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if (!hws_gws_support)
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return -ENODEV;
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dev = kfd_device_by_id(args->gpu_id);
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if (!dev) {
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pr_debug("Could not find gpu id 0x%x\n", args->gpu_id);
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return -ENODEV;
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}
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if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS)
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return -ENODEV;
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mutex_lock(&p->mutex);
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retval = pqm_set_gws(&p->pqm, args->queue_id, args->num_gws ? dev->gws : NULL);
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mutex_unlock(&p->mutex);
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args->first_gws = 0;
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return retval;
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}
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static int kfd_ioctl_get_dmabuf_info(struct file *filep,
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struct kfd_process *p, void *data)
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{
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@ -1795,8 +1769,6 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = {
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AMDKFD_IOCTL_DEF(AMDKFD_IOC_IMPORT_DMABUF,
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kfd_ioctl_import_dmabuf, 0),
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AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_QUEUE_GWS,
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kfd_ioctl_alloc_queue_gws, 0),
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};
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#define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls)
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@ -315,6 +315,8 @@ int smu_get_power_num_states(struct smu_context *smu,
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int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
|
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void *data, uint32_t *size)
|
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{
|
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struct smu_power_context *smu_power = &smu->smu_power;
|
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struct smu_power_gate *power_gate = &smu_power->power_gate;
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int ret = 0;
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|
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switch (sensor) {
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@ -339,7 +341,7 @@ int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
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*size = 4;
|
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break;
|
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case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
|
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*(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT) ? 1 : 0;
|
||||
*(uint32_t *)data = power_gate->vcn_gated ? 0 : 1;
|
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*size = 4;
|
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break;
|
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default:
|
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|
|
|
|||
|
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@ -451,6 +451,7 @@ struct smu_dpm_context {
|
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struct smu_power_gate {
|
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bool uvd_gated;
|
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bool vce_gated;
|
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bool vcn_gated;
|
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};
|
||||
|
||||
struct smu_power_context {
|
||||
|
|
|
|||
|
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@ -502,6 +502,8 @@ static int navi10_store_powerplay_table(struct smu_context *smu)
|
|||
|
||||
static int navi10_tables_init(struct smu_context *smu, struct smu_table *tables)
|
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{
|
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struct smu_table_context *smu_table = &smu->smu_table;
|
||||
|
||||
SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
|
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PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
|
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SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
|
||||
|
|
@ -516,9 +518,35 @@ static int navi10_tables_init(struct smu_context *smu, struct smu_table *tables)
|
|||
sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
|
||||
AMDGPU_GEM_DOMAIN_VRAM);
|
||||
|
||||
smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
|
||||
if (!smu_table->metrics_table)
|
||||
return -ENOMEM;
|
||||
smu_table->metrics_time = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int navi10_get_metrics_table(struct smu_context *smu,
|
||||
SmuMetrics_t *metrics_table)
|
||||
{
|
||||
struct smu_table_context *smu_table= &smu->smu_table;
|
||||
int ret = 0;
|
||||
|
||||
if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
|
||||
ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
|
||||
(void *)smu_table->metrics_table, false);
|
||||
if (ret) {
|
||||
pr_info("Failed to export SMU metrics table!\n");
|
||||
return ret;
|
||||
}
|
||||
smu_table->metrics_time = jiffies;
|
||||
}
|
||||
|
||||
memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int navi10_allocate_dpm_context(struct smu_context *smu)
|
||||
{
|
||||
struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
|
||||
|
|
@ -577,20 +605,27 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
|
|||
|
||||
static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
|
||||
{
|
||||
struct smu_power_context *smu_power = &smu->smu_power;
|
||||
struct smu_power_gate *power_gate = &smu_power->power_gate;
|
||||
int ret = 0;
|
||||
|
||||
if (enable) {
|
||||
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
/* vcn dpm on is a prerequisite for vcn power gate messages */
|
||||
if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
|
||||
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
power_gate->vcn_gated = false;
|
||||
} else {
|
||||
ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
|
||||
if (ret)
|
||||
return ret;
|
||||
if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
|
||||
ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
power_gate->vcn_gated = true;
|
||||
}
|
||||
|
||||
ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, enable);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -598,15 +633,10 @@ static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
|
|||
enum smu_clk_type clk_type,
|
||||
uint32_t *value)
|
||||
{
|
||||
static SmuMetrics_t metrics;
|
||||
int ret = 0, clk_id = 0;
|
||||
SmuMetrics_t metrics;
|
||||
|
||||
if (!value)
|
||||
return -EINVAL;
|
||||
|
||||
memset(&metrics, 0, sizeof(metrics));
|
||||
|
||||
ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics, false);
|
||||
ret = navi10_get_metrics_table(smu, &metrics);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
@ -894,8 +924,9 @@ static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)
|
|||
if (!value)
|
||||
return -EINVAL;
|
||||
|
||||
ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics,
|
||||
false);
|
||||
ret = navi10_get_metrics_table(smu, &metrics);
|
||||
if (ret)
|
||||
return ret;
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
@ -914,10 +945,7 @@ static int navi10_get_current_activity_percent(struct smu_context *smu,
|
|||
if (!value)
|
||||
return -EINVAL;
|
||||
|
||||
msleep(1);
|
||||
|
||||
ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
|
||||
(void *)&metrics, false);
|
||||
ret = navi10_get_metrics_table(smu, &metrics);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
@ -956,10 +984,9 @@ static int navi10_get_fan_speed_rpm(struct smu_context *smu,
|
|||
if (!speed)
|
||||
return -EINVAL;
|
||||
|
||||
memset(&metrics, 0, sizeof(metrics));
|
||||
|
||||
ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
|
||||
(void *)&metrics, false);
|
||||
ret = navi10_get_metrics_table(smu, &metrics);
|
||||
if (ret)
|
||||
return ret;
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
@ -1307,7 +1334,7 @@ static int navi10_thermal_get_temperature(struct smu_context *smu,
|
|||
if (!value)
|
||||
return -EINVAL;
|
||||
|
||||
ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics, false);
|
||||
ret = navi10_get_metrics_table(smu, &metrics);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
|
|||
|
|
@ -1391,7 +1391,7 @@ smu_v11_0_smc_fan_control(struct smu_context *smu, bool start)
|
|||
{
|
||||
int ret = 0;
|
||||
|
||||
if (smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
|
||||
if (!smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
|
||||
return 0;
|
||||
|
||||
ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, start);
|
||||
|
|
|
|||
|
|
@ -410,21 +410,6 @@ struct kfd_ioctl_unmap_memory_from_gpu_args {
|
|||
__u32 n_success; /* to/from KFD */
|
||||
};
|
||||
|
||||
/* Allocate GWS for specific queue
|
||||
*
|
||||
* @gpu_id: device identifier
|
||||
* @queue_id: queue's id that GWS is allocated for
|
||||
* @num_gws: how many GWS to allocate
|
||||
* @first_gws: index of the first GWS allocated.
|
||||
* only support contiguous GWS allocation
|
||||
*/
|
||||
struct kfd_ioctl_alloc_queue_gws_args {
|
||||
__u32 gpu_id; /* to KFD */
|
||||
__u32 queue_id; /* to KFD */
|
||||
__u32 num_gws; /* to KFD */
|
||||
__u32 first_gws; /* from KFD */
|
||||
};
|
||||
|
||||
struct kfd_ioctl_get_dmabuf_info_args {
|
||||
__u64 size; /* from KFD */
|
||||
__u64 metadata_ptr; /* to KFD */
|
||||
|
|
@ -544,10 +529,7 @@ enum kfd_mmio_remap {
|
|||
#define AMDKFD_IOC_IMPORT_DMABUF \
|
||||
AMDKFD_IOWR(0x1D, struct kfd_ioctl_import_dmabuf_args)
|
||||
|
||||
#define AMDKFD_IOC_ALLOC_QUEUE_GWS \
|
||||
AMDKFD_IOWR(0x1E, struct kfd_ioctl_alloc_queue_gws_args)
|
||||
|
||||
#define AMDKFD_COMMAND_START 0x01
|
||||
#define AMDKFD_COMMAND_END 0x1F
|
||||
#define AMDKFD_COMMAND_END 0x1E
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue